A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based in-Memory Computing

Omar Numan, Martin Andraud and Kari Halonen

Noise Modeling Using Look-up Tables and DC Measurements for Cryogenic Applications

Giovani Crasby Britton Orozco, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mickael Casse and Philippe Galy

A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter

Muhammad Jawad Shakil, Uzair Ahmad, Jafar Hussain, Hassan Saif and Rashad Ramzan

Look Before You Leap: an Access-Based Prudent Page Migration for Hybrid Memories

Aishwarya Gupta, N S Aswathy and Hemangee K. Kapoor

FPGA-Implementation Techniques to Efficiently Test Application Readiness of Mixed-Signal Products

Gabriel Rutsch, Konrad Maier and Wolfgang Ecker

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors

Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant and Rainer Leupers

A Two-Layer Connected Component Algorithm for Target Extraction Using K-Means and Morphology

Dheemanth Joshi, Aniket Gangotri, Sai Pranay Chennamsetti, Gautham Bolar, Ganesan Thiagarajan and Sanjeev Gurugopinath

A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer

Junjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang and Fengyi Huang

Mapping of CNNs on Multi-Core RRAM-Based CIM Architectures

Rebecca Pelke, Nils Bosbach, Jose Cubero, Felix Staudigl, Rainer Leupers and Jan Moritz Joseph

Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications

Sagheer Ahmed, Jayesh Ambulkar, Debabrata Mondal and Ambika Prasad Shah

Accelerating Large Kernel Convolutions with Nested Winograd Transformation

Jingbo Jiang, Xizi Chen and Chi-Ying Tsui

FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs

Klajd Zyla, Marco Liess, Thomas Wild and Andreas Herkersdorf

REMOTE: Re-Thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

Rafael Medina Morillas, Darong Huang, Giovanni Ansaloni, Marina Zapater and David Atienza

Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies

Mihai Sanduleanu, Mizan Gebremicheal and Solomon Serunjogi

Experiments in Power Side Channel Attacks: DPA and CPA on AES-128

Esrat Khan, Amal Alhashmi and Ibrahim Elfadel

A Deterministic Parallel Routing Approach for Accelerating Pathfinder-Based Algorithms

Umair F. Siddiqi, Gary Grewal and Shawki M. Areibi

GPU Vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results

Abhinav Agarwal and Guoping Wang

A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test

Paolo Bernardi, Giorgio Insinga and Nima Kolahimahmoudi

Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators

Safiullah Khan, Ayesha Khalid, Ciara Rafferty, Yasir Ali Shah, Maire O'Neill, Wai Kong Lee and Seong Oun Hwang

ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference

Imlijungla Longchar and Hemangee Kapoor

An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal on-Chip Memory Access

Yi Chen, Jie Lou, Christian Lanius, Florian Freye, Johnson Loh and Tobias Gemmeke

PR-PUF: a Reconfigurable Strong RRAM PUF

Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana and Anupam Chattopadhyay