ABSTRACT. IoT or « Internet of Things », recognized as the future massive extension of "M2M", will become one of the major markets of the following years and is going to bring incredible revolutions in industrial, and generally speaking, human activities, like energy, resource management, necessary replacement of programmed obsolescence by predictive maintenance or "on demand improvements" of machines, health care improvements, optimized agriculture...etc...

For those revolutions to come true, beyond necessity of other ongoing breakthrough on materials, nano-tech, or sensors, the IoT telecom revolution itself needs to be a reality. This is the big challenge. Because an unprecedented density of devices, at very low cost, with outstanding needs for autonomy, that humanity will have to "forget" along their service after "dissemination" on the field, will require a complete "flip-over" of the philosophy that has been dominating in the telecom industry for 100 years, with a culminating point in modern radiotelephony and internet.

Networks are today massively forcing their "administrated" modems to be highly disciplined (in frequency or modulation accuracy, time synchronization...) before they can negotiate a single bit of data. For a working IoT world, networks will need to be switched to "highly cognitive", with a high capacity to dynamically adapt to the various behavior of the disseminated devices they will have to "serve", through massively parallel Software Defined principles. "Networks at the service of free devices" : A true historic revolution in telecoms in fact !

Those philosophy changes will have unprecedented consequences on the modem's properties that will be embedded in those famous "objects", and thus will have consequences on hardware as well as software components from which they will be built. By cascade effect, consequences on SoC definition and design, will not be of minor importance…

ABSTRACT. An adaptive control mechanism to improve the efficiency of magnetically coupled resonators (MCRs) used in wireless power transmission is presented. The proposed system is capable of dynamically adjusting the capacitance of MCRs, hence, the resonance frequency of the transmitter (TX) and receiver (RX) coils in response to variations of transmission distance. The control unit operates in a self-sufficient manner through rectifying a portion of the AC signal present on TX and RX coils. A proof-of-concept circuit is designed in a 0.13 m CMOS technology and simulation results confirm the validity of the proposed scheme.

ABSTRACT. This paper presents an algebraic attack on a chaos-based "true" random bit generator (RBG). A clone system is proposed to analyze the security weaknesses of the RBG and its convergence is proved using master slave synchronization scheme. Secret parameters of the RBG are revealed where the only information available are the structure of the RBG and a scalar time series observed from the chaotic oscillator. Simulation and numerical results verifying the feasibility of the clone system are given. The RBG doesn't fulfill Diehard and NIST-800-22 statistical test suites, not only the next bit but also the same output bit stream of the RBG can be reproduced.

ABSTRACT. This paper presents the modeling of a sensor mote energy consumption together with the battery state-of-charge for wireless sensors network(WSN) using SystemC and the analog/mixed signal(AMS) extension. This model is intended to be employed in the simulation of WSN composed from few to several nodes. The energy consumption of the whole mote device has been described as a finite state machine with SystemC, which was characterized from a measured mote. The battery was modeled in SystemC-AMS and was implemented for an alkaline battery to describe its state-of-charge and the nonlinear behaviour of the voltage source. For illustration, a WSN composed of ZigBee motes, which is actually employed for the monitoring of dissolved oxygen, pH and temperature in water for shrimp farming, is presented.

ABSTRACT. Recent neural models defined by neuro-scientists exhibit interesting properties for bio-inspired computing in embedded and autonomous systems: distributed computing, unsupervised learning, self-adaptation, self-organisation, tolerance... But these properties only emerge from large scale and fully connected neural maps that result in intensive computation coupled with high synaptic communications. We study in this paper in what extend these complex models can be simplified and deployed in hardware accelerators compatible with an embedded integration onto mobile robots. We propose a Neural Processing Unit designed as a programmable accelerator implementing recent equations close to self-organizing maps and neural fields and validated onto FPGA devices.

ABSTRACT. The main objective of this study is to determine the impact of a co-designed small antenna on linear power amplifier (PA) performances. Special attention is paid to load–pull optimization to derive suitable values of the antenna input impedance at the operating frequency and the first higher-order harmonics. The impact of the antenna impedance profile in the operational band on PA performance is also addressed. It is found that the PA is more linear, when its operating frequency is below the antenna resonance, compared to other configurations.

ABSTRACT. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required to save power without limiting processing performances. Our solutions is to rely on the integration of Non-Volatile Memories within complex computing systems. In this paper, we describe a fully embedded hybrid System-on-Chip (SoC) and discuss the benefits of embedding NVM in terms of power consumption and functionality enhancements compared to an equivalent system relying on volatile memory blocks. Our methodology goes from the conception of the memory cell up to the benchmarking of the architecture in a hybrid magnetic/CMOS low-power technology. We present precise pre-silicon performance estimations using benchmarks based on compression algorithms.

ABSTRACT. This paper presents new TSV-Based applications such as resonant inductive coupling, variable Inductor, power amplifier, bandpass filter, and antenna. The Resonant Inductive Coupling system increases the amount of magnetic flux linked between coils and improves the power transmission significantly. In addition, TSV is used to construct transformer-coupled power amplifier. A new architecture for on-chip bandpass filters, based on TSV technology. This architecture is the first in literature. According to the simulation results, the TSV-based bandpass filter has an insertion loss of 1.5 dB at 90 GHz and 20 GHz passband from 80 to 100 GHz. TSV are also used to build an antenna on high resistivity substrate. The proposed antenna is centered at 90 GHz with 20 GHz bandwidth.

ABSTRACT. This paper presents a broadband high-Q tunable negative inductor based on a gyrator topology. In order to reduce the risk of instability and to increase circuit bandwidth, simple inverters are used as transconductance amplifier. A complete stability analysis and careful circuit design details using SOI 180 nm technology are presented. Post-layout simulations results show a negative inductance variation from -24 nH to -13.7 nH. For a bandwidth from 10 MHz to 1 GHz, inductance value error remains under 12.5 %. Circuit power consumption is 16 mW; and area consumption is 120 μm by 84 μm.

ABSTRACT. The bimetallic strip heat engines are thermal energy harvesters that have been designed to convert low-grade heat flux due to local thermal gradients, into mechanical energy by using the thermo-mechanical instability of bimetallic membranes. Great efforts must be done on the modeling of these heat engines in order to understand their way of working. This paper is a contribution to these efforts since it proposes approximate analytical expressions of the efficiencies of these heat engines and figures of merit to compare bimetallic beams.

ABSTRACT. Predicting the timing behaviour of modern computer architectures can be extremely difficult. Probabilistic Timing Analysis (PTA) is a recent technique to compute the execution time of a program within a given confidence interval, but requires specially designed hardware with certain properties. This work address the implementation of a probabilistically analyzable L1 instruction and data cache for the Ion MIPS32 processor on FPGA. We developed a random placement and replacement policy that fulfills all the requirements for PTA. Our experiments show that the cache fulfills all the requirements for PTA, and program timing can be determined with arbitrary accuracy. In addition, random placement and replacement improve the observed WCET from 6% to 19% w.r.t. a Least Recently Used policy.

ABSTRACT. A phase-coupled low noise, low power ring-based VCO for use in multi-GHz PLLs is presented. The building blocks of the RO design are discussed with a technique to expand the VCO to a variety of phases and frequencies without the use of inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive-element injection locking of the staged phases via a network of symmetrically placed metal interconnect capacitors. A 0.8-to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process. The proposed quadrature VCO occupies an area of 0.0024mm^2, consumes a power of 0.88mW at a 1.0V supply, and has a 123.5dBc/Hz phase noise at the 10MHz offset for a carrier of 25.0GHz.

ABSTRACT. We present initial experimental results of our low–power RF energy harvester that includes a charge pump, voltage regulator and a bandgap voltage reference in CMOS 130nm technology. The DC regulator designed for RF IC energy harvesting applications and optimized for powering implantable electronics.The internal circuit sections work with the local power supply voltage levels in the 1.5–1.9V range (worst case), and the 6.28μW bandgap generates 459mV DC reference voltage. The complete regulator consumes typically 23.5μW for its own operation while delivering regulated VPWR = 0.97V DC voltage.

ABSTRACT. This paper presents a new power management circuit for electrostatic vibration energy harvesting devices. Compared to most of the existing electronic interfaces dedicated to electrostatic vibration energy harvesting, this circuit presents three main advantages. Firstly, it does not include any inductive element, making possible drastic miniaturization. Secondly, the switch control does not need to be synchronized with the mechanical motion of the electrostatic device and thirdly, the energy conversion cycle is self-maximized and does not require any optimization algorithm, enabling thus simple, ultra-low power implementation of the circuit.

ABSTRACT. This paper presents an airflow energy harvester coupling (i) fluttering phenomena to turn airflows kinetic power into mechanical oscillations of a flexible membrane and (ii) an electret-based electrostatic converter to turn the resulting mechanical oscillations into electricity. The device is able to work down to 5.5m/s and harvests up to 330µW at 9m/s. It has been combined to a self-starting battery-free power management circuit to supply a Bluetooth Low Energy temperature sensor node, validating the complete Energy Harvesting chain. The power management circuit implements the Synchronous Electric Charge Extraction technique with a flyback architecture; it has a conversion efficiency reaching 60% and consumes about 1.2µA.

ABSTRACT. The high demand of low-power radio transceivers for the Internet of Things drives the design of innovative wireless architectures. As a solution, we propose to dynamically optimize the receiver performance jointly with the power consumption, in order to reach a low-margin operating mode. For this purpose, we have developed an IEEE 802.15.4 Digital Baseband (DBB) with a tunable subsampling mechanism built-in. This paper describes the design and the hardware implementation of a low-complexity controller for managing this adaptive system. It explains the basic methodology and points out some practical considerations for a robust and efficient implementation. As a result, the paper shows the impact of the controller design on the baseband power consumption.

ABSTRACT. In this paper, we discuss the increase of the SET state resistance distribution dispersion in Phase Change Memory (PCM) based on innovative materials, namely Ge-rich Ge2Sb2Te5 (GST). A new programming technique, which consists in linearly decreasing the temperature in the active region of the memory device, is studied and a circuit capable of generating the desired pulse is presented and simulated. Post-layout simulations demonstrate the functionality of the circuit and its potential to be used for the programming of PCM cells based on alternative-to- GST materials.

ABSTRACT. In this paper, the spectral-domain approach has been used as an efficient method to investigate the dispersive properties of anisotropic multilayered microwave circuits with arbitrary polarization of the optical axis. The analysis is based on Galerkin’s method via an adequate choice of basis functions while the spectral dyadic Green’s functions have been derived via a recursive algorithm. The proposed approach was demonstrated through successful comparison with data available in the literature.

ABSTRACT. Air traffic is likely to double in the next decade, and current systems will not be able to support the resulting increase in the aeronautical communications; and hence there is a need of new reliable and high speed communication system for air-to-ground (A/G) communications. Two candidate systems for the proposed L-band Digital Aeronautical Communications System (L-DACS), namely L-DACS1 and LDACS2, are being developed for future A/G communications. In this paper we propose a fast filter bank (FFB)-based channelizer for L-DACS1. We show that use of FFB enables simultaneous extraction of up to eight L-DACS1 channels (frequency bands), with 49% to 85% savings in number of multipliers over conventional methods and faster filtering operation without compromising on the filtering performance.

ABSTRACT. A linear constant current light-emitting diode (LED) driver without off-chip inductor and capacitor is presented in this paper. The proposed driver consists of one resistor, one diode bridge and one controller integrated circuits (IC). The controller IC employs four LED strings and sequences their conduction to shape the output current in proportion to the input voltage. The controller IC was designed and implemented by using HHNEC 1μm 700V process. The experimental results show that high PF of 97.93% and efficiency of 90.41% under the input voltage of 220V|rms utility voltage were obtained.

ABSTRACT. Modern embedded systems favor the chip multiprocessor frame to achieve higher performance, but are restricted by the inefficient cache hierarchies. Typically, the accessing interference and improper allocation in last-level cache (LLC) cause significant energy consumption and performance depression. In this paper, we propose a configurable and partitioned cache mechanism to well manage the LLC. This mechanism utilizes the repeated behaviors of hot subroutines to explore the optimal allocations. Thus, we can provide each core with such allocation information to partition the LLC during runtime. Experimental results in a quad-core system using the SPEC2006 benchmarks show that the cache access energy can be reduced by on average 32.5 percent compared to the equal partition scheme.

ABSTRACT. In this paper, a general circuit scheme for noise-tolerant logic design based on MRF theory and Differential Cascode Voltage Switch (DCVS) technique has been proposed, which is an extension of the work in [3], [4]. A DCVS block with only four transistors has been successfully inserted to the original circuit scheme from [3] and extensive simulation results based on HSPICE show that our proposed design can operate correctly with the input signal of 1dB SNR. When using the Kullback-Leibler Distance (KLD) [5] as the evaluation parameter, the KLD value of our design decreases by 76:5% on average than [3] which means that superior noise immunity could be obtained through our work.

ABSTRACT. In this paper, the impact of variations on the most representative pulsed flip-flops topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.

ABSTRACT. Oscillators are needed in many systems for time keeping. In low duty cycle systems, such as wireless sensors, such oscillators may incur a significant portion of system power consumption. Extensive research exists in making on-chip oscillators low power. However, the other part of the time keeping function, that of computing the number of oscillation cycles, is normally not treated. This paper describes research that focuses on developing oscillators with an innate capability of counting its own oscillation cycles, suitable for direct use as time-keeping devices. The functional correctness of solutions based on asynchronous counters and matched delays are demonstrated and a number of designs are characterized in terms of oscillation frequency and working ranges.

ABSTRACT. Local variations are increasingly important in new technologies. This paper presents the design of adaptive circuits based on the concept of Adaptive Body Bias Islands and a Forward and Reverse Body Bias Generator for FDSOI technology. The proposed Body Bias generator design, based on a DLL, allows a 70% area reduction compared to the DAC-based conventional design and reduces local variability by 85%. This closed loop implementation also allows to track runtime variations.

ABSTRACT. The performance of FinFET-based FPGA cluster is evaluated with technology scaling for channel length from 20nm down to 7nm showing the scaling trends of basic performance metrics. The impact of threshold voltage variation, considering die-to-die variations, on the delay, power, and power-delay product is reported after the simulation of a 2-bit adder benchmark. Simulation results show an increasing trend of the average power and power-delay product variations with threshold voltage as we go down with technology node. Unlike the average power and power-delay product, the delay is showing the least percentage of variations with threshold voltage at the most advanced node of 7nm.

ABSTRACT. In this paper, a time-integration based passive quenching – active recharge circuit for Geiger-mode avalanche diodes has been proposed with the aim of minimizing the avalanche charge and providing a hold-off time tunable within wide range. These are indeed important features to be taken into account in the design of the avalanche diode quenching - reset electronics. Furthermore a hold-off time tunable within a wide range is typically desirable in every application where a full characterization of the device dark count is required. A correct operation of the proposed circuit, designed in a commercial High-Voltage CMOS 0.35um technology, is assessed through SPICE simulations as well as Monte Carlo analysis in the Cadence Environment.

ABSTRACT. Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency performances are severely reduced by the 1/f noise. We recently proposed a theoretical study which confirm the capability of the spinning current technique to lower the 1/f noise on Low-Voltage VHD. In this paper, we proposed a practical way for the implementation of this technique. Experimental results bring out significant improvements. An offset of 0.1 mT and a resolution of 37 µT has been measured over a 1.6 kHz bandwidth.

ABSTRACT. This paper presents a fully Digital Pixel Sensor (DPS) front-end with a focus on the optimization of its operation and temperature dependence. The system relies on a new type of photodetector based on a hybrid MOS-PN structure displaying intrinsic light-to-time conversion. The photodetector as well as its front-end circuit are described as well as pulsed operation techniques that increase the Signal to Noise Ratio (SNR). The presented pulsed operation of the photodetector behaves as a direct light-to-digital conversion. Temperature dependence and its variation with bias conditions are theoretically and experimentally studied.

ABSTRACT. The present work proposes an improved PSPICE implementation of the equivalent electrical model of silicon photomultipliers (SiPMs) to simulate and predict their transient response to avalanche trigger events. In particular, the developed model provides a detailed investigation of magnitude and timing of the read-out signals and can therefore be exploited to perform reliable circuit-level simulations. The modeling approach used is strictly related to the physics of each basic microcell constituting the SiPM device, and allows the avalanche timing as well as the photodiode current and voltage to be accurately simulated. Predictive capabilities of the proposed model are demonstrated by means of experimental measurements on a real detector. Versatility of the proposed model is also confirmed

ABSTRACT. we present the performance characteristics of a Single Photon Avalanche Detector fabricated in a 180 nm standard CMOS image sensor technology. The SPAD implemented in 8 different diameters between 5 µm and 40 µm shows a DCR below 10 KHz at 15°C a with a low afterpulsing probability (0.2% at 300 mV) a good photodetection efficiency (20%) and a very good time resolution (85 ps at 405 nm).

ABSTRACT. This paper presents the methodology for selecting the architecture and optimizing the circuit design for the first block in a current-mode receiver chain, the low noise transconductance amplifier (LNTA). This methodology includes system-level considerations to select circuit design techniques for noise cancellation, linearity improvement and power reduction. The methodology is applied on an LNTA design in 28nm UTBB-FDSOI CMOS. The selected amplifier topology is designed to operate at 2.4GHz with a transconductance of 15mS. It achieves 2.67dB noise figure (NF), 1dB compression point (P1dB) of -7dBm, 9.5dBm input third order intercept point (IIP3) and consumes 1.5mA from a 1.2V supply.

ABSTRACT. This paper presents an inductorless 2.41GHz ISM receiver, consisting of a feedback LNA and an IQ VCO-mixer, designed for low area and low power in a 130nm CMOS technology. The VCO is based on an IQ cross-coupled RC relaxation VCO using active load coupling, which reduces area and power consumption in comparison to the commonly used soft-limiter coupling. The mixing function is incorporated in the VCO, benefiting from an increased gain. The LNA is based on a shunt-shunt topology, where feedback is used for input impedance matching and gain desensitization. The LNA works both as amplifier and VCO-mixer’s current mirror, further reducing the power consumption. The receiver has a gain of 22.26dB and a noise figure of 7.98dB, occupying 0.145mm2 and consuming 7.58mW from a 1.2V supply.

ABSTRACT. An envelope elimination and restoration (EER) transmitter that comprises a class-E PA and a current DAC modulator is presented. A switched capacitor DAC controls an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. This allows for increased filtering of the quantization noise that is problematic in digital PAs (DPA). The system measurements yield a peak output power and power added efficiency (PAE) of 22.5 dBm and 23.6%, respectively. When applying a WCDMA signal, the measured EVM is 1.32% and the adjacent channel power ratio (ACPR) is -37.9 dBc, while outputting 19.9 dBm at 14.3% PAE. For an LTE signal, the measured EVM is 3.72% and the ACPR is -30.2 dBc, while outputting 18.1 dBm at 10.6% PAE.

ABSTRACT. A low-voltage low-power CMOS ZigBee receiver front-end supporting 780/868/915/2400MHz bands is presented in this paper. The wideband common-gate (CG) low noise amplifier (LNA) and the I/Q current-commutating mixer are merged in a single circuit, sharing the bias current. Active trans-conductance (gm) boosting technique is utilized in the design of the presented receiver front-end. Post-layout simulation results for 180nm RF CMOS implementations show the conversion gain is 26.5dB at 780/868/915MHz bands and 19.5dB at 2400MHz band. The minimum simulated NF is 6.5dB. The receiver front-end consumes 830μW from a 1V DC supply and the active size of core circuit is 0.0276mm2.

ABSTRACT. IEEE 802.11ad (WiGig) is an emerging multi-Gb/s wireless standard in the unlicensed 60GHz spectrum. This work presents system level validation of a Single Carrier (SC), QPSK modulated WiGig transmitter based on a semi-digital Finite Impulse Response (FIR) Digital-to-Analog Converter (DAC). The 1.76GS/s complex baseband input signal is upsampled by two to a clock frequency of 3.52GHz. In order to introduce channel shaping and meet the standard requirements, the structure implements a 16th-order direct-form Root-Raised Cosine (RRC) FIR filter. Transmit mask and EVM requirements are met with a large margin while allowing a 14% random mismatches on the current sources implementing the FIR DAC coefficients.

ABSTRACT. In urban sensor networks, the diversity of propagation conditions can lead to the simultaneous reception of signals having very different power levels. Given the diversity of wireless technologies used in this area, implementing gateways using a Software-Defined Radio (SDR) approach seems to be a very practical solution. Overcoming the large dynamic range may however require a very high resolution Analog-to-Digital Converter (ADC) to digitize the weakest signal with a satisfying precision. One possibility to relax this requirement is to use a companding technique before digitization. This paper describes how to use an additive companding approach to reduce ADC’s complexity and proposes two implementations of the compressing law.

ABSTRACT. The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissipation and dynamic element matching. System level simulations indicate at a Q-factor of 75 Δ-Σ modulator with a 3-level quantizer achieves dynamic ranges of 106, 82 dB and 84 dB for RFID, TETRA, and Galileo over bandwidths of 200 kHz, 10 MHz and 40 MHz respectively.

ABSTRACT. This paper presents a novel digital phase-locked loop (DPLL) with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter clock. The hybrid analog/digital PI control mitigates a TDC quantization noise and reduces the deterministic jitter (DJ). Moreover, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of its negative feedback loop. We design the proposed DPLL in 130 nm technology. The proposed low jitter DPLL shows 4.3 psec of DJ and 12.5 psec of RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz.

ABSTRACT. An analysis of the cycle slipping behavior of a bang-bang phase locked loop (PLL) far from its lock provides expressions for the pull-in frequency range. Behavioral simulation is used to validate the analytical results which estimate the pull-in range at least 40% more accurately than prior work.

ABSTRACT. In this paper the effect of colored clock jitter on audio continuous-time ΣΔ modulators is studied. The results demonstrate the importance of using the correct model for the jitter on the clock signal, especially when it is generated by a phase-locked loop, as it is the case in most audio applications. The paper demonstrates that the popular clock signal model with white jitter noise spectrum leads to worse ΣΔ modulator performance than a more realistic model with colored jitter noise spectrum. Indeed, such a model allows the designer to obtain more reliable simulation results, in order to choose the most suitable architecture and size correctly the circuit components to achieve the desired design target, leading to power consumption and area optimization.

ABSTRACT. An EMI-resisting MOSFET-Only Voltage Reference is herein proposed, based on the MOSFET Zero Temperature Coefficient (ZTC) vicinity condition. The ZTC condition is analytically derived through a continuous MOSFET model that is valid from weak to strong inversion and a design methodology is proposed. The final circuit was designed in a 130 nm process and occupies around 0.0075 mm2 of silicon area while consuming just 10.3 μW. Post-layout simulations presented a Voltage Temperature Coefficient (VTC) of 146 ppm/oC, for a temperature range from −55 to +125oC. An EMI source of 4 dBm (1 V amplitude) injected in the power supply of our circuit, according to the Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of 24 % and 11m Vpp, respectively.

ABSTRACT. A bandgap voltage reference that operates from a power supply of 0.6 V is presented in this paper. The circuit is based on an all-CMOS implementation that allows operation below the base-emitter voltage limit by eliminating parasitic vertical bipolar-junction-transistors. Low-voltage design techniques are deployed to design an op-amp that obviates the need for a start-up circuit. The design was implemented in 65 nm CMOS technology. The measured reference voltage is 275 mV with an average temperature coefficient of 176 ppm/◦C from -50◦C to 80◦C without trimming. The circuit consumes 62 μW of power and occupies 0.011 mm2 of chip area.

ABSTRACT. In this paper we present a sizing methodology to make the cross coupled inverter based delay cell supply insensitive. The delay cell is used to design a three phase supply insensitive oscillator with an output frequency range of 2.4 - 65MHz for a control voltage range of 0.5V to 1.2V over a supply range of 1.2 - 1.8V. The power consumption in this range was found to be between 360nW and 13 micro-watt. Further analyses of the oscillator characteristics are presented. The oscillator was simulated in LFoundry 150nm process in Cadence Tools.

ABSTRACT. Abstract— In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal. Post-layout Simulation results for the proposed circuit implemented in a 0.18-µm 1P6M CMOS technology confirm that the power consumption of this circuit is able to operate over a wide range of the input voltages from 50 mV to 1.8 V, and a wide range of frequencies from 100 Hz to 100 MHz. For both a 0.4 V and a 1.8V supply voltages, the proposed circuit has a propagation delay of 10.43 ns and a power consumption of 9.89 nW for a 10-kHz input signal.

ABSTRACT. Abstract—this paper describes the implementation of a high-output current charge pump with passive level shifters, aiming the reliable driving of internal active switches. The technique described here enables the use of both high-density integrated MIM capacitors with low breakdown voltage, and active switches (MOS transistors) allowing provide surface efficient integration. In addition, capacitor area optimization methodology and feedback control allowing to generate constant output voltage are discussed. The 10MHz charge pump was integrated in 0.5μm CMOS process. Thanks to the extra epitaxial trench isolation, 18V output voltage is reached, with the output current ranging up to 280μA. The target application is the quadrature/frequency compensation of a 3-axis vibratory MEMS Gyroscope.

ABSTRACT. In this paper, we consider extending the refresh period of gain-cell based dynamic memories beyond the worst-case point of failure, assuming that the resulting errors can be tolerated when the use-cases are in the domain of inherently error-resilient applications. For example, we observe that for various data mining applications, a large number of memory failures can be accepted with tolerable imprecision in output quality. In particular, our results indicate that by allowing as many as 177 errors in a 16 kB memory, the maximum loss in output quality is 11%. We use this failure limit to study the impact of relaxing reliability constraints on memory availability and retention power for different technologies.

ABSTRACT. Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error tolerant applications involving perceptive or statistical outputs. This paper reviews two established techniques applicable to adders and multipliers: circuit pruning and carry speculation. A critical comparative study is carried out considering several error metrics.

ABSTRACT. Manufacturing, environmental, and workload variabilities lead to timing errors in digital circuits, that are avoided by conservative guardband. In this paper, we develop a scalable model for timing error prediction for a given pipelined circuit. The model is generated through a supervised learning approach that considers workload and hardware variations. We train and test our model on gate level simulations. We further assess the robustness of our modeling approach by changing different parameters that affect structural and electrical properties of the modeled circuit. Our model predicts the timing errors with an average accuracy of 95%. Approximate computing applications can utilize our model for a wide range of 0%–15% guardband reduction while satisfying their reliability specifications.

ABSTRACT. Near-threshold computing in CMOS is a promising alternative to achieve higher energy efficiencies for applications which can tolerate very wide voltage-frequency scaling. This paper proposes methods to design circuits for a wide range of VFS, and targets near-threshold. A standard-cell based methodology for near-VT is demonstrated in the paper. We show 10X energy/operation savings for applications that tolerate ultra-wide frequency scaling in their operating modes.The extremely low and highly-variable performance at sub- and near-VT have to be addressed by new design paradigm. In this work we show the use of logic design of approximate adders to reduce energy and timing performance up to 19.4% and 36.7%, respectively in a class of FIR filters without compromising their frequency response.

ABSTRACT. Stochastic Computing (SC) with random bit streams has been used to replace binary radix encoding. SC-based logic circuits take advantage of area minimization, fast and accurate operation and inherent fault tolerance. In this paper, the stochastic characteristics inherent in STT-MT bring on an innovative stochastic number generator circuit. The hybrid MOS-MTJ process allows to design a 4T1M structure with 1.98μm*1.46μm layout area, using 28 nm ultra thin body and buried oxide fully depleted silicon-on-insulator technology. A case study of designed SNM is performed by polynomial function synthesis, which significantly reduces area. The proposed circuit also takes advantage of non-volatility and infinite endurance from STT-MTJ, which can be applied to reliability-aware circuits and systems.