ABSTRACT. The Internet of Things (IoT) is a vision born from the convergence between embedded and networking technologies. It refers to the interconnection of uniquely identifiable embedded computing devices within the existing Internet infrastructure. Things can refer to a wide variety of devices such as heart monitoring implants, biochip transponders, automobiles with built-in sensors, field operation devices, smart thermostat and home appliances. They are equipped with sensors, actuators and microcontrollers which can provide the “real-time” embedded processing that is a key requirement of most IoT applications. The collected data are made available through a unified networking infrastructure, to users and interconnected machines. Furthermore, they can be processed and analyzed by the cloud for decision-making in order to respond to changes quickly and accurately, to predict events and optimize resources. We shortly discuss the IoT vision and its feasibility. We show that its achievement challenges our capacity to design mixed hardware-software systems that are trustworthy and optimal. We advocate the need for rigorous system design techniques. We present the current state of the art and discuss three major scientific problems: 1) linking physicality and computation; 2) component-based systems engineering; 3) intelligence in particular as the ability of system adaptation in order to meet given requirements in the presence of uncertainty. Achieving the IoT vision will have a tremendous societal, technological and scientific impact. In particular, it will reinvigorate Computing and enrich the discipline with new scientific foundations.

ABSTRACT. An ultra low power frequency synthesizer was designed and implemented in 130 nm CMOS technology. Based on integer-N phase locked loop architecture, the frequency synthesizer operates from 13.8 to 61 MHz. Current consumption has been minimized by the use of a mix of analog and digital blocks and a prior planning of current distribution amongst each blocks. The measured phase noise is -89.6 dBc/Hz @ 500 kHz offset and the current consumption is 77 uA from 1.2V supply at 32 MHz output. The reference frequency of 1 MHz is generated from an on-chip RC based oscillator whose output frequency varies by only ±0.025% when temperature varies between -10°C to 110°C.

ABSTRACT. A voltage mode transmitter that detects data transitions and enables a high frequency boost for the output signal is presented. The transmitter utilizes a passive high pass filter to detect input data transitions and increase the output amplitude by turning on additional NMOS and PMOS transistors only when the data is changing. In HSPICE simulations, the transmitter is capable of equalizing a 20 Gbps PRBS7 signal through a channel that has a loss of 9dB. It achieves a differential eye-opening amplitude of 194mVppd and an eye-opening of 0.988 UI. The transmitter is designed using 28nm CMOS process and uses a 1V supply voltage. It consumes 7mW of at-speed power.

ABSTRACT. A charge pump with excellent current matching in a wide dynamic range is proposed. It is aimed to be used in state of the art frequency synthesizers. The key concept is the direct equation of currents, instead of indirectly equating transistor voltages, using the current following action of a second generation current conveyor. The proposed design exhibits both static and dynamic high performance characteristics in terms of very low DC current mismatch, of the order of 0,05%, and suppressed transient glitches. Both these non-idealities degrade performance of PLLs inducing reference spurs and phase offset, and thus must be minimized. The proposed circuit is implemented in TSMC 65nm process and simulation results demonstrate performance in a wide output voltage range from 100mV to 950mV.

ABSTRACT. A novel integrate and dump receiver for clock signals is presented. The integrate and dump topology is known to be power efficient, but depends on a external clock signal. Here, we introduce a topology that auto generates the dump signal and hence can be used as a clock receiver. The proposed architecture is of special interest for optical clock channels as it accepts short pulses as input signal. This allows big power savings by using pulsed lasers for clock generation in place of continuous wave lasers and optical modulators. The proposed receiver includes inherent duty cycle control and outputs. Finally, the proposed topology is compared to classical approaches and is found to be the most power efficient solution in terms of overall optical link power consumption.

ABSTRACT. In this paper we model phase noise and spurious tones (spurs) for a fractional-N phase-locked loop (PLL) with static phase offset. The phase detector (PD) input-output characteristic around the bias point is approximated by a parabolic function. Using a MATLAB code, phase noise spectrum and fractional spurs are calculated as a function of slope and curvature of the PD characteristic. The dependence of the PLL output spectrum on PD nonlinearity and rms phase error at the PD input is discussed and compared with theoretical results. A close agreement with theoretical predictions is observed.

ABSTRACT. This paper presents a novel power-constrained algorithmic design methodology for radiofrequency (RF) low-noise amplifiers (LNAs). The methodology is based on matrix descriptions of the transistors allowing for the first time the derivation of exact synthesis equations for input impedance matching and transducer gain optimization. The equations are embedded in an algorithm for design tradeoffs between noise performance and gain. In particular, the synthesis equations are derived for the cascode topology with inductive degeneration. The methodology is validated through the design of a 2-mW 2.45-GHz LNA in a predictive 90 nm CMOS technology.

ABSTRACT. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs(VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the electrical parameters and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulation, with a good agreement in accuracy and speed-up factor of 60.000 &7.000 for 2nd and 3rd order PLL is achieved.

ABSTRACT. Quasi-Delay insensitive (QDI) circuits are the most robust and practical circuits that can be built and are resilient to process, temperature and voltage variations. This paper proposes a novel energy and cost efficient synthesis scheme to translate any Boolean functions into 4-phase handshaking QDI circuits with hybrid dual-rail (DR) and 1-of-4 (OOF) encoding signals. Preliminary experimental results in FPGAs indicate significant cost and energy reduction over DR DIMS design.

ABSTRACT. Simulation of higher order nonlinear device currents in RF integrated circuits becomes crucial when high linearity is a design goal. Prediction of the nonlinear behavior of passive circuits like mixers, attenuators or switches play an important role in low-distortion designs, but also causes trouble due to the inability of threshold voltage based compact models to inherently model higher order nonlinearities around zero drain-source voltage. This paper introduces a systematic workaround enabling the designer to receive qualitative higher order simulation data around that important operating point when there is no access to one of the advanced surface potential or inversion charge based transistor models.

ABSTRACT. Modern integrated circuits generate very high heat fluxes that can lead to a high temperature, degrading the performance and reducing the life time of the device. Thermal simulation is used to prevent this kind of issues, and many models were introduced in recent years. However, their validation is challenging: it is either based on established simulators (with reduced accuracy), or requires to produce a specific test chip with several thermal sensors. In this paper we propose a methodology and measurement setup that uses existing commercial processors to validate thermal models. We use infrared thermography and low-cost thermoelectric cooling, avoiding the issues of mineral oil setups used in previous works. We show how our approach was used to validate two thermal simulators.

ABSTRACT. About some years ago, several biometric technologies are considered mature enough to be a new tool for security and ear-based person identification is one of these technologies. In this paper, we propose an efficient online personal identification system based on ear images. Based on Gabor filter response, three ear features have been used in order to extract different and complementary information. Several combinations are tested in the fusion phase in order to achieve a better identification accuracy. The obtained experimental results show that the system yields the best performance for identifying a person and it is able to provide the highest degree of biometrics-based system security.

ABSTRACT. This work explores different means to implement software defined cellular radio over the cloud, which sets stringent real-time requirements. DPDK and MKL are two technologies proposed by Intel that can be used for that purpose. In this paper, we explore those technologies and using operating system isolation to reduce the computation time variability for LTE processes. It is found that MKL offers excellent performance, but as it is not scalable by itself over the cloud, combining it with DPDK is a very promising alternative. DPDK allows improving performance, memory management and makes MKL scalable.

ABSTRACT. The recent High Efficient Video Coding (HEVC) standard introduces a new interpolation filter for fractional-pixel motion estimation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are area- and power-efficient operators that are applied when intermediate additions are not required, which is the case for interpolation filters. This work employs various hierarchical adder compressor structures in the interpolation filter datapaths of a state-of-the-art HEVC interpolation filter architecture. Hardware design results show that datapaths using adder compressors reduce power by up to 15% and power delay product by up to 30% compared to the same filters with ripple-carry adders.

ABSTRACT. a 7 ps/LSB, 0.02mm2 and 3.9mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL). Multiple ring oscillators with unique and variable frequencies are used in order to make N independent measurements of the time pulse to be measured M times in order to create transmitter and receiver diversity similar to those in MxN MIMO antenna arrays. Targeted for wired applications, the design favors portability and flexibility by using standard cells and digital design flow.

ABSTRACT. This paper presents a design of a True Random Number Generator (TRNG) using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. Since the probability of the STT-MTJ-based TRNG is locked using a digitally controlled feedback loop, the sensitivity of the feedback gain can be reduced greatly, which eliminates a high-gain amplifier. It is demonstrated using the circuit simulator (NS-SPICE where the STT-MTJ model is established using 90nm CMOS/MTJ process technologies) and MATLAB that the random sequences generated from the TRNG become 50%, where the gain of signal converters in the probability-locked loop is the precision of at most 9bit.

ABSTRACT. This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC elements, each modeling a finite length increment of the line. Inductors are then emulated by a gyrator-capacitor combination, yielding a classical transconductor-capacitor (gm-C) circuit, suitable for integration. The validity of this approximation is discussed in the context of fault location in power networks. It is shown that a simple analog implementation can locate the fault within 1% accuracy with a significant speed advantage over classical computational methods, reducing the processing time to less than 100ms.

ABSTRACT. This work presents a new method for kTC noise calculation in periodic switched capacitor circuits. Two basic applications are overviewed. Namely the switched capacitor lowpass filter and the N-path band-pass filter. Analytical noise calculation using the new method is performed for both examples. The obtained analytical results are confirmed with SpectreRF Pnoise analysis and ELDO transient noise simulations.

ABSTRACT. A fully monolithic coupled differential Voltage-Controlled-Oscillators (VCOs) network for phased-array applications is presented in this paper. The proposed integrated VCO array, operating at 5.78 GHz is implemented on a 0.25 µm BiCMOS SiGe process and is made of two LC-NMOS differential VCOs coupled through a MOS transistor. At 2.5 V power supply voltage, and a power dissipation of 62.5 mW, the coupled VCO array features a measured best case phase noise of -125.21 dBc/Hz at 1 MHz frequency offset from a 5.78 GHz carrier.

ABSTRACT. In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall- or rise-time on the impedance transformation behavior of N-path filters.It is shown that clock skew and finite clock fall- or rise-time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with these effects present, the performance and filtering characteristics of the filter are altered. Finally, a technique has been introduced by means of which a specific harmonic fold-back component can be canceled by proper choice of clock timing.

ABSTRACT. Embedded electronic system for tactile data processing captures the attention of recent researchers because of its importance in many domains. Machine learning based on tensorial kernel approach has proven its effectiveness in processing tactile information. Computing tensorial kernel corresponds to computing the singular value decomposition. This paper presents an FPGA implementation of singular value decomposition for tensorial kernel computation. The design is implemented for an arbitrary m×n matrix with fixed point arithmetic. The results figure out a tradeoff between the accuracy of computation and the input data resolution. The experimental results demonstrate the efficiency of our design by increasing the accuracy of computation and by providing comparable results in terms of time.

ABSTRACT. This paper proposes the synthesis of approximate adders to save area and energy of FIR filters implemented in CMOS. All savings are in addition to the improvements obtained on previously optimized digital FIR filters. Digital FIR filters are largely used in multimedia systems which can tolerate levels of approximations in the arithmetic dataflow. Our work deals with different levels of approximation in ripple carry adders which are part of the filters implemented in hardware. Our results show that the effort to explore area and energy savings in low power optimized circuits through the approximate computing approach is validated with area and energy reductions up to 18.8% and 15.5% respectively, thus enabling energy-efficiency without compromising the SNR of recorded 16-bit audio signals.

ABSTRACT. A power efficient hardware architecture implementing a Split-Radix Fast Fourier Transform (SRFFT) is developed through pruning unnecessary computations. The new architecture of a configurable SRFFT processor is first devised and then the architecture is developed further so that unnecessary computations, which yield zeros at the output, are pruned. This is done through stalling butterfly computations with appropriate use of a pruning matrix. The proposed processor may find applications in orthogonal frequency division multiplexing (OFDM) communication transceivers. The processor is implemented on a field-programmable gate array (FPGA) and simulations show that maximum power saving of around 20% is achieved when computing 1024 point Fourier transform of signals with very sparse spectrum.

ABSTRACT. The paper presents an approach based on the curve fitting method for the design of non-iterative divider circuits with accuracy and area-delay product (ADP) trade-offs. The curved surfaces representing the quotient are partitioned into several regions, each of which is approximated by a square/triangular plane. The planes are obtained by using the curve fitting method for accuracy optimization. The proposed architecture for implementing the planes contains only simple arithmetic operations and a look-up table. Several non-iterative dividers with different accuracies and ADPs are obtained. The accuracy achieved in terms of the maximum absolute error percentage (MAEP) ranges from 1.87% to 0.14%. The MAEP of 0.14% is 30% better than the one achieved by the best existing non-iterative divider.

ABSTRACT. In this paper, we describe an LSI implementation and the measurement results of a 4×4-bit multiplier which has an ultra-low power dissipation characteristic. The proposed multiplier uses an ultra-low power technique which combines adiabatic logic and a subthreshold circuit. The output functionality and power consumption of the fabricated LSI chip at a 1 kHz frequency and 0.6 V peak voltage operation are measured and compared with conventional static CMOS and subthreshold static CMOS.

ABSTRACT. This paper describes a novel frequency compensation method for a low dropout regulator (LDO). The proposed load tracking-zero compensation circuit not only eliminates the need for a bulky external off-chip capacitor that is typically employed in conventional compensation techniques, but also consumes very low additional quiescent current (less than 1 pA) that makes this method highly suitable for integrated SoC power management applications. It is demonstrated that this compensation technique, designed for the LDO in 130-nm technology, improves the stability and enhances the load regulation of the low dropout regulator.

ABSTRACT. This work describes an ultra low power three chip system that harvests RF energy for sensing applications. The input RF power levels are typically lower than −6dBm. Our scheme uses two commercially available chips; a DC-DC boost converter and a low power micro-controller. In this paper we present the design of a third chip that compliments these to form a complete system. This chip includes an RF-DC rectifier, low power analog to digital converter (ADC) and a resistor emulation circuit (REC). While the REC helps in enhancing the efficiency of the boost converter, the ADC replaces the one present in the micro-controller and reduces the operating power requirements. The chip is designed in standard 0.18µm CMOS process technology.

ABSTRACT. This paper presents a new control technique for maximum power delivery of solar energy harvesting systems. The study is based on finding a relationship between the charge pump optimum frequency and the solar cell optimum voltage that delivers the maximum power of the solar cell. The goal of the control unit is to match this frequency-voltage relationship without sensing circuits. The solar model used maximally delivers 1.5 mW, VOC is below 550 mV. The harvester should deliver a 1.2 V supply voltage. The control unit consists of an 8-bit SAR ADC converter, exponential decoder and a digitally-controlled oscillator. The control unit power consumed is below 120 uW. The power efficiency reaches 43.6% at 975 uW available solar power. The technology used for simulations is GF 65 nm.

ABSTRACT. The lack of high power conversion efficiency in RF passive rectifier circuits at sub-μW power levels with current MOSFET technologies is directly related with the difficulty of the transistors in conducting the required level of current at low voltage values. With a different carrier injection mechanism, the superior electrical characteristics of the Tunnel FET devices at low voltage values (sub-0.25 V) can outperform the process of energy conversion at ultra-low power, thus improving the operation range of RF energy harvesting circuits. In this work, a simulation study on the doping profile and material selection of Tunnel FET devices shows the impact of device properties in rectifier circuit efficiency.

ABSTRACT. This paper presents a power management circuit implementing a Synchronous Electric Charge Extraction on piezoelectric energy harvesters and based on a flyback architecture. The novelty of this circuit lies in its ability to handle multiple energy harvesters operating at different frequencies and different output voltages with a single and standard flyback coupled inductor. The power harvested by the various scavengers is stored in a single and mutual storage capacitor. By construction, the power management circuit is capable of dealing with high input voltages (>100V). Its power consumption is about 1.15µA@3V per energy harvester and its conversion efficiency reaches 83%; its good operation has been validated by simulations and experiments on two vibration energy harvesters.

ABSTRACT. In this work, a novel technique for ultrasound imaging named Computational Ultrasound has been developed. The computational ultrasound imaging operation involves sending and receiving unfocused echo pulses which are spatio-temporally apodized with random binary sequences. The single channel of acquired RF data is then decoded using convex optimization to obtain the image. The proposed system reduces or eliminates side lobes and speckle noise while providing good image quality only for a fraction of the cost and area of a conventional ultrasound system. Simulations show that computational ultrasound can successfully image sub-wavelength features at the expense of image quality.

ABSTRACT. Recently, new tools have been developed which simultaneously take care of circuit sizing and layout generation. However, they either suffer from long run times or limited accuracy of the utilized parasitic model. This paper presents a complete layout-aware design automation tool for analog circuits. The proposed tool combines a simulation-based circuit sizing tool with a templatebased layout generation tool. The layout-induced parasitics are automatically extracted via a commercially available extractor. To reduce the run time cost originating from parasitic extraction, a two step methodology is followed, where infeasible solutions are prohibited from costly extraction process.

ABSTRACT. Computational video multi-camera systems allow novel applications such as stereo-vision and view interpolation. The computational- as well as communication and storage requirements for real-time multi-camera video are huge. High quality stereo- and view interpolation applications require the accurate combination of detailed image features in two or more cameras. The use of lossy video compression algorithms often lowers the accuracy of small details and textures that are probably not noticable by a human viewer, but that are crucial in disparity calculations, matching, video stitching and 3D model synthesis. This paper makes a quantitative comparison of two lossless video compression methods.

ABSTRACT. Conventional CMOS technologies require high production costs, which are largely due to masks production and high specification equipment. Interestingly, conjugated polymers and plastic semiconductors offer potential substitutes to lower the production cost. Such materials can be used in applications such as organic light-emitting diodes (OLEDs), organic field-effect transistors (OFETs), and organic photovoltaics (OPVs). However, electrical reliability, and especially potential damage by electrostatic discharge (ESD), is a major issue in the production cycle and cost, and also during operation. Here we present investigation of the ESD sensitivity of OFETs based on poly (3-hexylthiophene-2,5-diyl) (P3HT), which has so far received little or no attention in the literature.

ABSTRACT. Supply voltage scaling has become an important low power technique to reduce the power consumption of sub-nanometer technologies. Instead of supplying same magnitude of Vdd for the whole chip, multi-Vdd and Dynamic Voltage Scaling (DVS) have been advocated for the enhanced power efficiency at the cost of added complexity. In this paper, we present a low area, low power on-chip DC-DC converter suitable for low power Wireless Sensor Network (WSN) nodes. This converter offers the flexibility to perform micro-level DVS for various blocks of the system. Peak efficiency of 90% has been achieved and the proposed DC-DC converter takes utmost delay of 30us to switch between the different output voltages.

ABSTRACT. This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. They allow significant reduction of 25% in the memory and cost reduction of 56% in the check-node unit architecture with respect to the baseline. Implementation results on Xilinx Virtex 6 FPGA device show that they can achieve a decoding throughput between 1.95 and 2.41Gbps for 20 decoding iterations (48% to 83% increase with respect to OMS), while providing decoding performance close to the OMS decoder, despite the impreciseness introduced in the processing units.

ABSTRACT. In this paper, the bandwidth enhancement of planar type electromagnetic bandgap (EBG) structure using dissipative edge termination technique is investigated. Two termination schemes are presented; first with the termination along edges of every single EBG patches and second with termination along edges of the whole power plane. In the first case, simulations show that, both lower and upper cutoff frequency is improved for wideband suppression of simultaneous switching noise (SSN). For the second one lower cutoff frequency is shifted downward from 800MHz to 13MHz. which results in relative bandwidth of 63% higher than the commonly used EBGs. For fast simulation and validation of full-wave simulation, the circuit model of this structure is developed and simulation results are also presented.

ABSTRACT. In this paper we propose a digital blind calibration scheme for Time-Interleaved ADCs based on transfer function mismatch which corrects gain, time-skew and bandwidth mismatch errors. The esti- mation of mismatches uses an adaptive filtering struc- ture and the compensation is based on the development of a matrix approach to cancel the effect of mismatches. The algorithm was tested with a two-channel 14-bits ADCs board and the results show the effectiveness of the technique.

ABSTRACT. Reducing test costs of analog and RF circuits is a complex challenge, which intuitive solution is to reduce test time. However, such reduction usually leads to a egradation of measurement accuracy not easy to handle when no model is available to understand the impact of the reduction. This work presents a method to evaluate the impact of test time reduction on yield accuracy, using only measured values and easy-to-obtain uncertainty models. The results proposed by this method provide a balance between test time reduction and yield accuracy. The proposed method is applied on the SNR measurement evaluation and provides a reduction of measurement time based on the yield precision evaluation.

ABSTRACT. The radio frequency network on chip (RFNoC) is proposed as a solution to the network on chip issue. The maximizing of the number of the communication paths is required to increase the aggregate throughput. According to the configuration of the RFNoC and the organization of the repartition of the available spectral resources, the quality of the signal may be influenced. An analysis of the effect of the repartition of the spectral resources on the signal to noise ratio of the signal exchanged in the radio frequency network on chip is described in the content of this paper, where the final purpose is the optimizing of the overall throughput. When the signal to noise ratio is significantly deteriorated, some solutions are proposed to improve the quality of the transmissions.

ABSTRACT. A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply

ABSTRACT. Microwave imaging is recognized as a potential candidate for biomedical applications, such as breast cancer detection. In this context a miniature antenna is used for quantitative imaging of inhomogeneous tissues. Microwave breast imaging (MBI) uses low power and longer wavelength signals to obtain information about breast tissues, and promises a safer and more accurate modality for regular breast scanning. This paper presents a miniature microstrip antenna that can be placed in contact with the breast model to investigate the presence of malignant tissues. A miniature antenna has been designed, and placed toward a breast phantom model with inhomogeneous tissues.

ABSTRACT. A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 1080p FPS or 30 4K FPS. To the best of our knowledge, it outperforms all hardware solutions existing in the literature.

ABSTRACT. This paper deals with the study of a new correction structure for the compensation of distortions in direct digitization receiver. In that purpose a modified post- distortion algorithm using an efficient adaptive filter is used. Performance have been demonstrated on measurements from both a state of the art wideband TI-ADC and from an entire RX receiver. The algorithm improves the SFDR by ~25dB on a two tones signal with a TIADC and ~16dB on a DVB-T channel with a direct digitization receiver.

ABSTRACT. In this paper we describe the space grade camera we developed for the Polarimetric and Helioseismic Imager (PHI)instrument of the Solar Orbiter (SO) mission. The camera, called Correlation Tracking Camera (CTC) will be part of the Image Stabilization System (ISS) used to compensate the spacecraft jitter. Since the ISS works on a correlator basis, the CTC requires a high frame rate while keeping the power consumption as low as possible. The CTC works at a nominal frame rate of 414 fps for 128 pixels square images with a latency below the microsecond. The images have a 10 bit resolution and the tests shows an effective number of bits (ENOB) above 9.3. Also, the full ISS closed-loop has been successfully tested with this camera.

ABSTRACT. We present a novel single-carrier frequency division multiple access transceiver based on Discrete Cosine Transform Type-I (DCT1). We show the kind of redundancy (as prefix and suffix)that must be appended into each data symbol to be transmitted, and also the symmetry to be imposed on the channel impulse response, so that the channel matrix is diagonalized. Moreover, we show how the channel equalization can be carried out by means of a bank of scalars obtained through the DCT1 of a filter-right-half derived from the symmetric channel impulse response. This study is completed with several computer simulations.

ABSTRACT. In this work, the mixed-signal differentiator technique for the compensation of excess loop delay has been extended to counteract the effect of the finite GBW of the amplifiers. A RZ DAC is utilized to realize a fast compensation path from the quantizer output to the input of the last integrator. After proper tuning of the scaling coefficients, the original NTF of the modulator can be restored, which has been verified in a 3rd order, single-bit single-loop CT Delta-Sigma modulator. By using the modified compensation technique, the GBW requirements on the amplifiers can be relaxed significantly while maintaining the SQNR performance and the modulator stability. Consequently, the power consumption of the amplifiers can be drastically reduced.

ABSTRACT. This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency.

ABSTRACT. In wireless multihop transmission, there is a data transmission method called as cooperative transmission which exploits spatial diversity by transmitting signals from source (S) node via relay (R) nodes and then combining the direct and relay transmissions at the destination (D) node. In this study, the location of relay nodes in between source node and destination node are set as the manipulated variable, and the BER is calculated to find out the best location to place the relay nodes.

ABSTRACT. The transmission of waveforms through optical fiber usually results in some waveform distortion. To smoothen this distortion, digital finite-impulse response (FIR) filters are commonly employed. However, digital FIR filters require a relatively large area for digital signal processing (DSP), so an analog FIR filter is adopted. The overall architecture is implemented by employing gilbert cells and inverters using a 28-nm fully depleted silicon on insulator (FD-SOI) process with 1.0-V supply voltage.

ABSTRACT. In recently years, power supply which has fast transient response is required by systems employing LSIs. Hysteresis mode control is well known as a control scheme of power supply for fast transient response but its switching frequency changes following the input voltage fluctuation. In this paper, a design example based on the Constant On Time (COT) control is examined. Theoretically the switching frequency with COT control does not depend on the input voltage. Compared to the conventional hysteresis control, fluctuation of the switching frequency can be suppressed.

ABSTRACT. This paper proposes the design scheme of direct sampling mixer (DSM) by which unallowable amplitude characteristics due to aliases spreading over relatively broad band is suppressed. It is pointed out that the periodic frequency characteristic of a stage processing decimated signal causes decrease of attenuation in the stopband of the DSM, and an IIR section with a low decimation rate is employed as the first stage. A DSM the amplitude characteristic of which falls into the spectrum mask for IEEE 802.11 is designed as an example. Simulation results show that the designed DSM satisfies specification widely in not only the passband but also the stopband. It is confirmed that gradual decimation approach or use of a non-decimated section for the first stage is effective.

ABSTRACT. Impedance matching between transmission lines and parasitic capacitors of MOSFETs is necessary for high-frequency circuits including the analog FIR filter. Reactive elements are inserted in parallel with gate-source and drain-source capacitors to match impedances. This paper clarifies that large parasitics result in high sensitivity on the reflection coefficient. It is proved that a single inductor brings the lowest sensitivity.

ABSTRACT. Voltage-controlled oscillators (VCOs) are used in high frequency circuit. In LC-VCOs, noise dependence is not very serious, and inductors and MOS varactor are designed as variable capacitance by performing simulations. In this paper, we aim to improve the variable frequency range of these devices .

ABSTRACT. This paper reports human body detection while walking in an indoor environment using SISO-UWB radar system. Reflection of the human body is detected from the impulse response using inverse Fourier transform of S21 frequency characteristics between transmitting and receiving antennas. A trace of moving body can be confirmed when the sweep time of signals is shorten than the speed of walking. In this study, not only human body detection while walking but also walking speed of subject can be estimated. It was measured by the point that divides the frequency into 101 or 201 samples. In each case, it was conducted 5 ways while walking speed was changed. It was compared the speed that really walked and the speed that was measured by experiments. When the point is 101, it was measured that errors of the speed that really walked was small.

ABSTRACT. In this study, we examined the communication performance between base stations using intermediate relay stations mounted on unmanned aerial vehicles to form a temporary network in the event of a disaster. A link budget analysis of the uplink and downlink was performed. The communication performance was evaluated when error correction codes were used to meet the required bit error rate for the desired data rate. The received power fluctuated when parameters, such as the distance between the base station and the aerial vehicle, were varied. The adequacy of the desired communication performance from the received power was evaluated.

ABSTRACT. A differential amplifier based on logic circuits is suitable to design requirement of low-voltage operation and recent fine CMOS design technologies for digital LSI. In this paper, design of two digital-based differential circuits, one of which is implemented with discrete components and another is on an IC chip, are presented and verified through their applications to voltage follower. From their measurement results, there still remains room for investigation and design consideration of that kind of circuits.

ABSTRACT. Low voltage circuits can be realized by using subthreshold metal-oxide semiconductor field- effect transistors MOSFETs. However, it is necessary to consider their sensitivity to changes in temperature. A low-voltage circuit connects the gate terminal to a bulk terminal basic circuit, which connects the bulk terminal to the source terminal using subthreshold MOSFET current mirrors. The purpose of this study is to improve the temperature characteristics of the low-voltage current mirrors using subthreshold P-MOSFETs by changing the area of the source.

ABSTRACT. A simple simulation model of distance properties of the received power is studied for a 920-MHz-band indoor sensor network. For comparison with the model, the received power was measured for an RSSI with a terminal based on the IEEE802.15.4g standard. Distance properties of the received power can be expressed by the simple simulation model.

ABSTRACT. Ultra-thin body and BOX (UTBB) fully-depleted SOI (FDSOI) has emerged as an alternative to bulk and finFET technologies. The main goal of this work is to validate the FDSOI technology behavior for Low Power applications. During the past few years, the main driver for FDSOI were the efficient digital systems. This work is one of the first FDSOI research done in the RF domain.

ABSTRACT. The goal of this work is to evaluate UTBB FDSOI technology for energy-efficiency in the design of digital VLSI systems. The evaluation was done in three phases: first phase contains detailed exploration of the technology and its specific digital implementation flow; in second phase, energy-optimization methodologies were studied across various levels of digital design hierarchy; highly efficient fully-integrated body-bias generator was implemented in the third phase, along with on-chip run-time optimization algorithm.

ABSTRACT. Disruptive remote sensing and detection technologies are crucial to meet the needs of emerging applications that requires the development of innovative wireless devices and architectures. Such detection schemes should operate at low power in support of high sensitivity and reliability. These parametric specifications are becoming important for environment-sensitive applications such as biomedical and health-care sectors. Various radar technologies have recently been demonstrated for monitoring vital signs such as respiration and/or heartbeat. In a different context, such bio-radar systems can also be designed to monitor area security or search and rescue of survivors after disasters such as earthquake. In this case, such RF systems must be capable of providing two functions, namely vital signal measurement and physical positioning of survivor. Conventional radar techniques for vital signal monitoring are generally based on the operation of a single carrier frequency. In such systems, Doppler technique is used to extract ribcage movement and vital signs. With the constraints of Doppler transceivers, the re-configurability of system architectures is a promising solution. On the other hand, the aggregation of multiple carriers or harmonics leads to the development of new radar techniques. In our case, a so-called harmonic radar scheme (f and nf) can offer several advantages over most conventional radar techniques for monitoring vital signs. This frequency diversity-based harmonic radar can improve system sensitivity, detection reliability, and also reduce its cost, size and power consummation through the use of harmonic components. The proposed harmonic radar design and demonstration are able to increase SNR, resolve null points, and improve the detection of heartbeat compared to the single carrier-frequency counterparts. This presentation will provide the overview of the state-of-the-art of this radar technique with its theoretical foundation and experimental validation. Recent architecture developments will be examined for low-power applications. A further extension of this harmonic technique to other wireless systems will briefly be presented with simulated and measured results.

ABSTRACT. by G. Charvet, C. Mestais, F. Sauter-Starace, M. Foerster, A. Lambert, C. Chabrol, S. Robinet, R. D’Errico, V. Josselin, N. Torres-Martinez, T. Costecalde, D. Ratel, A.L. Benabid

ABSTRACT. Integrated systems in nanometer technologies are highly susceptible to process parameter variations, power supply and temperature variations, environmental disturbances, and ageing effects.  To account for these non-idealities it is required to equip systems with efficient self-healing capabilities both at post-manufacturing and during their lifetime in the field of operation. Self-healing at post-manufacturing aims at correcting yield loss while self-healing in the field of operation aims at maintaining an expected level of performances in a power-efficient manner to account for unexpected applications, harsh environments, and ageing. In this talk, we will present a generic self-healing paradigm for RF transceivers that is based on tuning knobs judiciously inserted into the design to add several degrees of freedom, built-in non-intrusive sensors, and a statistical learning algorithm. In particular, we will focus on post-manufacturing self-healing, where the statistical learning algorithm maps the output of non-intrusive sensors that offer an “image” of process variations to an optimal tuning knob setting in one-shot, that is, without needing to enter into a time-consuming self-test/self-healing loop.
 

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ABSTRACT. In this contribution we review the challenges and possible solutions to achieve accurate s-parameters and power calibration the (sub)mm-wave bands. First a numerical and experimental analysis of multimode propagation over co-planar transmission lines, used during the calibration process, are reviewed. The losses and coupling effects arising from the unwanted propagating modes are analysed by means of 3D electro-magnetic simulations. Fused silica is then proposed as an optimal calibration substrate due to its low loss-tangent and low dielectric constant, which allows to reduce, compared to alumina, losses arising from spurious modes. A frequency salable approach to achieve absolute power control for large signal characterization in the (sub)mm-wave bands is then introduced.

ABSTRACT. The idea of an embedded instrument (EI) is to embed some form of test and measurement into silicon to characterize, debug and test chips. The concept of the EI is different from build-in self test (BIST) and other kinds of monitors by the fact that embedded instruments can provide the user with rich and detailed information with respect to the performances of the target, not just a true/false indication. In this paper, two embedded instruments for analogue and mixed-signal IPs focusing on dependability applications are introduced. They are the EI for measuring MOS transistors’ threshold voltage and the EI for testing OpAmps’ gain and offset.

ABSTRACT. This paper presents our recent work towards state-of-the-art integrated test concepts for the in-situ characterization of silicon-integrated millimeter-wave devices and transceiver components for radar and communication applications. Narrowband as well as ultra-broadband integrated network analysis solutions for a variety of frequency bands ranging from 50 to 120GHz are outlined. In this context, direct-conversion and heterodyne architectures and their respective implementations in silicon-germanium technologies are discussed.

ABSTRACT. This paper presents a detailed analysis of substrate coupling effects. Two types of coupling are considered. (i) Coupling from the device to the substrate and (ii) coupling between two neighboring devices. To assess the substrate coupling effect, specific test-structures have been designed for the mmW characterization. Various devices dimensions and distance between two neighboring devices have been fabricated for investigation. S parameters measurements are performed up to 110 GHz and the substrate-coupling is investigated. To validate the analysis, Sentaurus TCAD simulations are used. A comparison between the S-parameters measurements and TCAD results is given. Finally, a scalable compact model based on lumped elements is proposed for the circuit design in the sub-THz range.