ABSTRACT. Injection-locked oscillators (ILOs) have experienced increasing use for wireless RF communication and in clocking circuitry for wireline links. This presentation begins with some background on ILOs, highlighting their benefits compared with DLLs, PLLs and other circuitry capable of clock amplification, multiplication, phase generation, interpolation, and phase noise filtering. A challenge limiting the practical use of ILOs in these applications is that their modeling is less well understood. This tutorial will therefore summarize the analysis and practical modeling methods for ILOs. First, the classical linearized model is presented. The intuitive understanding afforded by the linearized model will be highlighted and it will be used to inform high-level design choices. Second, the impulse sensitivity function, a cyclo-stationary approach popularized for modeling phase noise in oscillators, is applied to the modeling of ILOs. Finally, a more accurate model, called the phase transfer characteristic, is described, including methods for model extraction. A live demo of ILO modeling for practical applications will be incorporated into the tutorial using Matlab/Simulink.

The tutorial will then overview the design of ILOs for several practical applications. First, multi-phase clock generation is covered and techniques to ensure uniform spacing of the generated phases are described. Second, the use of ILOs for phase interpolation is discussed. A key challenge here is the ability to provide a clock phase programmable over the entire range ±π radians. For example, some past work in this area has observed that an ILO's performance suffers when used for phase shifts exceeding ±π/2 radians. This problem may be addressed by selectively injecting either the in-phase or quadrature stage of a quadrature ILO, thereby providing an additional 90-degree phase shift. Implementations of this approach are described including both ring and LC oscillators operating at frequencies from 2 - 20 GHz in CMOS technologies from 65nm - 130nm. Finally, approaches towards the design of an ILO for clock multiplication are reviewed. Particular attention is paid to the need to ensure adequate lock range for frequency-agile applications. A useful approach in this regard is to ensure strong injection via multiple sites in the oscillator, demonstrated in a 4x multiplying ILO implemented in 40nm CMOS.

The tutorial will culminate in two detailed design case studies from the presenter’s past work that combine multiple ILOs into highly-functional clocking subsystems. First, a high-frequency jitter-tolerant receiver in 65 nm CMOS is presented. The clock receiver comprises two ILOs to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Jitter tolerance is improved by tracking correlated jitter through the ILOs. Different data rates and latency mismatch between the clock and data paths are accommodated by controlling the ILOs’ jitter tracking bandwidth up to 300 MHz. A receiver using this architecture in 65nm CMOS consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz. Second, a frequency agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling is presented. Edge detectors and multiple injection sites extend the aggregate lock range of two MILOs to 55.7% of the 3.16-GHz center frequency. Monitoring circuits identify the correct MILO and power-off the other within 10 reference clock cycles.

ABSTRACT. With the increasing demand of processing power to be delivered by the System On Chips, it is now key to improve their energy efficiency, not only for thermal or battery life duration purpose but also for environmental considerations such as green supercomputers, wireless base stations and micro servers. Using FD-SOI technology enables designing energy efficient SOCs running at very high frequency over an ultra-wide voltage range while minimizing power dissipation. In this context, STMicroelectronics has developed a full design platform leveraging on body biasing considered as the key design solution to provide best-in class SOCs to the market. The talk will describe the capability of body biasing, showing it is not only well suited for performance boosting but also for power optimization and compensation. Body biasing implementation details will be also shared thru the presentation of several silicon demonstrations.

ABSTRACT. Injection-locked oscillators (ILOs) have experienced increasing use for wireless RF communication and in clocking circuitry for wireline links. This presentation begins with some background on ILOs, highlighting their benefits compared with DLLs, PLLs and other circuitry capable of clock amplification, multiplication, phase generation, interpolation, and phase noise filtering. A challenge limiting the practical use of ILOs in these applications is that their modeling is less well understood. This tutorial will therefore summarize the analysis and practical modeling methods for ILOs. First, the classical linearized model is presented. The intuitive understanding afforded by the linearized model will be highlighted and it will be used to inform high-level design choices. Second, the impulse sensitivity function, a cyclo-stationary approach popularized for modeling phase noise in oscillators, is applied to the modeling of ILOs. Finally, a more accurate model, called the phase transfer characteristic, is described, including methods for model extraction. A live demo of ILO modeling for practical applications will be incorporated into the tutorial using Matlab/Simulink.

The tutorial will then overview the design of ILOs for several practical applications. First, multi-phase clock generation is covered and techniques to ensure uniform spacing of the generated phases are described. Second, the use of ILOs for phase interpolation is discussed. A key challenge here is the ability to provide a clock phase programmable over the entire range ±π radians. For example, some past work in this area has observed that an ILO's performance suffers when used for phase shifts exceeding ±π/2 radians. This problem may be addressed by selectively injecting either the in-phase or quadrature stage of a quadrature ILO, thereby providing an additional 90-degree phase shift. Implementations of this approach are described including both ring and LC oscillators operating at frequencies from 2 - 20 GHz in CMOS technologies from 65nm - 130nm. Finally, approaches towards the design of an ILO for clock multiplication are reviewed. Particular attention is paid to the need to ensure adequate lock range for frequency-agile applications. A useful approach in this regard is to ensure strong injection via multiple sites in the oscillator, demonstrated in a 4x multiplying ILO implemented in 40nm CMOS.

The tutorial will culminate in two detailed design case studies from the presenter’s past work that combine multiple ILOs into highly-functional clocking subsystems. First, a high-frequency jitter-tolerant receiver in 65 nm CMOS is presented. The clock receiver comprises two ILOs to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Jitter tolerance is improved by tracking correlated jitter through the ILOs. Different data rates and latency mismatch between the clock and data paths are accommodated by controlling the ILOs’ jitter tracking bandwidth up to 300 MHz. A receiver using this architecture in 65nm CMOS consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz. Second, a frequency agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling is presented. Edge detectors and multiple injection sites extend the aggregate lock range of two MILOs to 55.7% of the 3.16-GHz center frequency. Monitoring circuits identify the correct MILO and power-off the other within 10 reference clock cycles.

ABSTRACT. by Eric Kerhervé, Aurélien Larie & Baudouin Martineau, IMS Laboratory, Bordeaux, France.

Traditionally, millimeter-wave (mmW) circuits using only III-V technologies have been used in low-volume, high-performance products. With the recent progress of highly scaled Si-based technologies such as 28nm-CMOS FD SOI achieving fT and fmax beyond 300 GHz, the application area of Si-based technologies has broadened from digital, analog, RF, and microwave domains to include mmW applications. The aim of this tutorial is to give the audience the design flow to successful the mmw power amplifier design in 28nm-CMOS FD SOI technology from STMicroelectronics. Recent developments at 60GHz perform by IMS Bordeaux will illustrate this tutorial from a research activity point of view.

Summary of the 60 GHz 28nm-CMOS FD SOI Power Amplifier design flow

- Why CMOS FD SOI?

- PA structure

- Challenge (active device)

- PA operating classes

- Linearity issues in WPAN applications

- Choice of structures and transistor topologies

- 28nm CMOS FD SOI transistor performances

- Optimal transistor finger width for fmax

- Optimal biasing for fT and fmax

- Output power and number of transistor fingers

- 28nm CMOS FD SOI transistor design

- Optimum output impedance determination

- Impact of the parasitic interconnections

- Extraction of parasitic elements

- Stability issues

- Impedance matching network design

- Simulation and measurement results of the PA

ABSTRACT. Speakers: Yann Deval, François Rivet, Yoan Veyrac, Nassim Bouassida (IMS Laboratory, Bordeaux, France).

Abstract

The diversity of communication standard simplies the use of multi-band and multi-mode radios. Recent years have seen a wide Investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-­‐standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance.

It is clearlyobserved that disruptive solutions are required. The

focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide‐band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade‐off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide‐band capabilities, low power consumption and high order of modulation schemes.

Table of content

The goal of this tutorial is to present our original methodology of Full Software Radio system design. The learning objectives address a wide audience:

beginner: presentation of RF constraints for circuit design, trade off between specification and 28nm FDSOI technologies.

intermediate: analog signal processing issues, noise, power, architecture.

advanced: mathematics adequation with transceiver specification, dynamic range, power consumption, technology.

Wireless system designers have been facing the continuously increasing demand for high data rates and mobility required by new wireless applications and therefore have started research on new generation of wireless systems that are expected to be deployed beyond 2020. For instance, 5G wireless networks will support 1,000‐fold gains in capacity, connections for at least 100 billion devices, and a 10 Gbps individual user experience capable of extremely low latency and response times. Deployment of these networks will emerge between 2020 and 2030. We present 3 main techniques:

- SASP Rx is a frequency domain receiver.

The principle of the SASP aims at selecting a spectral envelope of a RF signal within a very wide frequency band. To reach this target, the SASP processes analogically the RF input signal spectrum thanks to an analog Discrete Time Fourier Transform (DFT) with discrete time voltage samples. Once the spectrum is processed, voltage samples representing the spectral signal envelope to be treated are converted into digital. The selection of few voltage samples among thousands replaces the classical mixing and filtering operations. It reduces the A/D conversion frequency from GHz frequencies to MHz ones and thus allows a multi band selection at a very low power consumption. Its application for 5G standard is a direct carrier aggregation to achieve a 1Gbps data rate. SASP is a technique developed by IMS in 2010 by Rivet.

- Walsh is a frequency domain transmitter.

The aim here is to generate any kind of waveform from its spectrum i.e. from its harmonics. For this, and similarly to the Fourier theory, Walsh transform allows decomposing any signal into a series of harmonics. But, instead of building this series on sine waves harmonics, Walsh theorem demonstrates that a family of square waves can generate any kind of signal. Thereby, using a millimeter‐Wave [mmW] Phase‐Locked Loop [PLL], the harmonic generation can be done at low power and area integration cost. It avoids the integration of several voltage controlled oscillators associated to each harmonics of the series. Indeed, square signals can be generated from a high frequency and divide by 2, N times thanks to a mmW PLL. The mathematical theory based on Walsh theorem states that using algebraic operations (phase shifting, sum, delay, ...) on a finite number of square waves allows to implement this signal generator. The originality of this project is that every square signals are directly amplified and then combined by their power to form the transmitted signal with a correct matching. The sum is performed thanks to a current node. Algebraic operations are consequently carried out by biasing differential amplifying square signals. Walsh is a technique developed by IMS in 2013.

- Riemann Pump is a time‐domain transmitter.

The purpose of the Riemann Pump is to generate arbitrary waveforms up to the gigahertz range with a low cost and low consumption solution, the main target being the generation of modulated signals, especially to address the 5G standard. The wanted signal is to be generated thanks to a pre‐determined set of slopes. At first, the Riemann code is computed from the theoretical desired signal; it corresponds to the slope index sequence giving the better approximation of the signal (within the meaning of the Riemann integral). This code controls switched current sources, in order to produce current steps that are integrated into an output capacitive load, thus generating a piecewise linear approximation of the wanted signal. Riemann is a technique developed by IMS in 2013.

ABSTRACT. Recent research effort in exploring and exploiting substrate integrated circuits (SICs) has fundamentally changed the landscape of high-frequency circuit and system integration and development. In particular, substrate integrated waveguide (SIW) technology, which is part of the SICs family, has created a great enthusiasm in the applied electromagnetic and integrated circuit community worldwide for a wide range of low cost-enabled commercial and high-performance-oriented defense applications from MHz to THz. The critical enablers in this disruptive technology lie in the successful hybrid and monolithic planarization and integration of non-planar metallo-dielectric waveguides through the structure synthesis made of various processing techniques. The early SIW technology development has been pushed forward and has become matured thanks to the development of a series of single layered and multi-layered printed circuit board (PCB) processing techniques and hybrid multilayered micro-fabrication processing techniques such as LTCC and photo-imageable processing techniques. Those fabrication techniques have contributed to the fast-paced progress of passive integrated components, circuits and antennas. This paper reviews the recent developments and accomplishments of various SIW antenna and circuit techniques with emphasis on PCB-based design platforms. Practical examples are shown for their applications in the design and development of innovative integrated passive circuits and antenna arrays for applications ranging from MHz to THz. Emerging and future development trends of SIW techniques are discussed with special interest in the use and integration of smart and active materials as well as semiconductor-based microelectronic processing techniques such as CMOS schemes over millimeter-wave and terahertz frequency ranges. It is anticipated that emerging CMOS-based “SIW and SICs” will prevail in the decades to come. This presentation will also deal with a number of grand challenging issues and the arising of unprecedented problems in passive-active circuits integrations. 

ABSTRACT. Speakers: Yann Deval, François Rivet, Yoan Veyrac, Nassim Bouassida (IMS Laboratory, Bordeaux, France).

Abstract

The diversity of communication standard simplies the use of multi-band and multi-mode radios. Recent years have seen a wide Investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-­‐standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance.

It is clearlyobserved that disruptive solutions are required. The

focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide‐band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade‐off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide‐band capabilities, low power consumption and high order of modulation schemes.

Table of content

The goal of this tutorial is to present our original methodology of Full Software Radio system design. The learning objectives address a wide audience:

beginner: presentation of RF constraints for circuit design, trade off between specification and 28nm FDSOI technologies.

intermediate: analog signal processing issues, noise, power, architecture.

advanced: mathematics adequation with transceiver specification, dynamic range, power consumption, technology.

Wireless system designers have been facing the continuously increasing demand for high data rates and mobility required by new wireless applications and therefore have started research on new generation of wireless systems that are expected to be deployed beyond 2020. For instance, 5G wireless networks will support 1,000‐fold gains in capacity, connections for at least 100 billion devices, and a 10 Gbps individual user experience capable of extremely low latency and response times. Deployment of these networks will emerge between 2020 and 2030. We present 3 main techniques:

- SASP Rx is a frequency domain receiver.

The principle of the SASP aims at selecting a spectral envelope of a RF signal within a very wide frequency band. To reach this target, the SASP processes analogically the RF input signal spectrum thanks to an analog Discrete Time Fourier Transform (DFT) with discrete time voltage samples. Once the spectrum is processed, voltage samples representing the spectral signal envelope to be treated are converted into digital. The selection of few voltage samples among thousands replaces the classical mixing and filtering operations. It reduces the A/D conversion frequency from GHz frequencies to MHz ones and thus allows a multi band selection at a very low power consumption. Its application for 5G standard is a direct carrier aggregation to achieve a 1Gbps data rate. SASP is a technique developed by IMS in 2010 by Rivet.

- Walsh is a frequency domain transmitter.

The aim here is to generate any kind of waveform from its spectrum i.e. from its harmonics. For this, and similarly to the Fourier theory, Walsh transform allows decomposing any signal into a series of harmonics. But, instead of building this series on sine waves harmonics, Walsh theorem demonstrates that a family of square waves can generate any kind of signal. Thereby, using a millimeter‐Wave [mmW] Phase‐Locked Loop [PLL], the harmonic generation can be done at low power and area integration cost. It avoids the integration of several voltage controlled oscillators associated to each harmonics of the series. Indeed, square signals can be generated from a high frequency and divide by 2, N times thanks to a mmW PLL. The mathematical theory based on Walsh theorem states that using algebraic operations (phase shifting, sum, delay, ...) on a finite number of square waves allows to implement this signal generator. The originality of this project is that every square signals are directly amplified and then combined by their power to form the transmitted signal with a correct matching. The sum is performed thanks to a current node. Algebraic operations are consequently carried out by biasing differential amplifying square signals. Walsh is a technique developed by IMS in 2013.

- Riemann Pump is a time‐domain transmitter.

The purpose of the Riemann Pump is to generate arbitrary waveforms up to the gigahertz range with a low cost and low consumption solution, the main target being the generation of modulated signals, especially to address the 5G standard. The wanted signal is to be generated thanks to a pre‐determined set of slopes. At first, the Riemann code is computed from the theoretical desired signal; it corresponds to the slope index sequence giving the better approximation of the signal (within the meaning of the Riemann integral). This code controls switched current sources, in order to produce current steps that are integrated into an output capacitive load, thus generating a piecewise linear approximation of the wanted signal. Riemann is a technique developed by IMS in 2013.

ABSTRACT. Recent research effort in exploring and exploiting substrate integrated circuits (SICs) has fundamentally changed the landscape of high-frequency circuit and system integration and development. In particular, substrate integrated waveguide (SIW) technology, which is part of the SICs family, has created a great enthusiasm in the applied electromagnetic and integrated circuit community worldwide for a wide range of low cost-enabled commercial and high-performance-oriented defense applications from MHz to THz. The critical enablers in this disruptive technology lie in the successful hybrid and monolithic planarization and integration of non-planar metallo-dielectric waveguides through the structure synthesis made of various processing techniques. The early SIW technology development has been pushed forward and has become matured thanks to the development of a series of single layered and multi-layered printed circuit board (PCB) processing techniques and hybrid multilayered micro-fabrication processing techniques such as LTCC and photo-imageable processing techniques. Those fabrication techniques have contributed to the fast-paced progress of passive integrated components, circuits and antennas. This paper reviews the recent developments and accomplishments of various SIW antenna and circuit techniques with emphasis on PCB-based design platforms. Practical examples are shown for their applications in the design and development of innovative integrated passive circuits and antenna arrays for applications ranging from MHz to THz. Emerging and future development trends of SIW techniques are discussed with special interest in the use and integration of smart and active materials as well as semiconductor-based microelectronic processing techniques such as CMOS schemes over millimeter-wave and terahertz frequency ranges. It is anticipated that emerging CMOS-based “SIW and SICs” will prevail in the decades to come. This presentation will also deal with a number of grand challenging issues and the arising of unprecedented problems in passive-active circuits integrations.