ABSTRACT. A compact 67 GHz LC oscillator implemented in 65nm bulk CMOS technology by STMicroelectronics is presented. It exploits a three-spiral transformer to achieve low phase noise and low power consumption. The measurements show that the oscillator core is capable to operate with a supply voltage as low as 0.6 V, while consuming 3.6 mW. The measured phase noise amounts to -88.7 dBc/Hz at a 1 MHz frequency offset from the carrier when operating with 0.6 V voltage supply, and -96 dBc/Hz at a 1 MHz frequency offset from the carrier when operating with 1.2 V.

ABSTRACT. This paper presents the design of a mm-wave VCO for Backhaul applications. This VCO operates between 81-86 GHz and was designed in the BiCMOS 55 nm technology. The innovation is linked to the use of a slow-wave coplanar strip (S-CPS) as a differential inductor. Thanks to high quality factor (≈ 33) of S-CPS, the phase noise and power consumption are improved. The proposed VCO is compared to the classical VCO (lumped inductor and varactor based). The S-CPS based VCO exhibits 3 dB less phase noise, and lower power consumption, with a phase noise of -111 dBc/Hz at 10 MHz offset and a power consumption of 6.84 mW. With 1.2 V supply, the tuning range reaches 7.9%, which is enough for the targeted application.

ABSTRACT. This paper presents a novel design and an optimization methodology of an ultra-low power and low phase noise RF voltage controlled oscillator (VCO). This VCO is based on a PMOS-NMOS cross-coupled topology operating in the subthreshold region. An adaptive body biasing technique is presented in this circuit leading to a high immunity to PVT (P=Process, V=Voltage, and T=Temperature) variations. The VCO, implemented in 130nm CMOS technology, consumes only 65 μW under 0.6 V. The obtained tuning range is about 7.6 % from 2.27 GHz to 2.45 GHz; therefore, it can address many wireless communication standards such as Wi-Fi, ANT, ZigBee, IEEE 802.15.4, 6LoWPAN, and Bluetooth.

ABSTRACT. In this paper a novel tunable transmission line operating in V-band (57GHz to 66GHz) is presented. Designed in a 130nm BiCMOS technology, the proposed structure explores ground plane switching to perform impedance tuning. It exhibits a 16 Ohms shift over characteristic impedance – equivalent to 30% of tuning range - with a Q-factor higher than 16 thanks to a shielding used in slow-waves transmission lines. Using this topology versus a classical 50 Ohms coplanar waveguide into a reconfigurable pi-type matching network with tunable stubs, it allows to cover around 100% more of impedances in the Smith Chart with a “2 dimensional” tuning.

ABSTRACT. A high PSRR, low power 1.2V curvature corrected Bandgap reference (BGR) for Wearable EEG application is described in this paper. The proposed BGR provides a supply regulation of 0.113%/V with VDD range of 1.01-2.62V. Piecewise curvature compensation is employed to reduce the temperature coefficient (TC) to 2.295ppm/°C, in temperature range –10-110°C. The BGR circuit was designed in standard 0.18um CMOS technology where a proportional to absolute temperature (PTAT) and a complementary to absolute temperature (CTAT) current generation circuit were used. A non-linear current was generated using PTAT current and CTAT voltage generation circuit and a PSRR of 84.62dB was achieved.The total current consumption of the whole BGR including biasing and startup circuit is only 4.691uA

ABSTRACT. We present a CMOS differential neural amplifier with high input impedance. The miniaturization of the MEAs goes with an increase of the electrodes impedance and necessitates high input impedance neural amplifiers; otherwise it results in a significant loss of signal and low SNR. The circuit presented here is designed on a 0.35 um CMOS technology. Two versions are described which capacitive input impedance is 1 pF. One is robust to high input offset and consumes 13.5 uA; the other one is more sensitive to offset but consumes only 3.7 uA. Both generate less than 7 µVRMS input-referred noise and their NEF figures are respectively 6 and 2.59. These features are competitive in view of the literature on neural amplifiers, while the circuit was designed to present a high input impedance.

ABSTRACT. In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35µm high-voltage process. The transmitting circuit is taped out and measurements are performed on the integrated circuit in order to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100V, a frequency up to 5MHz and a driving strength of 2V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18mm2 and the power consumption at the scanner operation conditions is 0.754mW without the transducer load and 0.936mW with it.

ABSTRACT. This paper presents the design and realization of a programmable 4th-order bandpass filter for biomedical applications in a standard 0.18 µm CMOS technology. The center frequency is adjustable from 80 Hz to 7 KHz, using a 6-bit digital-to-analog-converter (DAC). At a center frequency of 1 KHz and quality factor of 4, the simulated dynamic range is 53.6 dB for 1% total harmonic distortion (THD) and the simulated total input-referred noise, integrated from 875 Hz to 1.125 KHz, is 177µV. The filter consumes only 6 nW from a 1-V single power supply voltage.

ABSTRACT. Powering active implantable devices is challenging. Implants must be small and have a long lifetime. Wireless power offers energy over the life of the device. Using integrated circuits for managing wireless power transfer allows for a small implant. Often when implemented in CMOS, a synchronous rectifier is used to achieve AC-DC conversion. Current spikes can occur in the rectifier and must be considered to avoid electromigration. This paper presents the analysis of the peak currents in the synchronous rectifier. Reducing the peak current can be achieved by decreasing the size of the rectifying transistors. We have developed and fabricated a synchronous rectifier in XFABs XH018 180nm high voltage CMOS process which we will use to confirm our analysis.

ABSTRACT. This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate large RC time constants associated with resistor ladder thus facilitating calibration to happen at full speed. 12-bit ADCs with first stage resolution of 1.5b, 2.5b, 3.5b, and 2b, followed by an ideal back-end ADC were simulated both in MATLAB and Cadence. Circuit simulations in Global Foundry’s (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method gives significant performance improvement.

ABSTRACT. A power-efficient 14-bit 250MS/s pipelined ADC is present. With the aid of range-scaling technique, an original single-stage opamp is adopted to replace the conventional large-swing opamp. A novel charge compensation based (CCB) technique effectively reduces input-dependent errors of the reference voltage and it consumes no static current. This ADC is designed in a 55nm CMOS process with a 1.2-V supply voltage. CCB reference improves SNDR/SFDR by more than 4 dB/10 dB and stabilizes the performance. The simulation result with noise shows that the ADC has the SNDR/SFDR of 71.2 dB/86 dBc at 119 MHz input frequency. The ADC consumes 36.2 mW, which includes 23 mW for the ADC core and 12 mW for the low jitter clock receiver. It achieves the figure of merit (FOM) of 48.6 fJ/step.

ABSTRACT. This work presents a blind background calibration algorithm for correcting inter-stage gain error and capacitor mismatches in multi-bit stage pipelined ADC. Based on the analysis of the density of specific output codes, the algorithm stores the information of the codes and needs only 80 registers. And there is no need to modify the analog circuits, which simplifies the design. Besides, since there is no multiplication or division in the digital logic, the algorithm can be implemented with a low hardware overhead, which lowers the power dissipation. For verification, a 14-bit 150MS/s ADC is fabricated in 130nm CMOS process. At 15.5MHz input signal, SDNR/SFDR improved from 66.8dB/78.57dBc to 69.7dB/87.3dBc and INL dropped from 8LSB to 3LSB after calibration.

ABSTRACT. The manuscript describes the design and implementation of a low-power switched-capacitor Sigma Delta modulator in STM 90-nm CMOS technology, for sensors interface applications. With the aid of an accurate behavioral model, the power consumption is minimized without sacrificing the effective resolution. Through the optimization of single-stage integrators, with feed-forward summation, and using a class-A OTA op-amp whit local positive feedback, a total power consumption of 50-μW from a 1.2-V power supply is achieved. The modulator reaches a peak SNR of 96-dB and a noise floor of 8.6-μV-rms over a 250-Hz signal bandwidth. The presented design is one of the first modulator implemented in a 90-nm CMOS and achieving a 16-bit effective resolution with a 1.5-pJ/conv. figure-of-merit.

ABSTRACT. This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead of using an array of time amplifiers (TAs) to amplify the time residue, the proposed TDC reduces the power and area consumptions by using only one TA. The designed TDC achieves a resolution of 1.2 ps with a conversion range of 0.614 ns while consuming 0.602 mW at 10 MHz and 8.299 mW at 150 MHz. The achieved figure-of-merit (FoM) of the TDC is 0.108 pJ/conversion at a frequency of 150 MHz.

ABSTRACT. Due to the increase of wireless standards using different RF frequencies there is a need to have transceivers that can handle a wide range of RF frequencies. By abandoning the classical narrowband approach, new receiver architectures are explored in which noise and interferer robustness problems have to be solved. At the same time new features are wanted such as spectrum sensing for cognitive radio and self-interference cancelling for future full duplex communication. In this presentation several circuit and system techniques will be illustrated that may enable future radio systems.

ABSTRACT. This work proposes an inductorless wideband low noise amplifier (LNA) for multistandard applications. This LNA is based on a self-biased complementary current-reuse common source amplifier on the forward path and a source follower on the feedback, using a gyrator-C like effect to create real valued impedance and an inductive effect, achieving wideband input matching. Designed in IBM 130 nm CMOS process, it presents NF of 2.7 dB, voltage gain of 22.8 dB, IIP 3 of -6 dBm. The power consumption is 2.8 mW for a supply voltage of 1.2 V.

ABSTRACT. In this paper, a power amplifier implemented with a common-drain structure is introduced. With proper input matching, this structure is shown to provide a reasonable power gain and superior linearity and efficiency in comparison to other low-power topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the low-voltage variations across the gate-source capacitance. This power amplifier is suitable for low-power and short-range applications such as Bluetooth Low Energy (BLE). Based on the calculated S-parameters, the operation frequency of this amplifier and its design trade-offs are presented, along with a comparison with competitive topologies.

ABSTRACT. An ultra-wideband Voltage Controlled Oscillator (VCO) is presented in this paper. The circuit achieves fast startups and stops which allow wideband pulses to be generated. In addition, the VCO allows bipolar modulations as Binary Phase Shift Keying to be implemented without the need of a shaping circuit as a mixer. The oscillator output provides large differential oscillations from 2.6GHz to 12.3GHz. Measurements have demonstrated the frequency agility of the proposed VCO which covers the mandatory channels of the low (resp. high) bands centered on 4492.8MHz (resp. 7987.2MHz) defined by the IEEE 802.15.4 standard. The VCO power consumption is about 3.2mW/GHz. By using Current Mode Logic (CML) gates, the power consumption can be reduced to 3.84uW only when the VCO is not running.

ABSTRACT. This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator’s configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different number of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.

ABSTRACT. A 60GHz class-A bipolar power amplifier (PA) is fabricated in a BiCMOS55nm technology. In order to enhance the power added efficiency (PAE) behavior of the PA, a bias control loop, is implemented in order to dynamically adjust the DC bias current according to its output power level. A power detector (PD) is connected directly at the output of the power amplifier in order to track the envelope variation of the RF signal. Under constant bias conditions, the PA has a power gain (Gp) of around 7dB, a maximum PAE of 16%, and an OCP1dB of around 7.5dBm while driving 25.8mA. Under adaptive bias control, the mean value of the DC current is reduced down to 20.8mA, while maintaining high Gp, leading to a significant enhancement of the PAE of the PA.

ABSTRACT. Multi-disciplinary technologies are currently involved in orthognathic and dental surgery. By using 3D and CT scans, the surgery can be planned beforehand by making use of 3D image processing, visualization and planning tools. With 3D printing, accurate splints and wafers can be generated for the surgery. Nowadays, these tools are on-premises software and this makes it very hard for collaboration between several specialists. Therefore, we researched the possibility to create an online cloud-based platform to run the currently used surgical planning tools. We achieved multiple two-factor authentication user logins, simultaneous surgical planning sessions and lightweight multi-platform support.

ABSTRACT. In this paper, an auto tuning system that uses a variable synchronous switched capacitor for controlling the resonant frequency of the tank circuit of a half bridge voltage mode resonant converter for High intensity focused ultrasound (HIFU) applications is presented. The presented auto tuning system using a switched capacitor instead of a large inductor in the classical tuning topology. Hence, there will be no need of bulky magnetic components. which makes it naturally comply with the Magnetic Resonance Imaging (MRI) compatibility regulations. The designed circuit works under 1MHz, which is simulated in a CMOS 0.35µm technology. The required performances have been confirmed by simulation results.

ABSTRACT. In this paper, a new sigma delta modulator based on a multiplexed input topology is proposed to decrease power consumption and size in implantable bio-interfacing systems. An opamp sharing technique is employed in order to process several input sequentially. The proposed sigma delta modulator integrates each input separately and stores the integrated value inside a dedicated capacitor. We show that the resulting transfer function of the modulator is equivalent for all channels. The proposed circuit has been implemented in a 180-nm TSMC process. The circuit consumes 11.5 μW per channel, provides an ENOB of 7.8 bits, and presents a bandwidth of 10 kHz. The chip area for the proposed design is 150 μm x 135 μm for 4 multiplexed inputs.

ABSTRACT. This paper presents an ultra-low power analog front end (AFE) with ΣΔ modulator ADC meant for acquisition of biopotential signals. The system consists of a signal conditioning stage with programmable gain and bandwidth, a mixed signal automatic gain control (AGC), and a ΣΔ ADC. The full system is designed in UMC 0.18µm. The AFE achieves an overall linearity of more 10 bits with 0.47µW power consumption. The ADC provides second order noise shaping while using single integrator and an ENOB of ~12 bits with 1.4µW power consumption. The system was successfully tested for a ECG signal from PTB database.

ABSTRACT. This paper presents an Ultra-WideBand (UWB)RADAR system for distance and breathing measurement based on a Step Recovey Diode emitter delivering 230 ps pulse signal width. The reflected signal by the target is sampled on an oscilloscope and the system shows a 1.3 cm human chest displacement when the target is 20 cm distant from the RADAR. Then, the oscilloscope is replaced by a low cost and low complexity CMOS circuit, developed in our laboratory and named Time Delayed Sampling and Correlation (TDSC). Experimental results show a resolution of 5 cm and a maximum range of 25 cm for a metallic target.

ABSTRACT. Dynamic Voltage-Frequency Scaling is a very efficient way to manage performance/power trade-off in embedded systems. It consists in switching between low and high voltage-frequency according to the required processing performance. However, with novel technologies such as FD-SOI, circuits can be designed to work on very wide frequency ranges. Substantial power savings can be achieved through efficient power mode placement. We propose a method to determine the optimal position of intermediate operating points that maximizes the power reduction on the operating frequency range by exploiting Body Bias with DVFS. Results from circuit measurements illustrate the efficiency of the proposed method with average power reduction up to 35% on a 1800MHz wide frequency range, with peaks up to 50.3%.

ABSTRACT. Self-adaptive systems aim to satisfy system constraints in an environment with sudden parameter changes. Moreover, they enable new possibilities to cope with dynamic run-time requests. Their self-adapting capabilities lead to a highly dynamic system behavior which leads to development and run-time overheads. Additional real-time constraints increase the design space complexity further. The challenge is to reduce the complexity of application and system design. Recently self-adaptive systems have been discovered for applications in emerging domains, such as the Internet of Things and Cyber- Physical Systems. This paper surveys approaches to handle task scheduling/mapping, as well as resource management in these systems.

ABSTRACT. Modern autofocus systems are known for their fast response speed and optimized routines of the image processing. Nevertheless, the bottleneck of the autofocus system development is the transformation of the technical specification into the design rules that strictly take in account the specifications and introduce a guarantee of the best performance. In this paper we propose a new approach in autofocus systems design that uses some linear control theory results that allow to obtain the optimal feedback gain in the sense of quadratic sharpness hypothesis. The method proposed in this work allows to improve the existent autofocus systems that are based on the sharpness autofocus using the optimal feedback gain.

ABSTRACT. This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in large digital systems on chip. The originality of the work is in the use of a solution based on digital circuits. This offers many opportunities for implementation of different algorithms of synchronization, depending on the application context and operational conditions. The synchronization algorithm is based on a PI control applied to the phase error measured between neighbors. Such architecture is compatible with the concept of networks on chip. The paper presents two prototypes demonstrating the feasibility and reliability of the proposed solution for synchronization.

ABSTRACT. Wireless sensor nodes are now cheap and reliable enough to be deployed in different environments. However, their limited energy capacity limits their lifespan. In this paper, a Management strategy at network-level of a set of nodes is implemented, taking into account an estimation of the remaining energy in each sensor node. The control formulation is based on Model Predictive Control with constraints and binary optimization variables, leading to a Mixed Integer Quadratic Programming problem. The estimation of the remaining energy in batteries must be simple enough to be implemented in low-cost, low-power, low-computational-capability sensor nodes.

ABSTRACT. In this work, the impact of short-channel effects on velocity overshoot is discussed. Hydrodynamic simulations are first performed to investigate the overshoot behavior under a uniform electrical field. Then a spatially varying electric field, which corresponds to the electric field profile in inversion of a MOSFET, is introduced to observe the impact of short-channel effects. Finally, this overshoot is included in SPICE simulations to observe how it affects a ring-oscillator.

ABSTRACT. Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper, we deliver a comparative review between different RRA architectures found in literature. We also propose a new efficient RRA architecture. The implementation results of the previous RRA architectures and our proposed one on FPGA are given, that shows the improvements of the proposed RRA.

ABSTRACT. The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a configurable delay element. Reported simulation results, in accordance with static timing analysis, show that the self-timed timing constraints are satisfied using our design methodology.

ABSTRACT. This paper proposes to analyze a WSN microcontroller sub-system power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node’s sub-modules. Power simulations of a microcontroller based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. This study exhibits power gains from 14.5% to 76% (very low to medium activity rates) attesting the future design of this new module.

ABSTRACT. This paper investigates the subthreshold operation of the inverter-based operational transconductance amplifier for the potential use in very low power data conversion systems. Circuit analysis and sizing strategies are presented, and a first order continuous-time delta-sigma modulator circuit is used as a case study to verify the performance of the amplifier when operating in subthreshold region. We demonstrate experimental results using a digitally configurable Nauta operational transconductance amplifier implemented in a 180nm CMOS process which shows up to 97.76 percent power reduction when 600mV is used instead of 1.8V as supply with better figure of merit and without significant signal-to-noise distortion ratio penalty highlighting its significant potential at subthreshold operation.

ABSTRACT. In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18µm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197µVRMS.

ABSTRACT. A new CMOS digitally controlled negative-transconductance amplifier (DTA) and an application example of a 4-Bits-Digitally Controlled Oscillator (DCO) are presented in this paper. The DTA is based on the traditional Digital CMOS inverter topology. From simulation and under 1.2 volts supply voltage, the proposed DCO oscillates from 375MHz to 475MHz which is compatible with the Medical Implant Communication Service (MICS) frequency band. The maximum total power consumption is about 2.5mW and only 2.5nW in power-off mode. All simulations have been performed using a CMOS 130nm process design kit from STMicroelectronics.

ABSTRACT. An amplitude demodulation system is described here. An envelope detector is connected to the non inverting input of a differential amplifier whereas a reference voltage is applied to its inverting input. This reference is established during a self calibration process and compensates the input offset of the differential amplifier. This mechanism has been designed and implemented within the circuit described in this paper. The circuit is designed in a 160 nm Complementary Metal Oxide Semiconductor process. A sensitivity of -30 dBm is achieved. It can operate over a large frequency range from 100 MHz to 3 GHz and from -55 °C to 125 °C ambient temperature. It consumes only a few microwatts.

ABSTRACT. A high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution exploits a three-gain-stage topology and, as a distinctive behavior, provides an inherent class-AB performance with simple and robust standby current control. A 0.7 V supply OTA is designed using a 180-nm standard CMOS technology. Post layout simulations show a 61-dB open loop gain and a unity gain bandwidth of 3.6 MHz, under a capacitive load of 20 pF. Significant performance improvement when compared to prior art is achieved, so that the best figure of merit is found.

ABSTRACT. This paper presents the results of the feasibility study of a millimeter-wave system-on-chip Dicke radiometer for space-based detection of solar flares, operating at a frequency of 36.8 GHz and expected to be implemented in a 0.25 µm SiGe BiCMOS space-qualified process by IHP. System analysis and circuit simulations are presented and discussed. The results show a resolution of 0.7 K for an integration time of 0.04 s. These results support the objective targeting the first implementation of a SoC radiometer for space-based detection of solar flares in a space qualified technology.

ABSTRACT. An Application Specific Integrated Circuit (ASIC) has been designed in order to demonstrate the limitations and the challenges in ultra-low current sensing. The Utopia (Ultralow Picoammeter) ASIC is foreseen to be the front-end in the new radiation measurement system for personnel safety at CERN. It is based on the topology of a Current to Frequency Converter (CFC) and has a wide dynamic range of 7 decades without range changing. Four different channels have been implemented in order to evaluate the limits regarding sub-picoampere current measurements. Test currents starting from -50 fA have been measured.

ABSTRACT. Rogowski coils (RC) used for high-accuracy contactless current measurement ask for precise sensor geometry and specific conditions, such as a centered primary conductor. To relax these constraints, we propose here a recently patented continuous calibration system which features a reference conductor added coaxially to the primary conductor and a proportional-integral controller integrated in CMOS technology. Experimental results obtained with commercial flexible and rigid RC show that the sensor immunity to the conductor position, as well as the dispersion between RC, is reduced to +/-0.1%, i.e. a 0.1 class measurement. In addition, the system may ensure an absolute calibration of the RC current transducer, avoiding any costly calibration procedure at the end of the sensor manufacturing.

ABSTRACT. an M/D/1/N queuing model is used to determine the impact of integrating an embedded FIFO in a TCSPC system on the counting loss probability for a giving expected arrival rate to an output rate frequency. The results were applied to design a multichannel TCSPC system, while the multichannel system allow for an efficiency of 54% adding the FIFO increased the efficiency value up to 90%.

ABSTRACT. An all-digital MEMS tuning-fork self-excited vibration control method, using TAD (Time-A/D converter)-based all-digital PLL (ADPLL) by applying a unique control algorithm based on entirely time-domain processing is presented. It involves three-step processing: 1) driving a tuning-fork by ADPLL for searching MEMS self-resonant frequency, 2) comparing the phase difference between drive-pulse signal and monitor-pulse signal, 3) keeping 90º-relationship with any drift factors. TAD-type TDC digitizes the resonant frequency and phase difference alternately without the need for any analog circuit method. By using conventional piezoelectric MEMS tuning-fork, we experimentally confirmed its self-excited vibration, resulting in its resonance jitter level of σ = 52.6ns at 37µs-self-resonance period.