ABSTRACT. In this paper, the gate-level techniques for mitiga-tion of Single Event Transients (SETs) in combinational circuits have been analyzed. The main objective was to compare the SET mitigation techniques in terms of their quantitative impact on SET generation and propagation effects for individual standard cells. The comparison was done with SPICE simulations, using the 130 nm standard cell library. The following SET mitigation techniques have been analyzed: gate upsizing, gate duplication, load upsizing, insertion of transmission gates, insertion of charge sharing logic, insertion of decoupling cells, and insertion of Schmitt trigger. We have shown that the impact of techniques based on insertion of redundant logic depends on the type of target gate. In addition, we have demonstrated that the most effective SET suppression can be achieved by combining multiple techniques. The characterization results could be used as a guide for deciding on the optional SET mitigation approach for a given design.

ABSTRACT. As CMOS technology dimensions continue to reduce, radiation-induced reliability challenges are becoming increasingly prominent. Effective strategies to mitigate radiation-induced soft errors are critical for maintaining the reliability and performance of advanced technology nodes, showing that the choice of a logic style is essential, which may directly influences circuit robustness. This work aims to analyze the robustness of different 2:1 multiplexer designs to transient faults using static logic styles. Electrical simulations were performed with 32nm High-Performance technology, and Linear Energy Transfer values were assessed through P-hit and N-hit fault effects. Results show that CMOS and DCVSL logic styles exhibit strong performance in terms of robustness to radiation.

ABSTRACT. Systems-on-chip (SoCs) used in space and critical environments feature increasing cores. Because of the environment in which these systems operate, they must use fault tolerance techniques to improve reliability. XINA (eXtensible Interconnect Network Architecture) is a reliable network-on-chip for space systems, which has already been verified and tested. However, a network interface (NI) must provide communication services for its effective use in real systems. Therefore, this work presents the development of a fault-tolerant NI compatible with the XINA that implements communication services commonly adopted in SoCs. The NI implements the AMBA-AXI 5 communication protocol to facilitate and accelerate the core integration process with XINA. We present a standard and a fault-tolerant version of the NI using TMR (Triple Modular Redundancy) and Hamming ECC (Error Correction Code) techniques in its internal components. The fault-tolerant interfaces reduced the error propagation by up to 16.7x compared to the standard versions, at a price of 82% more LUTs (Look-Up-Tables) and 23% more FFs (Flip-Flops) on average.

ABSTRACT. Electronic devices exposed to non-ionizing radiation are susceptible to Single-Event Upsets (SEUs) in digital systems. These SEUs can lead to failures in the digital system of Brushless DC (BLDC) motor drivers, resulting in data reading errors, speed control malfunctions, phase commutation inaccuracies, and erroneous rotor position detection, which can have significant consequences in critical situations. Thus, this paper proposes to enhance the reliability of a Proportional-Integral (PI) speed control system for BLDC motors by employing the Triple Modular Redundancy (TMR) technique implemented within an FPG Artix-7. The results of the control efficiency are evaluated through its performance characteristics given through simulation and implementation. The fault tolerance validation of this proposal was carried out through fault injection campaigns. The results demonstrate that the TMR-based system can tolerate around 115% more faults than a non-TMR system, highlighting the robustness and reliability of the proposed solution.

ABSTRACT. This study investigates the cumulative impacts of ionizing radiation and performance variations under different temperatures of P-MOS power devices featuring two distinct layouts: Enclosed Layout Transistor (ELT) and Rectangular Layout. The Device Under Test (DUT) was exposed to 10 keV X-rays, accumulating a dose of 300 krad, while operating in polarized and off modes. Subsequently, the devices underwent thermal treatment and were characterized at temperatures ranging from 223 K to 343 K. The results suggest that both layouts exhibit similar resilience to the effects of Total Ionizing Dose (TID) and thermal variations.

ABSTRACT. Data security is an essential prerequisite for the effective functioning of modern systems. It guarantees the secure transmission of information to thwart unauthorized access and potential data breaches. Cryptography plays an indispensable role in safeguarding sensitive data during communication. The Advanced Encryption Standard (AES) is an esteemed choice among symmetric key algorithms, owing to its proven reliability and robust security features. Despite its extensive adoption, optimizing AES implementations to achieve high throughput while minimizing hardware resource consumption, particularly in area, is a significant challenge. This study addresses the challenge of reducing area usage while enhancing the throughput of the algorithm by focusing on improving the throughput-to-area efficiency of AES through a novel hardware implementation. This approach introduces an optimized SubBytes stage featuring a smaller S-box comprising just 16 elements. The proposed optimization enables an enhanced throughput per area (Mbps/k-gate), providing a more balanced solution for lightweight encryption applications. It allowed a notable area reduction of 84%, alongside doubling the maximum frequency compared to the original implementation. In terms of throughput-to-area efficiency, the optimizations resulted in a value 12.5 times greater than the original design's. Furthermore, the security robustness of the modified algorithm is confirmed through three distinct security tests, validating its reliability and suitability for practical deployment.

ABSTRACT. CHIMERA and PEGASUS introduced new categories of Fully Homomorphic Encryption schemes, offering methods for converting between schemes and improving repacking algorithms for agile encryption frameworks. Using PEGASUS as a starting point, we aimed to speed up their novel repacking algorithm through the use of additional GPU computation. This work achieved a 50x speedup and 25% reduction in the overall repacking algorithm compared to CPU computation, focusing on unexplored parts and Homomorphic functions that are already GPU-amenable. In addition, We integrated our acceleration function into the Open-Source PEGASUS framework, enhancing its compatibility with complementary works on Homomorphic Encryption acceleration.

ABSTRACT. Manycore platforms are designed to provide high performance through parallelism, addressing the current demand for embedded devices with power consumption and communication constraints. A manycore system contains processing elements (PEs) interconnected by complex communication infrastructures, such as Networks-on-Chip (NoCs). As the adoption and complexity of manycores increase, data protection emerges as a critical design requirement. Furthermore, the widespread use of third-party intellectual property cores (3PIPs) to meet time-to-market constraints and reduce design costs increases the risk of malicious hardware insertion through Hardware Trojans (HTs), thereby making manycores more vulnerable. The literature presents security techniques, such as cryptography, authentication codes, error correction codes, and the creation of secure zones. However, these countermeasures are only effective if the system can identify the location of the attack source. The goal of this work is to present a non-invasive method for localizing HTs in an NoC. The proposed method employs a probing protocol with test packets to detect the presence of HTs. The results demonstrate the effectiveness of this method in accurately identifying HTs within the NoC.

ABSTRACT. This paper presents the design and performance evaluation of a non-volatile VCMA-MTJ-based Ternary Content Addressable Memory (TCAM), focusing on energy efficiency, search speed, and reliability. Although traditional DMTJ-based NV-TCAMs offer reliability, they often encounter data overwriting during search operations. To overcome this issue, we introduce a novel VCMA-MTJ architecture that employs voltagecontrolled state transitions, effectively eliminating the risk of memory overwrite and ensuring stable and robust operation. Monte Carlo simulations demonstrate that the proposed design achieves a Search Error Rate (SER) of 0.7% for a 144-bit word, with a read energy consumption of 49.94fJ/bitcell and a search time of 0.777ns. These results highlight the potential of VCMAMTJ- based TCAM for high-density, energy-efficient memory applications that offer significant improvements in reliability and performance over existing technologies. Future efforts will focus on further reducing energy consumption while maintaining the demonstrated high reliability.

ABSTRACT. Reversible computing is a promising field that explores the possibility of performing computations in such a way that the initial state of the computation can be uniquely reconstructed from its final state. In this work, we propose an algorithm to reduce the gate count of a set of functions. We use a mix of three different approaches that translates into 15 strategies. The proposed algorithm has shown great results, even when used with other metrics.

ABSTRACT. AV1 is a codec developed by huge technology companies to be used in current and future commercial video applications. It introduces and improves several tools from its predecessor VP9, designed for a wide range of video scenarios. One of the improved tools is the Fractional Motion Estimation (FME), which generates sub-pixel predictors. AV1 employs four sets of interpolation filters, requiring significant computational effort during the Interpolation Filter Search (IFS) to identify the best filter to be used. This work proposes the FIFS, a machine-learning method developed to reduce the processing time of IFS while maintaining minimal impact on coding efficiency. This method achieved over 52% reductions in IFS time, with only a slight increase in BD-BR of 0.14%. To the best of the authors' knowledge, this is the first work in the literature to propose a machine learning-based approach for the AV1 IFS.

ABSTRACT. The growing demand for high-definition online videos emphasizes the need for efficient video codecs like H.266/VVC, which offer significant compression potential. However, its implementation presents challenges, particularly in terms of computational cost, as is the case of the Multiple Transform Selection (MTS) tool. This study analyzes the performance of MTS modes, showing that explicit MTS improves coding efficiency but increases encoding time, while implicit MTS offers modest efficiency gains with less computational cost. A machine learning-based approach is proposed, using decision trees, to accelerate encoder decisions for both intra and inter predicted blocks in explicit MTS, reducing encoding time by an average of 7.98%, with only a 0.89% increase in BD-rate. These results highlight the potential for optimization of explicit MTS in both intra and inter transformations.

ABSTRACT. As the demand for video transmission surges on remote work, education, and streaming services, the need for continuous advancements in video encoding technologies becomes increasingly evident. Adapting to the evolving requirements of efficient video delivery and consumption necessitates ongoing development and enhancement in video encoding standards, with Versatile Video Coding (VVC) emerging as a notable example. This paper provides an overview of key algorithms within Inter-Frame prediction of VVC, mainly focusing on the Test Zone Search (TZS) and the Affine Motion Estimation (AME), two of the most computationally intensive tools inside the VVC. Furthermore, this paper introduces a fast TZS and AME approach using Machine Learning, specifically employing Decision Trees. The proposed approach achieved an average reduction of over 20% in total VVC encoding time while maintaining less than a 1% impact on BD-BR coding efficiency.

ABSTRACT. This paper presents a novel approach for approximated 360° still image compression that combines latitude-adaptive quantization with low-complexity transform and quantization. While addressing the redundancies inherent in the equirectangular projection format, the proposed method is multiplication-free, requiring only addition and bit-shift operations. We experiment with different low-complexity transforms, showcasing the plug-and-play nature of our approach. We test our methods in a popular benchmark - including 4K, 6K, and 8K images - and compare them against their exact counterparts. We show that our approximated compression methods lead to no higher than 4-7 dB quality loss at small bitrates, providing efficient alternatives for resource-constrained devices.

ABSTRACT. Immersive multimedia technologies have gained popularity in recent years, and among them, omnidirectional or 360º videos are popular for entertainment and education purposes. But this video content requires a lot of information to be represented, imposing the use of highly efficient video encoders to make this technology useful. Video coding is known for being a burdensome task, and the recent Versatile Video Coding (VVC) standard introduced multiple encoding tools that pushed this complexity issue even further. In addition to that, the larger resolutions required to represent 360º videos only increase the encoding workload. This work aims to reduce this encoding cost challenge by proposing a heuristic for fast intraframe prediction of 360º videos with minimal coding efficiency penalties. The proposed heuristic exploits the texture distortion caused by the equirectangular projection to discard less relevant partition blocks and encoding tools, reducing the encoding time by 8.27% with a coding efficiency loss of only 0.34% BD-BR. Compared to related works, the proposed method obtains the best trade-off between coding efficiency and encoding time reduction.

ABSTRACT. Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at \url{github.com/MorganaMacedo/AxPPA_HTH}), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA's resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95\% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.

ABSTRACT. The object of study in this work is dynamic 3D point clouds. These clouds are formed by a set of points in a three-dimensional space that represent a real scene or object. With the increased accessibility to 3D digital model generation technologies, the need to store and transmit this type of content also grows. Just as with 2D images and videos, point clouds are prohibitively expensive to store and transmit in their original state. Therefore, it is essential to reduce the amount of data required to represent the clouds with the least possible loss of quality. However, this encoding step has a high computational cost. Thus, the method proposed in this work to reduce computational cost is based on reducing the complexity of the block partitioning stage in the reference software HEVC Test Model (HM) of the High Efficiency Video Coding (HEVC) standard, used as the dynamic point cloud encoding stage, provided in the Video-based Point Cloud Compression (V-PCC) standard reference software. For this, a decision tree model was proposed, capable of predicting, based on the characteristics of each block to be encoded in a given point cloud frame, whether a block should continue to be partitioned into smaller blocks or not, in order to reduce encoding time by avoiding costly steps.

ABSTRACT. Approximate computing attempts to maximize area and energy savings for a trade-off between quality and efficiency. This paper investigates the approximate squarer and divider units in the calibration procedure for radio astronomy called StEFCal (Statistically Efficient and Fast Calibration). The StEFCal circuit uses two squarer units from the literature, i.e., radix-4 (AxRSU) and SquASH, and iterative-based Newton-Raphson (NR) and Goldschmid (GLD) dividers. We demonstrate the efficiency of StEFCal using the approximate arithmetic operators from the Pareto-optimal that show the area- and power-quality trade-off. The results show that using the AxRSU combined with the NR divider improves the Mean Square Error (MSE) by 4.24\%, with 58x more energy saving than the state-of-the-art.

ABSTRACT. Os sistemas de codificação de vídeo evoluíram consideravelmente nos últimos anos, com destaque para o Versatile Video Coding (VVC), que proporciona uma alta eficiência de compressão. Contudo, mesmo as implementações mais eficientes do VVC, como o VVenC, ainda demandam recursos computacionais elevados. Um dos métodos utilizados pelo VVenC para realizar a etapa de estimação de movimento é o algoritmo Test Zone Search (TZS), que demanda elevado custo computacional. Portanto, o objetivo deste trabalho é propor uma otimização do algoritmo TZS na implementação do codificador de vídeo VVenC para reduzir o tempo de execução do processo de codificação. Uma análise foi conduzida para identificar o comportamento do algoritmo, a partir da qual foi desenvolvida a otimização proposta. Os resultados experimentais demonstraram que a melhoria proposta foi capaz de, em média, reduzir 0,474% o tempo total de codificação, com um impacto de apenas 0,159% no BD-BR.

ABSTRACT. A codificação de vídeo tem um papel essencial nos dias de hoje, possibilitando a transferência de conteúdos em vídeo em várias plataformas físicas e online. No entanto, o processo de codificação de vídeo é extremamente custoso computacionalmente, necessitando de hardware dedicado para aplicações eficientes em tempo real. O desenvolvimento de hardware dedicado para a codificação de vídeo deve lidar com várias limitações físicas, como dissipação de potência, área demandada no chip e questões relacionadas a memória (tamanho, acessos e consumo de energia). A Estimação de Movimento (ME) é a etapa de codificação mais importante nos codificadores de vídeo atuais, porém, também é a mais exigente em termos de tempo, capacidade computacional e uso de memória. Para abordar este problema, este artigo propõe o uso de blocos comprimidos na ME, permitindo um cálculo eficiente da Soma das Diferenças Absolutas (SAD) sobre uma quantidade reduzida de dados, diminuindo a demanda de memória interna e economizando energia tanto na memória interna quanto no processamento do SAD. Este artigo propõe uma arquitetura de hardware dedicada para um compressor de blocos e uma árvore de SAD configurável, que opera sobre os dados dos blocos comprimidos. Os resultados da síntese ASIC demonstraram que o uso de blocos comprimidos pode reduzir o tamanho da memória interna da ME e sua dissipação de potência em até 75%. Além disso, a arquitetura SAD eficiente proposta pode alcançar até 58,6% de redução na dissipação de potência no processamento do SAD.

ABSTRACT. The Versatile Video Coding (VVC) standard provides new tools that enable higher compression rates when compared with previous standards, as well as greater adaptability to different types of videos. To do that, VVC requires a very high computational effort when compared with previous standards, mainly at the Inter-Frame prediction step. Therefore, many challenges are still open to reduce this problem and to contribute to a wider use of this standard in real applications. This work presents a deep investigation and analysis of published works targeting the computational effort reduction of VVC Inter-Frame prediction. As a result, eighteen works were categorized and described, and the research opportunities that are still open to novel contributions were discussed.

ABSTRACT. This paper presents a comparison between two LDOs (Low Dropout Regulators) developed for a PMIC (Power Management Integrated Circuit) responsible for powering a 32-bit microcontroller based on the RISC-V microarchitecture, designed in 22 nm technology. The microcontroller will be integrated with a radio frequency interface for IoT (Internet of Things) applications. Two LDOs were designed: one with external compensation and the other a capacitor-less LDO. Both operate with an input voltage of 2.5V, an output voltage of 0.8V, and a maximum current of 150mA. The externally compensated LDO exhibited greater stability in response to load variations and a higher PSRR (Power Supply Rejection Ratio), while the capacitor-less LDO demonstrated faster regulation speed and occupied a chip area similar to the externally compensated LDO.

ABSTRACT. A low noise CMOS Bandgap Voltage Reference used in a ADC for biomedical applications is designed in this paper. It uses Chopper Stabilization Techniques in different parts of the circuit, to reduce low frequency noise. The circuit consumes roughly 1µA and creates a precise voltage of about 1.225 V. The temperature range is -40 to 125 ºC and the circuit is very robust in supply voltage and corners variations. Simulations show a typical temperature coefficient (TC) of 12.4 ppm/ºC in the extended temperature range and 3.9 ppm/ºC in the specification range. The output integrated noise from 0.1Hz to 10Hz is 8.17µVRMS and from 1µHz to 1kHz is 10.07µVRMS.

ABSTRACT. This work presents a compact multi-bit multi-order finite impulse response (FIR) digital-to-analog converter (DAC) design for internet of things (IoT). It is accomplished in 65-nm CMOS technology merging the 4-order FIR filter and 4-bit calibration-free DAC as one block. This FIR DAC achieves over -20-dB out-band noise filtering with 0-dBFS in-band signal input, and demonstrates a maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.26% and 0.12% in 502.5-mV full-scale range while consuming a power of 0.53-mW and occupying 0.052-mm² area.

ABSTRACT. In recent years, the demand for efficient power man- agement solutions in electronic devices has increased significantly, especially for microcontrollers operating in low-power modes. This article presents the design and implementation of a Pulse Frequency Modulation (PFM)-based buck converter for applica- tions in 32-bit microcontrollers using 22nm CMOS technology. The methodology involves the development of a Constant On Time (COT) architecture that maintains a fixed duration for the activation of the high-side MOSFET, using a monostable multivibrator to generate the necessary timing signals. The performance of the converter was simulated under various load conditions and process corners to evaluate its efficiency and output characteristics. The results show that the proposed buck converter achieves high efficiency, with peak values above 95%, while maintaining low output ripple. Specifically, the converter exhibits an efficiency of 93.4% at a load of 1mA, with output ripple voltages as low as 2.20 mV under ideal conditions. The contributions of this work lie in the advancement of PFM converter technology for modern microcontroller applications, demonstrating the potential of 22nm CMOS processes to improve power efficiency and performance.

ABSTRACT. Power management ICs commonly use DC-DC converters because of their higher efficiency than LDO counterparts. DC-DC converters operate in different modes to keep efficiency constant over different loads, reducing quiescent and dynamic power losses. Switching between modes requires a well-behaved, configurable and adaptable digital control circuit to avoid hazardous states. This paper presents a digital control circuit for a dual-phase buck converter divided into synchronous and asynchronous parts to meet power management requirements. The digital control manages transitions between three different converter modes according to load current: low-power-mode (LPM), single-phase mode (SPM), and dual-phase mode (DPM). Asynchronous logic is responsible for switching control and protection mechanisms while synchronous logic implements time-dependant functionalities. The asynchronous part was designed with STG models and synthesized into a map of standard cells and primitive analog-to-asynchronous (A2A) elements with the Petrify and MPSat tools.

ABSTRACT. With the advancement of semiconductor technologies, the need for efficient power management solutions in integrated systems, such as RISC-V architecture-based microcontrollers, becomes increasingly critical. However, there is a lack of studies comparing current reference architectures in terms of performance and robustness, particularly in 22nm technologies. In this paper, we present a comparative analysis of two current reference designs implemented in the same technology—referred to as Reference Design A and Reference Design B. We focus on their approaches to thermal compensation, supply stability, and layout optimizations. Through simulations and experimental tests, we evaluate the performance of each design within a power management system that includes DC-DC converters and LDO regulators. Our results indicate that Design A exhibits superior power supply rejection with a PSRR of-85 dB, while Design B demonstrates enhanced energy efficiency and thermal stability, achieving a nominal current of 5.14 µA and a temperature coefficient of 16.21 ppm. These findings underscore the importance of balancing energy efficiency, thermal stability, and power supply variation rejection when selecting current references for lowpower, high-reliability applications, such as those in the Internet of Things (IoT).

ABSTRACT. A negative resistance multi-gated circuit (NRMGC) integrated with an NMOS cross-coupled pair is proposed in this design. The topology incorporates four parallel PMOS transistors, with two configured for cross-coupled differential operation and the other two providing a feedback negative resistance. This configuration effectively reduces phase noise from high-order frequency currents through cancellation. The added NMOS cross-coupled pair enhances the transconductance and headroom of the NRMGC, addressing its limited voltage swing. Implemented using TSMC 65 nm LP technology, the proposed VCO achieves a tuning range of 18 GHz to 20.4 GHz. With a high voltage swing and robust start-up, the design delivers exceptional phase noise performance at -110.4 dBc/Hz. Furthermore, it boasts an impressive Figure of Merit (FoM) of -190 dBc/Hz and consumes only 4.8 mW of power, highlighting its excellent overall performance.

ABSTRACT. In this paper, a new class of transformers is introduced, where the cyclical switching of N identical dc-to-dc converters into the signal path at fLO using an N-path passive mixer makes a k:m switched-capacitor (SC) dc-to-dc converter appear as a k:m RF transformer to input RF signals. The cyclical switching of the N k:m SC dc-to-dc converters up-converts their transfer function to the RF frequency of the input LO. The k:m N-path transformer provides a voltage (current) conversion ratio of k:m (resp. m:k) between its two ports, and hence, offers an impedance transformation capability of k2:m2 around a tunable center frequency, fLO. Additionally, the SC transformer provides a tunable high-selectivity filtering capability of a center frequency at fLO. Simulation results of a 65-nm CMOS 1:3 design verify the performance advantages of the proposed SC transformer. With a 450-Ω load attached to the output port and a 50-Ω input (1:9 impedance transformation ratio), the 1:3 8-path transformer design achieves input and output matching across a tuning range from 0.1 to 1 GHz, where S11 and S22 are less than –15 dB across the range. When both input and output ports are terminated in matched loads, the transformer exhibits almost identical S21 and S12 performance. The insertion loss of the SC transformer is below 2.75 dB over the tuning range. The SC transformer design achieves a noise figure below 4.2 dB throughout the 0.1-to-1 GHz range and obtains an IIP3 of +13.6 dBm when fLO is set to 500MHz. The power consumption of the design is below 4.79 mW.

ABSTRACT. Reconfigurable Intelligent Surface (RIS) representsa crucial technology for the advancement of wireless communica-tions, particularly in the context of 5G and beyond. To the best ofour knowledge, there is no work in literature which investigatesa possible link between circuit parameters, which are necessaryfor the representation of the unit cell and its reconfigurabilitycircuit, and the system parameters, in order to evaluate theperformance of a RIS-assisted communication. This work aimsto address this gap by establishing a link between the two typesof parameters. Another fundamental contribution concerns thestudy of the effects of quantization of the phase values associatedwith the unit cell on communication performance. In this paper,the scenarios with continuous and quantized phase values wereconsidered, as well as effects of the quantization, taking intoaccount the impact of circuit components within RIS-unit cells.

ABSTRACT. This paper investigates antenna mutual coupling in narrowband uniform linear arrays through Thévenin network modeling. After an in-depth analysis, we derive a Thévenin network representing a given mutual coupling matrix and develop a method to achieve an equivalent decoupled model. This approach can significantly reduce computational and memory requirements in practical applications.

ABSTRACT. This paper presents the design and modeling of a Bluetooth Low Energy (BLE) All-Digital Phase-Locked Loop (ADPLL) for 28 nm CMOS technology. A behavioral model was developed and implemented using event-driven simulation technique to validate the ADPLL specifications. To anticipate process variations on DCO and TDC components, a new method is introduced to integrate inaccuracies into the model, improving the behavioral model realism. The model was designed using Python language targeting in-band phase noise of -95 dBc and -108 dBc at 1 MHz, meeting BLE target requirements.

ABSTRACT. This paper presents a carrier-based impulse radio ultra-wideband (IR-UWB) transmitter specifically designed for on-cortex implants and seizure forecasting applications. It utilizes advanced 28 nm HPC TSMC CMOS technology. The compact design occupies 0.043 mm², making it suitable for integration within a 1 mm², 49-channel neural recorder. The transmitter operates with a pulse repetition frequency of 770 MHz and a central frequency of 4.8 GHz, aiming to achieve a high output energy of 500 picojoules per bit. Despite its low voltage operation, with a supply voltage of 1.2 V, the transmitter delivers an output peak-to-peak differential voltage amplitude of 2.32 V. This high output voltage amplitude is achieved through an innovative antenna driver, enhancing energy efficiency per bit by up to 12.8%. This results in a competitive figure of merit of 2.98 W / (Hz · J · mm²).

ABSTRACT. Electric grids have been restructured with Smart Grids (SGs), and the deployment of Advanced Metering Infrastructure (AMI) systems is a fundamental part of this process. An AMI system consists of Smart Meters (SMs) that collect energy consumption data and send it to the utility company through Data Aggregation Points (DAPs). Thus, methods to determine the appropriate quantity and positions of DAPs become necessary. In this context, this work proposes a method called ePlace, which determines the minimum number of DAPs and their positions using the K-Means algorithm, ensuring that smart metering applications can adequately transmit data through a Long Range Wide-Area Network (LoRaWAN) network. The proposed method is compared to three related methods: KM, KMD, and Place, through simulations, and the results show that the ePlace method reduces the required number of DAPs by up to 42.86% while achieving communication performance - evaluated through metrics such as packet delivery delay and energy consumption – similar to the other methods, even with a lower number of DAPs.

ABSTRACT. Integrated photonics is an emerging field that has been of interest to numerous scientists and engineers in recent years. This field has enabled a wide range of applications, such as fibre optic communications, quantum computing or artificial intelligence. More specific applications of this technology can be found in a variety of astrophysical instruments. These technologies provide new functionalities within a remarkably small space and aim to reduce the cost and consumption and enhance performance. One of the major limitations of traditional wavefront sensors (WFS) used in solar adaptive optics (AO), such as Shack-Hartmann (SH) or plenoptic cameras, is the requirement to form an image of the Sun with a minimum resolution in order to compute and correct wavefront aberrations. To overcome this boundary, this work presents a mathematical description based on the scattering matrix of a wavefront sensor grounded in the integrated photonics (IP-WFS) for solar telescopes.

ABSTRACT. The development of pseudo-random number generators (PRNG) has attracted significant attention from researchers, due to, among others, its application to cryptographic systems. An effective method for developing a PRNG involves utilizing chaotic systems, however, the use of continuous-space chaotic systems makes the PRNG inefficient in terms of energy consumption. In this context, we propose an energy-efficient PRNG based on a discrete-space chaotic map employing approximate computation. Using an Approximate Radix-4 Multiplier Unit in the map's implementation reduces the complexity of its single complex calculation, which is an integer multiplication, aiding both its energy efficiency and its performance. The fast version of the PRNG has a 4.39 times increase in throughput compared to the state-of-the-art, along with a 74\% reduction in energy consumption. The lightweight version achieves a 85.6\% area reduction and 90.57\% lower energy consumption, with only a 37\% throughput reduction. The use of approximate computing does not affect the PRNG's deterministic behavior, which is essential to applications in cryptography. The randomness of the generated sequences was verified through NIST tests.

ABSTRACT. Rotating machines, such as motors and pumps, are of crucial importance for industrial operations, but are prone to failure due to their increasing complexity. Condition-based monitoring and early fault diagnosis, especially through vibration analysis, are essential to avoid costly downtime. Although cloud computing is widely used for machine condition monitoring, it can be inefficient due to the high data transfer and resource requirements. Edge computing offers a solution by processing the data locally on the devices, reducing latency, bandwidth usage and energy consumption. This paper presents an IoT sensor node for vibration monitoring of electric motors and compares the efficiency of local feature extraction (edge processing) with transmitting raw data to a server and remote feature extraction (cloud processing). We show that local feature extraction leads to 65.7% lower energy consumption and 37% faster execution time than cloud processing.

ABSTRACT. The modernization of electrical systems, driven by the increasing penetration of renewable energy sources such as Photovoltaic Generation (PVG) and Wind Generation (WG), presents challenges to the stability of the Electrical Distribution Network (EDN). This work proposes the Distribution Network Reconfiguration (DNR) of the Auroras Campus, Ceara, using the Particle Swarm Optimization (PSO) algorithm to optimize the EDN with PV generation. PSO, inspired by the collective behavior of animals, seeks the best configuration of sectionalizing switches to ensure efficiency. The methodology was tested on a 33-bus and 37-line system, considering different scenarios and PVG generation curves over 24 hours. The results show a significant reduction in energy losses, from 4859.648 kWh to 3347.599 kWh per year, approximately 15%, proving the effectiveness of the methodology used.

ABSTRACT. In the Internet of Things (IoT) era, the demand for sustainable and autonomous wireless sensor nodes has surged, driven by the need for efficient environmental monitoring and management. This paper presents the design and implementation of a sustainable, energy-autonomous, and battery-free wireless sensor node leveraging LoRaWAN connectivity. The proposed node operates seamlessly in Activation By Personalization (ABP) and Over-The-Air Activation (OTAA) modes, ensuring robust and flexible network integration. Powered by energy harvesting techniques, specifically solar cells, the sensor node eliminates dependency on traditional batteries, enhancing sustainability and reducing maintenance costs. Integrating a low-power microcontroller and optimized power management strategies ensure continuous operation under variable environmental conditions. Comprehensive experimental evaluations demonstrate the node’s capability to maintain reliable communication and data transmission over long distances while effectively managing energy resources. The results highlight the potential of this solution in various IoT applications, including environmental monitoring, smart agriculture, and industrial automation, contributing to the development of sustainable IoT infrastructures.

ABSTRACT. Este trabalho apresenta o desenvolvimento de um simulador web interativo para a arquitetura RISC-V, focado no conjunto de instruções RV32I. O simulador foi implementado usando TypeScript e Angular, permitindo interação direta com código em linguagem de montagem. Com um design simples, o simulador se destaca pela capacidade de operar sem servidor, tornando-o acessível em vários sistemas. O simulador foi comparado às soluções disponíveis e demonstrou o menor consumo de memória, possibilitando seu uso em dispositivos com restrições de desempenho. A versão atual do simulador suporta a execução completa de instruções e pseudo-instruções RV32I.

ABSTRACT. The High Efficiency Video Coding (H.265/HEVC) standard is currently in a phase of its life cycle where hardware acceleration support is prevalent across modern video-enabled consumer devices. In contrast, its immediate successor, the Versatile Video Coding (H.266/VVC) standard, does not yet benefit from hardware accelerated encoding by any general-purpose or graphics processor. This works evaluates the current state of HEVC hardware acceleration on modern devices, including an Intel laptop processor, an Nvidia desktop graphics processor and a Qualcomm mobile processor. The results of this work provide an opportunity for researches to assess whether the impact in visual quality and bit rate caused by their own solutions aligns with the characteristics of devices available in the market.

ABSTRACT. This work explores the development of an edu- cational tool to assist in learning the cell placement process in integrated circuits. The objective is to create an interactive platform that allows users to visualize different cell insertion methods and their impacts on circuit performance. Placement and legalization algorithms were implemented in Python, using the Half Perimeter Wirelength (HPWL) to measure wirelength. The results show that the tool provides a practical and visual understanding of placement choices, enhancing learning in the field of integrated circuits.

ABSTRACT. The early stages of the physical design of VLSI circuits, referred to as floorplanning, are critical for achieving quality layouts since they directly affect the subsequent stages. A typical floorplanning flow consists of pin assignment, macro placement and power planning. However, pin assignment and macro placement are interdependent steps and their execution order affects the floorplanning outcomes. That is why they are often alternated. For instance, the standard florplanning flow in the open-source OpenROAD platform performs an initial random pin assignment followed by the macro placement and global placement, finishing with an extra pin assignment step. This way, the pin assignment step does not influence directly on the macro and global placement result. In this work we explore the floorplanning flow within integrated circuit (IC) synthesis using the open-source platform OpenROAD as a test case, by adding one extra step of non random pin assignment. The new proposed flow is tested and compared with the standard flow using two different macro placers available within OpenROAD. Our experimental results with OpenROAD’s FreePDK45 test circuits showed that the proposed flow achieves average improvements in wirelength and number of vias of 1.99% and 1.71%, respectively, for one of the macro placers, with improvements of up to 15.76% and 9.82%. Those results highlight the existence of room for optimization that still exists in the floorplanning stage.

ABSTRACT. RC oscillators are a promising alternative for low-power circuit designs, showing a good trade-off between area, power, and noise performance. For these circuits, the comparator is one of the fundamental blocks, and also one of the bottlenecks in terms of performance. In this work, the effect of the comparator’s non-idealities, in specific delay and offset, in the oscillation frequency of differential swing-boosted relaxation oscillators was investigated using analytical and simulation methods. Results show delay is a major factor affecting the oscillation frequency, while the oscillator is inherently robust to offset. These quantitative estimations may aid designers in achieving improved accuracy for the oscillation frequency in hindsight, without having to navigate through all circuit design phases.

ABSTRACT. Nuvens de Pontos se refere ao conceito de guardar uma imagem ou vídeo não como uma captura bidimensional, como é comum para câmeras tradicionais, mas sim como vários pontos capturados em três dimensões, que quando projetados em uma tela permitem a visualização do alvo capturado em vários ângulos e perspectivas. Essa tecnologia tem sido experimentada em várias implementações de software, entretanto dispositivos modernos se beneficiam do uso de codificadores dedicados em hardware para os formatos de vídeo utilizados na geração de uma nuvem de pontos no V-PCC. Esse trabalho avalia a viabilidade e quantifica o impacto das limitações do codificador incluso no chip SM7325, presente no celular Poco X5 Pro, dentro do contexto de codificação de Nuvens de Pontos. Os resultados deste artigo fornecem dados de referência sobre o impacto na qualidade e eficiência dos dados codificados pelo codificador HEVC presente no chipset Qualcomm SM7325 na compressão de nuvens de pontos dinâmicas. Esses dados podem ser utilizados para a avaliação de viabilidade e escolhas em relação a bitrate quando ponderando os parâmetros de um codificador de hardware para nuvens de pontos.