ABSTRACT. This paper presents a low-power and fast start-up crystal oscillator (XO) operating at 48 MHz. To reduce the start-up time (Ts) required to oscillate the crystal (XTAL) resonator, the XO uses a combination of two different techniques. A dynamic negative resistance boosting (DNRB) technique is utilized to efficiently control the duration of the boosted gm and total power consumption. In order to further improve the start-up speed, a novel technique to set the initial condition is used to increase the initial motional current amplitude. The proposed XO achieves a start-up time of 7.6 μs while it is powered by a 0.85V power supply and consumes 107μW of steady-state power and 1.9 nJ of start-up energy. The proposed techniques are implemented using CMOS transistors in 130nm BiCMOS technology occupying an active area of 0.004mm2.

ABSTRACT. This paper proposes a low-noise area-efficient voltage bandgap reference (BGR) for neural applications in 180 nm CMOS TSMC process. A single resistor is inserted between the base terminals of the BGR core replacing any extra CMOS circuitry for noise reduction achieving small area and low-noise. The resistor also influences the BGR output voltage value and the temperature coefficient (TC). By inserting this resistor in the BGR core, the flicker noise is reduced, which is significant in neural applications. Post-layout simulations and measurements of the BGR exhibit an output voltage of 0.9 V, a total noise of 15.88 muVrms between 0.1 Hz and 10 kHz within an area of only 0.009 mm^2. The TC in the application range of 0 ºC and 60 ºC is 32.67 ppm/ºC, and 55.23 ppm/ºC in the extended range of -20 ºC and 85 ºC.

ABSTRACT. This paper presents the analysis and design of a three-stage low-power CMOS-based voltage-controlled ring oscillator (VCRO) fabricated in standard 130nm BiCMOS technology. Using the fine and coarse frequency tunability features acquired by employing a variable RC network, the VCRO can work in three different industrial, scientific, and medical (ISM) bands. The theoretical model, corroborated by measurements, demonstrates that incorporating both capacitive and resistive frequency tuning features allows the VCRO to adapt its voltage-controlled oscillator gain (KVCO) variation according to demand. This makes the presented ring oscillator suitable for a broad spectrum of applications such as phase-locked loops (PLLs), where the voltage-controlled oscillator (VCO) must meet strict criteria. The VCRO is powered by a 0.75V supply and consumes only 1.7μW, 3.5μW, and 5.7μW of DC power at 13.56 MHz, 27.17 MHz, and 48.68MHz ISM frequencies, respectively. The circuit core occupies an area of 0.0012mm2.

ABSTRACT. This paper presents a rectifier with a power combiner for a millimeter-wave wireless power transmission system. The proposed circuit uses a diode fabricated in a 0.1 um GaAs process for rectification and mixing, and a metal layer create a transformer to synthesize the power. The rectifier and power synthesizer are integrated into a single chip. The chip has four input ports for 24 GHz WPT differential signals and 25 GHz RF differential signals, and one output port for DC and 1 GHz IF single-ended signals. The DC output can operate with a 100Ω load. For power generation, the most efficient DC conversion is achieved at 25.4GHz signal, where with a total input power of 26.2 dBm, DC conversion efficiency is 10.8%. The maximum DC power obtained is 51.8mW. As a mixer, it achieves a down-conversion gain of -15.6 dB.

ABSTRACT. This paper presents the analysis of the start-up time and injection locking in ring oscillators and develops an equation for the start-up time. This work introduces two low-power CMOS-based voltage-controlled injection-locked ring oscillators (VCILROs)—a three-stage and a nine-stage—designed and fabricated in a standard 130nm BiCMOS technology, aiming to validate the theory and compare their performance. Using the frequency tunability feature acquired by employing a variable RC network, the VCILRO provides the calibration feature to compensate for process, voltage, and temperature (PVT) variations. The oscillation frequency of both presented VCILROs can be locked to the injected reference signal to improve frequency stability. The three-stage and nine-stage oscillators are powered from a 0.9V supply and consume 8.9μW and 76.8μW of DC power at 50 MHz. The three-stage and nine-stage VCILROs occupy areas of 0.0015mm2 and 0.0048mm2, respectively.

ABSTRACT. This work investigates the use of the Discrete Walsh-Hadamard Transform (DWHT) for cryptographic applications, particularly within resource-constrained environments like microcontrollers such as RISC-V. DWHT’s use of adder and subtractor arithmetic operations makes it highly suitable for low-complexity algorithms. In order to enhance efficiency further, our work integrates various approximate adders (AxAs) such as AxPPA, COPY, ETA-I, LOA, and Trunc into both forward (DWHT) and inverse (IDWHT) transform architectures. Our approach outperforms existing methods from the literature regarding accuracy metrics, particularly for lower approximation levels (K = 1 to K = 3), with substantial improvements in PSNR and SSIM. Additionally, our designs significantly reduce power and area compared to existing hardware implementations, showcasing their potential for deployment in real-world cryptographic and hardware security applications.

ABSTRACT. Multiplication is a key operation in neural networks. To overcome the power efficiency challenges of designing dedicated hardware for neural networks, designers can explore approximate multipliers to reduce area and power while maintaining tolerable accuracy.In this work, we evaluate the power and accuracy trade-offs of adopting two approximate multiplier structures, AxMultV1 and AxMultV2, for image classification in neural networks. In these multipliers, we explore seven approximate 4:2 compressors from the literature and compare with  our proposed MAX4:2CV1 compressor. The adoption of our proposed compressor in multipliers provides power savings up to 56%, a delay reduction of 45.5%, and reduction in transistor count up to 48% compared to an exact multiplier. The multipliers based on the MAX4:2CV1 compressor can be considered suitable for classification tasks in neural networks, achieving 95.54% accuracy on the MNIST using a Multilayer Perceptron and up to 81.27% accuracy on the SVHN dataset with the LeNet-5 architecture, comparable to the accuracy of an exact multiplier.

ABSTRACT. Memristive systems are one of the most promising candidates for a post-CMOS era. They are small, energy-efficient, and are ideal targets for In-Memory Computation (IMC) via stateful logic. As adders are critical building blocks for any computing systems, improving them is an essential design goal. With the rise of Artificial Intelligence (AI), providing memristive adders that are optimized for Neural Networks (NNs) is extremely important. For this, we propose a Material Implication (IMPLY)-based adder algorithm in the serial topology that can preserve the weights in memory, which was not addressed in the State-of-the-Art (SoA). Our approach is 20% − 23% faster and requires 1% − 12% less energy when the adder is used repeatedly. We propose a flowchart for IMPLY-based algorithms that can represent the state changes of individual memristors and apply it to our adder. We embed our adder in a shift-and-add multiplier and evaluate the potential gains on the 8-bit quantized ResNet18. Our approach is up to 17% more energy-efficient and requires up to 20% fewer cycles for the inference than SoA adder.

ABSTRACT. The integer multiplier is a key component of digital systems, so reducing its power dissipation can lead to significant system-level power savings. It is well known that the workload in terms of input data vectors impacts circuit power dissipation. If there is a switching activity difference between the two input operands to a multiplier, the input assignment can have a significant impact on the multiplier power. Here, we explore the energy per operation of different multiplier configurations and point out some situations when it is worth considering activity-based input operand assignment to reduce power dissipation.

ABSTRACT. Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves exploring different approximation adder (AxA) configurations as a viable form of reducing power consumption in many applications. This work explores the use of AxAs in a hybrid watermarking technique that combines discrete Haar-Wavelet (DHWT) and discrete cosine transforms (DCT). The proposed hybrid method, HyDHWCT, integrates these transforms to improve robustness and imperceptibility in watermarking systems while optimizing for energy efficiency. We evaluate the performance of various AxAs, including Copy, ETA, LOA, Truncation (Trunc), VLSPPAs, and the AxPPA, regarding energy consumption, circuit area, and error resilience. Our results demonstrate that the AxPPA-based HyDHWCT offers superior accuracy and energy-quality trade-offs over other state-of-the-art AxAs. Specifically, the AxPPA on HyDHWCT with K = 1 achieves up to 72.85% energy savings and 88.32% area savings compared to the exact HyDHWCT while maintaining high accuracy, with a normalized cross-correlation (NC) of 0.9949 and a structural similarity (SSIM) of 0.9920 for the extracted watermark. These results make the AxPPA-based HyDHWCT a highly effective solution for robust and energy-efficient watermarking systems.

ABSTRACT. This paper explores the performance and energy efficiency of deploying Convolutional Neural Networks (CNNs) on IoT devices and FPGA-based edge nodes. A CNN model was trained for the Herbicide-Resistant Weed Dataset, using both floating-point precision and quantized integer at 2-bit precision. The floating-point model was evaluated on a Raspberry Pi 4, while the quantized model was deployed on an FPGA-based edge server using AMD/Xilinx’s FINN framework. The study compares the accuracy, latency, and power consumption of the models in both environments. The results demonstrate significant improvements in energy efficiency and inference latency when utilizing the FPGA-based edge server, highlighting the potential for FPGA-based accelerators in precision agriculture applications.

ABSTRACT. Vector-borne diseases have been a challenge to public health for decades. This work addresses the Aedes aegypti mosquito, one of the leading carriers of vector-borne diseases such as dengue. We propose to use classifiers based on neural networks and cheap IoT sensors to quickly identify mosquitoes of interest, thus allowing a fast response and preventing the spread of vector-borne diseases. Our implementation uses cheap resource-constrained microcontrollers, such as the ESP32 family, to implement mosquito detection solutions based on machine learning. We then analyze the technical aspects, such as our intelligent models’ numerical error analysis, resource degrada- tion time, and data accuracy optimization. Our results can direct solutions for applying technologies such as neural networks, the Internet of Things, and machine learning to combat vector- borne diseases, focusing on dengue, and explore the practical implementation of these solutions on low-cost hardware.

ABSTRACT. This paper introduces a novel approach for straw- berry maturity detection using YOLOv5x, an advanced Con- volutional Neural Network (CNN) model, within an automated harvesting system. Traditional methods for determining the ripeness of strawberries are labour-intensive and error-prone, highlighting the need for a more efficient solution. We present a prototype that utilizes this model to identify ripe strawberries from 2D images. This research focuses on the integration of YOLOv5x running on the single-board computer Raspberry Pi 5 and explores the implications for reducing labour costs and increasing efficiency in harvesting. The key contribution of this work is a highly efficient and low-cost solution for AI applications in agriculture, achieved by implementing a high- precision AI model on a Raspberry Pi 5 without the need for model optimization.

ABSTRACT. Spatial heterogeneity, or the variation of environmental conditions within a greenhouse, reduces productivity. High-definition heat maps can help address this, but generating them in greenhouses is challenging. This paper compares multi-spectral cameras and wireless sensor networks (WSNs) for this task, evaluating them based on eight criteria. Multi-spectral cameras excel in point density and sampling rate, while WSNs offer greater flexibility and lower costs. A hybrid solution combining both technologies, along with AI and robotics, could enhance efficiency in greenhouse monitoring.

ABSTRACT. In this work the design and implementation of a fully integrated ISO 11784/5 RFID reader front-end ASIC is presented, for both HDX and FDX transponder types. The ASIC was designed in a 0.18 μm CMOS-HV technology, and includes the two analog front-ends which are multiplexed to a single 10-bit, 8-bit ENOB ADC, and a digital signal processing unit. The digital block is integrated by a field-programmable, re-usable, set of IIR filters to further process the RFID signals, working @1.25MSPS and composed of ∼ 20k logic gates ( 61% utilization ratio). The designed ASIC area (PADs not included) is 0.8mm2.

ABSTRACT. This paper proposes a 1D residual convolutional neural network (CNN) for classifying arrhythmias based on electrocardiogram (ECG) signals. The additional residual blocks and skip connections effectively alleviate the gradient problem in deep neural networks by providing a direct path for gradient propagation and enhancing the feature information propagation. In addition, the SMOTE–Tomek technique was demonstrated in this work to mitigate the effects of class imbalance caused by a large amount of data during model training and effectively increase the SNR of the training set. The robustness of the model is increased by adding the cosine annealing technique and L2 regularization. The proposed model was evaluated with various performance metrics, resulting in an accuracy of 98.74%, sensitivity of 98.35%, specificity of 91.86%, precision of 97.95%, and F1 score of 98.14% on the MIT-BIH Arrhythmia Database. The result shows better performance for classifying previously unseen data for the proposed approach as compared to the state-of-the-art works.

ABSTRACT. We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient (D2) for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems.

ABSTRACT. In gait analysis, precise results typically depend on gold-standard techniques such as motion capture with kinematics cameras and force platforms in biomechanics labs. However, these methods are costly, time-consuming, and require controlled environments, limiting their accessibility for clinical and research use. This study investigates inertial measurement units as a cost-effective wearable circuit implementation alternative. We focused on extracting features from inertial data, such as acceleration and angular velocity. We derived metrics like speed and angular acceleration to approximate the accuracy of camera kinematic data. After extensive preprocessing of inertial data and kinematic datasets, we explored alternatives, including Pearson correlation and cross-correlation analyses, to identify significant relationships between the data sources. The highest correlated features were used to train machine learning models, which were then analyzed using clustering techniques to evaluate the consistency and reliability of the results. The findings show that certain inertial data aspects strongly correlate with kinematic outcomes, indicating that inertial data can replicate results traditionally obtained through more complex methods under specific conditions.

ABSTRACT. This paper presents the results of an investigation focused on estimating the pressure value in an elastic conduit located inside a developed physical model of the forearm. This research highlights the proposal of a machine learning (ML) model, a significant advance in this field, to estimate the pressure value in the elastic conduit. The proposal used a device to measure the electrical impedance in physical forearm models; these emulate muscle tissue's electrical and mechanical properties, an environmental control chamber where temperature and relative humidity are controlled, a controlled pressure generation system, and a machine learning (ML) model. The experiments were performed in two conditions: without and with control of the environmental variables. The multilayer perceptron (MLP) obtained promising results, reaching an R^2 value for the validation data higher than 94 % ducing the number of variables or dimensions for the ML model inputs revealed that the value of electrical impedance and environmental variables are essential. At the same time, geometrical variables are of low relevance. Finally, future work is planned to address strategies to reduce the electrical noise produced by the actuators during temperature control in the environmental control chamber, seeking to improve the accuracy in estimating the pressure in the elastic vessel.

ABSTRACT. Medical errors in disease diagnosis, particularly those reliant on imaging, pose a significant challenge in healthcare systems worldwide. The misinterpretation of medical images can lead to incorrect diagnoses, delayed treatments, and adverse patient outcomes. To address these challenges, this study explores the potential of collaborative intelligence through Federated Learning and Computer Vision in enhancing healthcare. By leveraging federated learning techniques, multiple healthcare institutions can collaborate without sharing raw data, thereby improving diagnostic accuracy and patient outcomes. To this end, the study presents a simulated case of data sharing between two institutions, both using the Alexnet architecture. At the end, considerations about the performance and role of Federated Learning are pointed out, developing a discussion about the role of collaborative learning for the application analyzed.

ABSTRACT. Non-volatile emerging technologies exploiting magnetic tunnel junction (MTJ) capabilities are presented as promising alternatives to conventional Content Addressable Memories (CAMs). In this paper, an eight-transistor-two-MTJ (8T2MTJ) NV Binary CAM based on a voltage-divider configuration is proposed along with a Dual Voltage Level Control Circuitry (DVLCC) and periphery design to drive search and write control signals through the Searchline. The design was evaluated under nominal, as well as mismatch and process variation through 1000 Monte Carlo simulations for write and search delay, energy, search error rate (SER), and search stability margins. In particular, compared to state-of-the-art designs, the proposed 144-bit NV-BCAM offers lower (1.8%) SER, at the expense of a slight increase in search delay and search energy per bit. However, our design offers DVLCC which allows combined search and write operations through a single VDD supply.

ABSTRACT. In physical design of VLSI circuits, placement and routing are responsible for finding cell positions and connecting them, respectively, significantly impacting the circuit layout quality. To cope with design complexity, they were originally solved separately in a divide-and-conquer approach, resulting in a decoupling that often leads to poor solutions. To mitigate this problem, a few techniques seeking to integrate those steps have recently emerged. Unfortunately, some of those techniques do not consider the detailed placement information and thus, it is hard to evaluate their outcomes. In this paper we present GRCMO, a technique that optimizes Global Routing by moving a few cells to their medians respecting the detailed placement rules, and rerouting the affected nets. GRCMO was implemented in the well-established open-source platform OpenROAD, thus making possible its use within a complete RTL-to-GDSII flow. Experimental results using the ISPD 2018 Contest circuits showed that, in comparison to the standard global routing solutions from OpenROAD, GRCMO is able to reduce the estimated wirelength by 0.43%, on average, and from 0.5% up to 0.7% for the biggest circuits, requiring less than 20 iterations and moving 2.61% of the cells, on average.

ABSTRACT. Advancements in technology scaling have improved circuit performance and energy efficiency. However, they have also introduced challenges, including increased leakage, radiation susceptibility, and aging effects. As reliability becomes a crucial concern, traditional average reliability methods frequently fail to account for critical circuit conditions. This paper introduces the Single-Pass Critical Input Vectors Detection (SP-DCIV) method, which addresses these limitations by focusing on logic gate error masking through backpropagation analysis. By identifying critical input vectors posing the greatest reliability risks, SP-DCIV offers a more targeted and efficient approach to enhance circuit reliability. To validate our method, SP-DCIV was compared to the PGM reliability method, and the results were found to be equivalent. SP-DCIV demonstrates a fast and computationally efficient solution for detecting critical input vectors in modern circuits.

ABSTRACT. Accurate timing estimation is critical for the design closure of modern integrated circuits. However, significant discrepancies often arise between pre-route and signoff delay estimations due to factors such as inaccurate wire load models, and the complexities introduced by routing. This paper presents a machine learning-based approach that aims to correlate the pre-route and the signoff delay estimations by predicting the delta or difference between them, with the goal of enhancing early-stage design accuracy. Our approach effectively reduces timing uncertainty, enabling faster convergence towards signoff quality, and demonstrates potential to streamline the timing closure process. Experimental results show that the proposed model achieves high prediction accuracy, achieving up to 60% RMSE reduction, thus, making it a valuable tool for improving the efficiency of VLSI design methodologies.

ABSTRACT. The continuous advancement of communication systems necessitates the development of algorithms capable of identifying and correcting errors that may arise during data transmission and storage. This pursuit of reliability is particularly crucial in critical systems and sectors that are challenging to access, such as space exploration, passenger transportation, and financial services. In this context, the Error Correction Code (ECC) is a fundamental tool for providing a certain degree of reliability to these systems. This research proposes a novel technique to enhance the error correction capacity of ECCs by leveraging region overlapping. Specifically, we propose correcting data areas protected by more than one ECC, which allows for the inference of logical correlations between ECCs, thereby augmenting their error detection and correction capability. Our focus is bidimensional codeword structures, commonly known as 2D-ECCs, which entail a hierarchical arrangement of ECCs. We evaluated the ECC proposal, comparing its error correction and detection capabilities. Through this evaluation, we aim to demonstrate the technique’s efficacy in bolstering the reliability and resilience of communication systems, particularly in critical domains where precision and accuracy are paramount.

ABSTRACT. The increasing demand for wearable and portable IoT devices necessitates alternatives to traditional battery-powered systems, leading to the emergence of RF energy harvesting as a viable solution. However, long-distance charging poses challenges due to diminishing RF power and increased losses with distance, highlighting the critical importance of improving the sensitivity of the harvesting circuit. In this work, we propose a highly sensitive UHF RF energy harvesting circuit by optimizing a combined RF-DC rectifier (RDR) with a DC-DC converted (DDC) based on a commercial 22nm fully-depleted silicon on insulator (FDSOI) technology. Flipped well transistors and feedback self-body biasing are used to design the RDR to adaptively tune threshold voltages while an ultra-low power frequency-adjustable feed-forward dynamic leakage suppression (FFDLS) two-phase clock generator is used for pumping the DDC to boost output DC voltage, achieving sensitivity enhancement without peripheral power overhead. Based on simulation results, our proposed circuit shows the highest sensitivity of -41.3dBm at 1V output under a 100Mohm load, making it a promising candidate for ultra-low power far-field wireless charging IoT applications.

ABSTRACT. Low-input voltage switched-capacitor (SC) DC-DC converters are highly sensitive to variables such as switch resistance, operating frequency, load current, and other specifications. Identifying the most appropriate topology is challenging due to the numerous possibilities, including Doubler, Dickson, Fibonacci, Parallel-Series, and others. This work presents a clonal selection algorithm (CSA) based approach for designing switched-capacitor DC-DC converters, which can discover and optimize non-conventional topologies to meet user-defined specifications. As a result of the CSA implementation, a charge-flow equation system based on incidence matrices is proposed to quickly solve the steady-state of arbitrary two-phase converters at a low computational cost. To validate the proposed CSA-based design approach, three DC-DC converters were performed, with voltage conversion ratios (VCRs) of 1.69 V/V (target 2 V/V), 2.48 V/V (target 3 V/V), and 3.18 V/V (target 4 V/V) under stringent conditions: load current of 100 nA, operating frequency of 1 MHz, switch ON resistance of 100 kΩ, input voltage of 0.2 V, and output capacitance of 100 pF.

ABSTRACT. This paper introduces an Ultra-Low Voltage (ULV) OTA topology combining a bulk-driven fully-differential input stage with local common-mode feedback (CMFB), a differential to single-ended converter based on an improved current mirror whose accuracy is boosted thanks to a ULV error amplifier, and a cascode output stage with optimal bias settings for proper operation with a 0.3V supply voltage. The proposed topology allows to accurately set the bias current in each circuit branch, thus guaranteeing a robust biasing despite PVT variations. The ULV OTA has been designed in the 180nm CMOS technology from TSMC, and can achieve a voltage gain as high as 56 dB with a power consumption lower than 2.35 nW. Results of parametric and Monte Carlo simulations have confirmed the strong resilience of the proposed OTA to PVT variations. Its capability to operate at a supply voltage of 0.3V with the above mentioned specs makes the proposed OTA ideal for analog applications in IoT systems and biomedical devices.

ABSTRACT. This paper presents the design and system integra- tion of low-power analog and digital building blocks intended for DC-DC buck converters used in IoT applications by using time-based control techniques. Each building block has been independently simulated to extract the relevant parameters for the full system. Simulation results in steady-state behaviour of the DC-DC buck converter and its system efficiency using open- source CAD tools are provided to demonstrate the effective operation of the time-based control. The maximum simulated efficiency yields 85.8% for a conversion from 3.3V to 1.8V and a 270mA load current, with a switching frequency of 1.9MHz. The blocks have been implemented in the Skywater open-source 130-nm CMOS process, with an estimated total area of 0.27mm2, from which the controller area represents only 4.4%.

ABSTRACT. In the rapidly evolving landscape of edge computing, the integration of neural networks (NNs) into Internet of Things (IoT) devices presents unique challenges related to resource constraints and real-time processing needs. This paper introduces the Neural Edge Acceleration Toolkit (NEAT), a scalable System-on-Chip (SoC) framework designed to facilitate the integration of RISC-V processors with customizable NN accelerators generated by the FINN framework. NEAT promotes flexibility and efficiency in edge applications by providing a robust architecture that adapts to varying workloads and hardware configurations. The framework leverages FreeRTOS for multitasking management, ensuring responsiveness to dynamic conditions. Through practical applications, including a case study on the DeepSat (SAT-6) Airborne Dataset, we demonstrate the effectiveness of NEAT in generating tailored SoC designs capable of real-time inference tasks. Our results highlight the framework's potential to streamline the deployment of sophisticated AI solutions in constrained environments.

ABSTRACT. This research investigates various configurations of the Zynqnet AI Engine to accelerate image classification tasks using the SAT-6 dataset and a 4-layer CNN. The C++ code for the hardware accelerator was translated into RTL using Vivado HLS and integrated with the Zynq Processing System on a ZedBoard Zynq-7000 ARM/FPGA SoC. The AI engine was configured to work with 32-bit floating point, 8-bit fixed point and 8-bit integer type operations, with different processing elements for parallelizing CNN tasks. Considering a 64-bit data memory bus in communication with the accelerator and despite having considered an 8-bit integer quantization, the variation in the number of processing elements does not indicate a considerable performance improvement. To address this, different communication architectures were designed to improve data transfer between the accelerator and DDR memory, with optional L1D and L2 cache enablement. The research analyzes CNN computation performance and FPGA resource usage (LUTs, FFs, BRAMs, DSPs) across configurations, providing insights into the trade-offs in FPGA-based CNN implementations, aiding the development of efficient, high-performance hardware accelerators for Deep Learning applications.

ABSTRACT. Multi-Party Computation in the Head (MPCitH) algorithms are appealing candidates in the additional US NIST standardization rounds for Post-Quantum Cryptography (PQC) with respect to key sizes and mathematical hardness assumptions. However, their complexity presents a significant challenge for platforms with limited computational capabilities. To address this issue, we present, to the best of our knowledge, the first design space exploration of MiRitH, a promising MPCitH algorithm, for embedded devices. We develop a library of mixed HW/SW blocks on the Xilinx ZYNQ 7000, and, based on this library, we explore optimal solutions under runtime or FPGA resource constraints for a given public key infrastructure. Our results show that MiRitH is a viable algorithm for embedded devices in terms of runtime and FPGA resource requirements.

ABSTRACT. Convolutional Neural Networks (CNNs) are widely used for optical character recognition of vehicle license plates in automatic license plate recognition (ALPR) systems. However, their high computational complexity makes meeting specific ALPR applications' time and cost requirements challenging. This work aimed to develop a CNN architecture and select a hardware acceleration technique to create a low-cost optical character recognition (OCR) system capable of real-time vehicle identification. We designed the CNN architecture with accuracy and simplicity in mind, and we chose the hardware acceleration technique based on silicon cost and performance. Our 8-bit quantized CNN achieved an accuracy of 97.11%, and the accelerator resulted in a latency of 4.21 ms and a throughput of 598 FPS. The solution offers accuracy and performance comparable to related work methods, using less than 20% of the hardware resources.

ABSTRACT. This study compares the implementation of a trained convolutional neural network (CNN) for epilepsy detection by analyzing an EEG signal on resource-constrained embedded platforms typically employed for IoT applications. CNNs, while effective in classifying EEG signals, are computationally demanding, leading to increased energy consumption on embedded platforms. We evaluate the ease of deployment, the time and energy performances on four different CPU embedded boards, in order to anticipate and guide future implementation of CNNs on embedded solutions.

ABSTRACT. Graphene-based biosensors are extensively used for several applications, such as detecting neurotransmitters and DNA. This paper presents the modeling and electrical characterization of graphene field-effect transistors (GFETs) and the design and validation of a 180 nm complementary metal–oxide–semiconductor (CMOS) front-end. The ambipolar-virtual-source model is used in Matlab and Virtuoso for the sensor's modeling, resulting in a good fit between the model and measurements. The CMOS front-end consists of a transimpedance amplifier, a fully differential amplifier, and a 12-bit, 1 MS/s successive-approximation analog-to-digital converter. The core area of the front-end is 970 µm × 500 µm. Post-layout simulations and measurements of the CMOS analog front-end show a transimpedance gain in the order of 14 kΩ and transient response capable of a readout of 10 kS/s per channel for a 32 GFETs array.

ABSTRACT. This paper presents the architecture and design considerations of an overvoltage and reverse polarity protection controller. The controller was developed to protect low-voltage electronics from load dump transient. The system was designed and fabricated in a BCD 130 nm 85V process. Measurement results demonstrate the functionality and performance of the controller and are comparable to other benchmarks in the market.

ABSTRACT. This paper presents a small-formfactor, low-voltage,and low-power CMOS frequency recording IC for stand-alone continuous glucose monitoring contact lenses. The proposed IC employed burst-pulse counting with reference pulse generation for reducing area occupation and power consumption. The prototyped chip in 22nm CMOS has demonstrated 0.034 mm2 form-factor and 1.3 nW with 0.4 V supply, which is sufficient for in-room-light-energy-harvested stand-alone continuous glucose monitoring contact lenses.

ABSTRACT. This work presents the design and implementation details of a reference current generator intended to be used in a temperature sensor. The reference generator produces a PTAT and a ZTAT current. The ratio of these currents contains the temperature information, which can be translated to time via integrator oscillators, and then from time to digital via a counter. To generate the currents, a MOSFET-based current generator supplied with 900 mV and consuming less than 450 nA is proposed. The simulation results show that the error of the current ratio when translated to temperature is less than ±1.7 °C at 32 °C and less than ±3.1 °C at –20 °C and 85 °C. The one-point calibration of the current generator was carried out through an exponentially scaled network of integrated resistors.

ABSTRACT. Space systems are increasingly complex. To address the challenge of reducing cost and schedule, NASA has provided a set of reusable components for flight software. This work presents an implementation of NASA's Operating System Abstraction Layer (OSAL) for the FreeRTOS operating system running on an Arm Cortex-M microprocessor, along with a case study mission based on NASA's Core Flight System (cFS). Neutron irradiation is used for early assessment of the software's reliability exposed to radiation-induced soft errors. Benchmark applications are tested in two scenarios: running directly on FreeRTOS and running within the cFS framework. The results show that the overhead of cFS negatively affects reliability, increasing the dynamic cross-section by up to 51%. However, this comes with the benefits of software portability and reuse of components with proven flight heritage.

ABSTRACT. As transistors dimensions shrink to nanometer sizes, the variability of their electrical parameters becomes a significant factor in the performance of integrated circuits. Random Telegraph Noise (RTN) is a time-dependent variability that changes the drain current (or threshold voltage) of metal-oxide-semiconductor field-effect transistors (MOSFETs) from one instant in time to the other, leading to jitter in oscillating circuits, such as ring and voltage-controlled (VCO) oscillators. This work evaluates the time-domain jitter caused by the RTN in a capacitive and a current-controlled ring oscillator-based VCO. Different concepts of jitter (absolute jitter, period jitter, and cycle-to-cycle jitter) are studied, focusing on the influence of time window sizes on the jitter amplitude. Monte Carlo simulations are employed for both oscillators, considering a modified SPICE simulator to properly include the RTN impact on the threshold voltage of the transistors.

ABSTRACT. It is presented a novel method for modeling Random Telegraph Noise (RTN) as a deterministic process using dynamic systems theory. Initial investigations are focused on Ion and Ioff current fluctuations in FinFET transistors (20 nm to 5 nm) analyzed via Lyapunov exponents. The model was further tested on a ring oscillator to evaluate RTN’s effect on stability, considering noise trap density. Strange attractors were constructed and analyzed to identify topological features indicative of RTN-induced chaos. This approach confirms the chaotic impact of RTN. It utilizes dynamic invariants like entropy and Lyapunov exponents to quantify RTN effects, offering lower computational complexity and faster execution compared to other methods. The computational complexity for calculating Shannon entropy is O(n), whereas for calculating the power spectral density (PSD) using the Fast Fourier Transform (FFT) is O(nlog⁡n). With the presented theory, it is possible to estimate the number of traps from the calculated entropy.

ABSTRACT. In recent years, there have been significant advancements in electronic device technology. However, these devices remain vulnerable to Single-Event Effects (SEEs), caused by the interaction of cosmic rays with sensitive regions, potentially leading to processing errors. Thus, it is interesting to investigate the correlation between cosmic ray events and the likelihood of processing errors, particularly concerning the interactions between specific particles and the sensitive areas of the devices. This work presents a study using the Geant4 tool to simulate the interaction of cosmic rays with FET devices and their potentially associated effects. Simulations involve hitting particles such as protons, alpha particles, positive and negative pions, as well as positive and negative muons. These are injected with energies ranging from 0.5 MeV to 100 TeV and at various angles of incidence. Simulations demonstrate that alpha particles generate the most electrons, which is especially relevant in outer space environments. Protons, which constitute the majority of cosmic rays, significantly affect SEEs not only in outer space and low Earth orbit but also at ground level. Although positive muons and pions have a lesser effect, they become prominent at lower altitudes, including at ground level. The angle of incidence is critical in evaluating SEEs, with planar technologies showing a higher occurrence of electron generation. In contrast, finFETs, although producing fewer electrons, exhibit a greater potential for generating bit flip currents.

ABSTRACT. This work presents an advanced behavioral simulation model for artificial synaptic transistors, developed to address the limitations of existing models in accurately capturing the dynamic behavior of Synaptic Thin-Film Transistor (STFT). Our model, derived from the charge transfer mechanism, offers a comprehensive emulation of the fundamental characteristics (Including: Output characteristic curve, Transfer characteristic curve, Long-Term Potentiation curve, Paired-Pulse Facilitation curve, Excitatory Post- Synaptic Current curve) of artificial synaptic transistors fabricated by aqueous solution process. 

ABSTRACT. Quantum computing offers revolutionary potential for data processing and the efficiency of information systems. This work investigates the impact of the Single Event Effect (SEE) duration on quantum circuit outputs using the Quantum Fault Injector (QuFI) and the Quantum Vulnerability Factor (QVF). We evaluate four distinct well-known quantum circuits, including the Bell circuit, to determine the probability of faults impacting the results and to understand the impact of these faults on the number of shots performed. After 270,336 injected faults in qubits, the results demonstrate significant variations in the robustness of the analyzed circuits, and it becomes evident that injections in theta tend to have a more significant impact on the final output, highlighting the importance of metrics like QVF for the development of reliable quantum systems.

ABSTRACT. The charging/discharging process of batteries produces heat, degrades their materials, and decreases their capacity; this problem demonstrates the requirement of a co-design for both the power and control stages of a battery charger/discharger to ensure stability and safety in the entire operating range of the process. The literature review shows several charging/discharging solutions, but there is a lack of design procedures that consider the power stage and control system. This work presents a co-design process for both the power and control stages of a battery charger/discharger based on a boost converter. The system uses a sliding-mode current controller and an adaptive proportional voltage controller to ensure global stability, impose a first-order behavior in output voltage, and limit the battery current derivative to prevent battery-accelerated degradation. Simulation results validate the co-design process because they fulfill the design requirements for the charging, discharging, and stand-by scenarios.

ABSTRACT. Low ripple levels in voltage and current is an issue of major importance in DC-link applications. The typical solution to reduce those ripples has been increasing the DC-link capacitor. However, reliability decreases when the capacitance increases. In addition, solutions based on power electronics devices raise the complexity of the system and the control techniques required for a suitable operation. This paper presents an adaptive capacitor approach for reducing the voltage and current ripple in AC-DC and DC-AC systems caused at twice the fundamental frequency. The presented solution allows to increase the effective impedance of the DC-link capacitor only at the oscillation frequency. In consequence, the ripple on the voltage and current are reduced according to the requirements of the application without a significant increment on the system capacitance.

ABSTRACT. Low-cost electronic circuits for Internet-of-Things (IoT) applications are based on system-on-chips (SoCs) with wireless connectivity. Among them, the ESP32 is a well-known microcontroller family adopted by a wide developer community. This SoC is selected in this work to implement a wireless remote power meter for energy quality analysis. The ESP32 provides a 12-bit analog-to-digital converter (ADC), but its performance is not suitable for precision applications. In this work, an offline ADC calibration is performed and the correction codes are stored in the ESP32 internal memory to optimize the analog-to-digital conversion to meet high-precision energy quality measurement standards. The results before and after calibration are shown to verify the effects of ADC linearity especially when measuring total harmonic distortion. We demonstrate that the ADC nonlinearity distorts the signal and introduce odd harmonic components that affect the reliability of the measured values, especially at the end of the scale. The look-up table based correction method can mitigate these effects and allows the use of a low-cost ADC with poor linearity in high-precision applications.

ABSTRACT. This paper presents a non-isolated multiport converter (NIMC) designed for microgrids that integrate renewable energy sources, such as photovoltaic panels and energy storage systems. The advantages of using multiport converter topologies are discussed, allowing for the efficient interconnection of multiple sources and loads, thereby facilitating optimal energy management. Through a detailed analysis, it is demonstrated that the proposed NIMC not only improves power density and system efficiency but also provides a robust solution for bidirectional charging and discharging of storage systems. Control strategies based on PID are implemented to regulate inductor currents and optimize the duty cycle, ensuring stable operation of the DC bus. Simulation results show high system performance, achieving efficiencies of up to 98.5%, validating the effectiveness of the proposed approach in energy management for microgrids.

ABSTRACT. Abstract — This paper analyzed how the addition of a Kelvin pin in 1.2 kV silicon carbide (SiC) MOSFETs influences switching losses. Using Spice simulations with the PSIM and LTspice soft-ware, we investigated the impact of the Kelvin pin on losses, con-sidering the associated parasitic elements. The Kelvin technology separates the current path of the gate driver from the power path. Three SiC MOSFETs with different packages were ana-lyzed: TO-247-3, without a Kelvin pin, TO-247-4, and TO-263-7, both with a Kelvin pin, with the latter also equipped with multi-ple source pins to reduce the equivalent parasitic inductances present at the source terminal. The results show that the addition of the Kelvin pin and multiple source pins significantly reduces switching losses, which can improve efficiency in high-frequency converters.

ABSTRACT. Most learned B-frame codecs with hierarchical temporal prediction suffer from the domain shift issue caused by the discrepancy in the Group-of-Pictures (GOP) size used for training and test. As such, the motion estimation network may fail to predict large motion properly. One effective strategy to mitigate this domain shift issue is to downsample video frames for motion estimation. However, finding the optimal downsampling factor involves a time-consuming rate-distortion optimization process. This work introduces lightweight classifiers to determine the downsampling factor. To strike a good rate-distortion-complexity trade-off, our classifiers observe simple state signals, including only the coding and reference frames, to predict the best downsampling factor. We present two variants that adopt binary and multi-class classifiers, respectively. The binary classifier adopts the focal loss for training, classifying between motion estimation at high and low resolutions. Our multi-class classifier is trained with novel soft labels incorporating the knowledge of the rate-distortion costs of different downsampling factors. Both variants operate as add-on modules without the need to re-train the B-frame codec. Experimental results confirm that they achieve comparable coding performance to the brute-force search methods while greatly reducing computational complexity.

ABSTRACT. This paper presents an evaluation of the Coarseto-Fine Spatio-Temporal Information Fusion (CF-STIF) network for enhancing the quality of compressed videos across multiple codecs, including HEVC, VVC, VP9, and AV1. The CF-STIF network leverages spatio-temporal fusion and deep learning techniques to reduce compression artifacts and improve video quality. The evaluation extends existing methods by employing multiple quality metrics such as PSNR, SSIM, LPIPS. The CFSTIF network has been integrated with the Spatio-Temporal Deformable Fusion (STDF) training scheme in order to execute the model. Results demonstrate that CF-STIF achieves the highest quality improvements for HEVC-encoded videos, with an average PSNR increase of 0.813 dB and superior visual quality as measured by SSIM. However, the performance significantly drops for other codecs, particularly AV1, highlighting the need for future adaptations to optimize CF-STIF for diverse compression standards.

ABSTRACT. Lossy video compression introduces visual artifacts that degrade video quality, where deep neural networks (DNNs) are effective in enhancement. However, conventional DNN-based methods often focus on a single video compression standard, limiting their deployment in multiple cases. To overcome this issue, this study introduces a multi-domain video quality enhancement architecture based on the Spatio-Temporal Deformable Fusion (STDF) technique. This method enables the model to enhance videos compressed with multiple codecs, maintaining reliable performance across standards. After trained, the proposed architecture was tested with videos compressed by the High EfficiencyVideo Coding (HEVC) encoder, the Versatile Video Coding (VVC)encoder, the VP9 codec and the AOMedia Video 1 (AV1) codec. Results show an average Peak Signal-to-Noise Ratio (PSNR) improvement between 0.228 dB and 0.787 dB.

ABSTRACT. Several high energy physics experiments suffer from coherent noise affecting their readout electronics. To solve that, the highly successful SAMPA chip is gaining a new successor, the SALSA front-end readout ASIC, which is going to be used in the EIC experiment of the Brookhaven National Laboratory, United States. This new integrated circuit is going to have a common mode noise subtraction, a non-linear filter that is based on finding median values between the many channels of the chip. To guarantee peak efficiency in the filter implementation, this work focuses on the filter’s core: the median finder. This part needs to have an efficient algorithm to be implemented in hardware, therefore this paper shows three approaches, two of which are original techniques for digital median finding. These three designs were implemented and verified in TSMC 65nm technology and lastly they were compared in terms of speed, area, power consumption and a preliminary evaluation of error tolerance.

ABSTRACT. Nowadays, speech acquisition, speech recognition, speech enhancement are the essential part in almost all speech applications, such as surveillance devices, mobile phones, smart - home, voice - controlled equipment, teleconference system. They play an important role in front-end applications for noise reduction and speaker identifi cation. Many modern devices use microphone array (MA) technology for achieving a better noise reduction and enhanced speech quality at the same time. MA beamforming exploits the spatial geometry, the coherence between MA signals, the characteristic of recording environ- ment, the designed confi guration of MA to form a steerable beampattern towards the sound source and suppress background noise, interference, competing talker and non-directional noise source. Minimum Variance Distortionless Response (MVDR) beamformer is an effective solution to extract the desired target speaker while removing the total noise power at the output. Unfortunately,the error of estimating the steering vector, the inaccurate calculation of covariance matrix of observed MA signals, the displacement of MA, the microphone mismatches, and the difference of microphone sensitives seriously degrades the MVDR beamformer’s performance in complex and annoying situations. In this article, the author proposed an adaptive updating covariance matrix according to the rapidly chang- ing environment to improve the robustness, the effectiveness of MVDR beamformer in complex recording scenarios. The obtained resulting has confi rmed the advantage of the author’s proposed technique in reducing speech distortion to 4.8 dB, eliminating noise level to 15.2 dB and increasing the speech quality in the term of signal-to-noise (SNR) ratio from 9.5 to 11.8 dB. This method can be integrated into a multi-channel system for serving as a crucial pre-processing step.

ABSTRACT. Even though Internet of Things (IoT) devices have enabled many Deep Learning (DL) applications to run closer to users, they do not scale to modern heavy-load DL algorithms due to their restricted processing and energy capabilities. One alternative is sharing the computational load with remote edge and cloud servers through offloading, exploiting the so-called IoT-edge-cloud continuum. However, diverse network conditions and hardware heterogeneity across the continuum pose significant challenges to deploying efficient offloading-based processing. To address these challenges, we propose HALOIC. HALOIC smartly distributes the workload based on networking/hardware runtime profiles and user-defined optimization goals to minimize either execution time or energy consumption. By leveraging the hardware heterogeneity, HALOIC achieves superior performance and energy efficiency compared to traditional offloading strategies, demonstrating its effectiveness in optimizing DL workload processing across the continuum.

ABSTRACT. Lithium-ion batteries have become a fundamental power source for a wide range of applications, and proper monitoring and control of these batteries is useful to ensure safe and efficient operation, avoid risks, and prolong their lifetime. Charging capacity testing is a crucial indicator of battery health and performance status, allowing to estimate battery autonomy and detect degradation mechanisms. This paper presents the design, implementation, and experimental results of a portable and low-cost electronic system called Core Phantom, developed to evaluate the charging capacity of lithium-ion batteries. The system can assess batteries up to 60V and allows setting the discharge current up to 5A and the cut-off voltage for the capacity test. The Core Phantom system uses an ATMega328P microcontroller as the central control unit, a controlled charging circuit, a thermal dissipation module, and additional components such as a real-time clock, SD card storage, and an LCD for the user interface. The design includes protection measures to ensure safe operation within the specified thermal ranges. The experimental results show discharge tests performed on three commercial lithium-ion batteries. The tests revealed significant discrepancies between the capacities reported by manufacturers and actual measurements, underlining the importance of performing rigorous evaluations before the design and implementation stages of lithium-ion battery cells or banks.

ABSTRACT. The growing demand for efficient solutions to integrate and control sensors and actuators in IoT devices highlights the complexity of traditional programming, which often requires advanced knowledge and familiarity with the hardware and communication protocols, making the process dependent on highly skilled labor. This paper explores a low-code approach for programming a microcontroller with data transmission over a LoRaWAN network, a widely used solution in IoT applications due to its long-range communication and low power consumption. Although low-code tools like XOD provide simplified programming methods, they present limitations in projects involving LoRaWAN communication. In this study, custom components were developed in XOD, enabling the programming of an ESP8266 microcontroller integrated with LoRaWAN and GPS modules. Through a case study, the coverage of the Everynet network in Rio Grande city was evaluated, demonstrating how the low-code approach can simplify the development, implementation, and rapid prototyping of IoT devices, making the process more accessible and efficient.

ABSTRACT. This paper presents a performance evaluation of the Backward Extended Kalman Filter (EKF) and Backward Unscented Kalman Filter (UKF) techniques for estimating the launch point of ballistic projectiles with data from a Weapon Locating Radar (WLR). This research is significant in the field of defense and radar technology. The proposed methods focus on backward extrapolating limited-time windows radar measure- ments to accurately determine the projectile’s launch position. This approach aims to optimize the WLR system performance in real-time operational scenarios by tilizing shorter detection periods. The study investigates the impact of measurement errors and observation time on the accuracy of the launch point estimation. Simulation results comparing the backward EKF and UKF methods demonstrate their effectiveness in providing precise launch position estimates, which are crucial for strategic defense operations and counter-artillery responses.

ABSTRACT. With the ongoing evolution of technology and the digitization of information, Ethernet-based network protocols have become increasingly prevalent. In scenarios involving explosive atmospheres, which were previously restricted to Fieldbus networks, Ethernet APL emerges as an alternative to bring digitization to process plants. In light of this growing trend, this work evaluates the replacement of the Profibus PA protocol with Ethernet APL, comparing their performances. The research focuses on the temperature control of an industrial furnace, a typical scenario in industrial plants. The results confirm that the implementation of Ethernet APL does not cause any losses in existing plants and offers additional qualitative advantages, as demonstrated in this work.