Talk Keyword Index

TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

Shortcuts: 3 A B C D E F G H I L M N O P Q R S T U V W Z

3
3GPP	148: Portable Power Tracer for USIM with Smart Analyzer
3PIP	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
A
ACL	167: MUD "IRL" - Implementing Manufacture Usage Description
advanced encryption standard	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
AE	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
AEAD	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Aegis	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
AES	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Aging	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Air Gapped Network	171: Demonstration of Exfilteration of Data through Smart Light Bulb (Internet of things)
Analog Hardware Trojan	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection
Analog PUF	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Analog/RF ICs
Application Inference	159: Application Inference using ML based Side Channel Analysis
architecture	Enabling a Secure Development Lifecycle for Hardware
Ascon	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
ASIC	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Authenticated encryption	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Authentication	FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection 164: Authentication of Consumables using Portable NQR Spectrometer 146: Remote Authentication of Low-Cost Devices using Unclonable IDs
Autoencoder	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
B
Backscattering side channel	160: Hardware Trojan Detection Using Backscattering Side Channel
Backward Trust	CAD for Security
Bias temperature instability	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
bitstream security	158: Boot and Runtime Bitstream Authentication for FPGAs
Blockchain	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain
Bluetooth Low Energy Protocol Stack	171: Demonstration of Exfilteration of Data through Smart Light Bulb (Internet of things)
BotNet	167: MUD "IRL" - Implementing Manufacture Usage Description
C
Cache Architecture	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Cache Partitioning	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
CAESAR	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
chaos	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme 151: Experimental Cryptanalysis : Case study on chaotic random number generators
Chaos-based random number generator	150: Security analysis of chaos-based no-equilibrium chaotic system
Circuit techniques	Circuit Techniques for Energy-efficient Hardware Security
colm	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Commodity Devices	149: The Hardened Adversarial VET Challenge
Computer Aided Design	CAD for Security
correlation power analysis	156: A SCA-resilient Design Based on Dynamic Reconfiguration Side Channel Attacks and Countermeasures
correlation power analysis (CPA)	165: Demonstration of Enhancing the Resilience against CPA Attacks for Three-Dimensional Chips with Power Distribution Network Noise
Counterfeit ICs
Countermeasures	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Covert Channel	A Fetching Tale: Covert Communication With The Hardware Prefetcher
Covert/side Channel Detection	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Cryptanalysis	150: Security analysis of chaos-based no-equilibrium chaotic system
Cryptographic hardware	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
D
Data Privacy	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
denial-of-service	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
Design Obfuscation	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Detection	149: The Hardened Adversarial VET Challenge
Differential Power analysis	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
DVFS	159: Application Inference using ML based Side Channel Analysis
Dynamic partial reconfiguration	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD) 158: Boot and Runtime Bitstream Authentication for FPGAs
dynamic reconfiguration	156: A SCA-resilient Design Based on Dynamic Reconfiguration
Dynamic voltage and frequency scaling	170: Software-controlled voltage differentials-based hardware fault attack
E
eCash protocol	163: PUF-based eCash
Edge Device	146: Remote Authentication of Low-Cost Devices using Unclonable IDs
Edge Security	167: MUD "IRL" - Implementing Manufacture Usage Description
electromagnetic	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
electromagnetic attack	156: A SCA-resilient Design Based on Dynamic Reconfiguration
electronic cash	163: PUF-based eCash
EM attack	Circuit Techniques for Energy-efficient Hardware Security
EM Emissions	159: Application Inference using ML based Side Channel Analysis
EM Sensor	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection
EM Side-channel attack	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Embedded systems	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
Embedded Systems Security	143: RASC: Enabling Remote Access to Side-Channels
Emerging NVM	ENTT: A Family of Emerging NVM-based Trojan Triggers
Encrypted Execution	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Encryption engines	Circuit Techniques for Energy-efficient Hardware Security
energy harvesting	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
experimental cryptanalysis	151: Experimental Cryptanalysis : Case study on chaotic random number generators
experimental demonstration	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
F
Fast Fourier Transformation	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
fault attack	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller 155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
Fault detection	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
fault injection	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Fault injection attack	170: Software-controlled voltage differentials-based hardware fault attack
Field Programmable Gate Array (FPGA)	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
finite field multiplier	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
flash memory	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Formal Method	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Formal methods	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
Forward Trust	CAD for Security
FPGA	FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists 158: Boot and Runtime Bitstream Authentication for FPGAs 155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs 154: RISC-V Secure Caches Demo on FPGA 149: The Hardened Adversarial VET Challenge 142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
FPGAs	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
FSM Extraction	Improving on State Register Identification in Sequential Hardware Reverse Engineering
functional attack	SURF: Joint Structural Functional Attack on Logic Locking
Fuzzing	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
G
Generic countermeasure	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Ground-up EM Leakage Modeling	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
H
hardware	Enabling a Secure Development Lifecycle for Hardware
hardware accelerators	152: Securing Accelerators with Dynamic Information Flow Tracking
hardware attack	169: System level attacks on HaHa platform
Hardware Performance Counters	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Hardware Reverse Engineering	Improving on State Register Identification in Sequential Hardware Reverse Engineering
Hardware Root-of-Trust	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Hardware Security	On the Impossibility of Approximation-Resilient Circuit Locking A Fetching Tale: Covert Communication With The Hardware Prefetcher 169: System level attacks on HaHa platform 161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming 160: Hardware Trojan Detection Using Backscattering Side Channel 155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs 149: The Hardened Adversarial VET Challenge 147: Hardware Demo of a Piezoelectric Based PUF for Hardware Security in IoT Devices 143: RASC: Enabling Remote Access to Side-Channels Enabling a Secure Development Lifecycle for Hardware
hardware security tools	Property Driven Hardware Security
hardware security verification	Property Driven Hardware Security
Hardware Trojan	160: Hardware Trojan Detection Using Backscattering Side Channel 149: The Hardened Adversarial VET Challenge
Hardware Trojans	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ## 172: A CAD Framework for Machine Learning based Hardware IP Trust Verification
Hardware Vulnerabilities	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
heterogeneous architectures	152: Securing Accelerators with Dynamic Information Flow Tracking
Holistic Platform	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
HW/SW Co-Design	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
I
IC camouflaging	On the Impossibility of Approximation-Resilient Circuit Locking
Image Analysis	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
ineffective fault	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Information Flow	CAD for Security
information flow tracking	Property Driven Hardware Security
infrared	FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection 142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Integrated Circuit	160: Hardware Trojan Detection Using Backscattering Side Channel
intermittent computing	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Internet of Things	171: Demonstration of Exfilteration of Data through Smart Light Bulb (Internet of things) 167: MUD "IRL" - Implementing Manufacture Usage Description
IoT	167: MUD "IRL" - Implementing Manufacture Usage Description
IoT security	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 168: Securing IoT Devices in Heterogenous Network Setting using Blockchain 146: Remote Authentication of Low-Cost Devices using Unclonable IDs
IP Trust Verification	172: A CAD Framework for Machine Learning based Hardware IP Trust Verification
L
laser injection	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Lattice-based Cryptography	Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
leakage	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Lightweight Cryptography	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers
Localized EM attacks	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
logic encryption	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
logic locking	On the Impossibility of Approximation-Resilient Circuit Locking SURF: Joint Structural Functional Attack on Logic Locking
Logic obfuscation	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Logic synthesis	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Logic Test	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Long-Short-Term-Memory	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Low voltage error	170: Software-controlled voltage differentials-based hardware fault attack
low-complexity	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
Low-power	Circuit Techniques for Energy-efficient Hardware Security
Low-Power Design	Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
M
Machine Learning	SURF: Joint Structural Functional Attack on Logic Locking 172: A CAD Framework for Machine Learning based Hardware IP Trust Verification 159: Application Inference using ML based Side Channel Analysis
Malware detection	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems ** 143: RASC: Enabling Remote Access to Side-Channels
Manufacture Usage Description	167: MUD "IRL" - Implementing Manufacture Usage Description
Master slave synchronization of chaotic systems	150: Security analysis of chaos-based no-equilibrium chaotic system
Meltdown	Secure Processor Architectures in the Era of Spectre and Meltdown
Micro-Architectural attacks	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
Micro-architecture	A Fetching Tale: Covert Communication With The Hardware Prefetcher
Microscopy	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
MILENAGE	148: Portable Power Tracer for USIM with Smart Analyzer
Morus	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
MUD	167: MUD "IRL" - Implementing Manufacture Usage Description
Multi-party computation	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
multi-tenant	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
N
Nearest-neighbor search	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
NetFPGA	149: The Hardened Adversarial VET Challenge
network vulnerabilities	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain
No-equilibrium chaotic system	150: Security analysis of chaos-based no-equilibrium chaotic system
Nuclear Quadrupole Resonance (NQR)	164: Authentication of Consumables using Portable NQR Spectrometer
Number Theoretic Transform	Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
NVM	ENTT: A Family of Emerging NVM-based Trojan Triggers
O
Obfuscation	On the Impossibility of Approximation-Resilient Circuit Locking SURF: Joint Structural Functional Attack on Logic Locking CAD for Security
On-Chip Sensor	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection
optimization	SURF: Joint Structural Functional Attack on Logic Locking
P
parity bit	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
Partial Reconfiguration	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Partially Homomorphic Encryption	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Penetration testing	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
Physical Unclonable Function (PUF)	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Physical unclonable functions	163: PUF-based eCash
Physically Unclonable Function (PUF)	147: Hardware Demo of a Piezoelectric Based PUF for Hardware Security in IoT Devices
Piezo Sensors	147: Hardware Demo of a Piezoelectric Based PUF for Hardware Security in IoT Devices
Power	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems ** 145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
power analysis attack	148: Portable Power Tracer for USIM with Smart Analyzer
Power attack	Circuit Techniques for Energy-efficient Hardware Security
power distribution network (PDN)	165: Demonstration of Enhancing the Resilience against CPA Attacks for Three-Dimensional Chips with Power Distribution Network Noise
power tracer	148: Portable Power Tracer for USIM with Smart Analyzer
Private-set intersection	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Process Variation	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Proximity Attack	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
PUF	146: Remote Authentication of Low-Cost Devices using Unclonable IDs
PUFs
Q
Quantitative Information-Flow	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
R
Random bit generator	150: Security analysis of chaos-based no-equilibrium chaotic system
random number generator	151: Experimental Cryptanalysis : Case study on chaotic random number generators
Ransomware	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Real-time Security	143: RASC: Enabling Remote Access to Side-Channels
Reconfigurable Fabric	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Recycled IC	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Resonance	164: Authentication of Consumables using Portable NQR Spectrometer
resource-constrained microcontroller	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Reverse Engineering	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits 157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Ring-oscillator (RO)	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
RISC-V	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme 154: RISC-V Secure Caches Demo on FPGA
S
SAT	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
SAT Attack	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
SAT attacks	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Secure auction	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Secure Caches	154: RISC-V Secure Caches Demo on FPGA Secure Processor Architectures in the Era of Spectre and Meltdown
secure intermittent architecture	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Secure Processor Architectures	Secure Processor Architectures in the Era of Spectre and Meltdown
Secure voting	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
secureboot	158: Boot and Runtime Bitstream Authentication for FPGAs
security	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator Enabling a Secure Development Lifecycle for Hardware
Security and Trust
Security architecture	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
Security Language	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Security policies	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
Security primitives	Circuit Techniques for Energy-efficient Hardware Security
security property languages	Property Driven Hardware Security
Sequential Reverse Engineering	Improving on State Register Identification in Sequential Hardware Reverse Engineering
Side Channel Analysis	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers Side Channel Attacks and Countermeasures CAD for Security
side channel analysis attacks	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Side Channel Attacks	159: Application Inference using ML based Side Channel Analysis
side channel countermeasures	Side Channel Attacks and Countermeasures
Side-Channel	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs Circuit Techniques for Energy-efficient Hardware Security
Side-channel Analysis	143: RASC: Enabling Remote Access to Side-Channels
side-channel attack	156: A SCA-resilient Design Based on Dynamic Reconfiguration
Side-channel attacks	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Side-Channel Leakage
SIFA	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Signal Processing	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Signature Attenuation Hardware	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
smart contract	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain
Snapdragon	159: Application Inference using ML based Side Channel Analysis
SoC	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists 159: Application Inference using ML based Side Channel Analysis
Spectral Features	159: Application Inference using ML based Side Channel Analysis
Spectre	Secure Processor Architectures in the Era of Spectre and Meltdown
Spectroscopy	164: Authentication of Consumables using Portable NQR Spectrometer
Split Manufacturing	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
SRAM	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Stable Matching	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
State Register Identification	Improving on State Register Identification in Sequential Hardware Reverse Engineering
statistical fault analysis	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
statistical security models	Property Driven Hardware Security
STELLAR	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
structural attack	SURF: Joint Structural Functional Attack on Logic Locking
system level attack	169: System level attacks on HaHa platform
System Monitoring	143: RASC: Enabling Remote Access to Side-Channels
System-on-Chip security	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
T
taint tracking	152: Securing Accelerators with Dynamic Information Flow Tracking
tamper detection	FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Test chip and Measurement	Circuit Techniques for Energy-efficient Hardware Security
three-dimensional (3D) integration	165: Demonstration of Enhancing the Resilience against CPA Attacks for Three-Dimensional Chips with Power Distribution Network Noise
Time-Series	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Toeplitz matrix-vector product	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
TPM	158: Boot and Runtime Bitstream Authentication for FPGAs
Transistor-level Programming	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Trigger circuit	ENTT: A Family of Emerging NVM-based Trojan Triggers
Trojan	ENTT: A Family of Emerging NVM-based Trojan Triggers
trust	Enabling a Secure Development Lifecycle for Hardware
TrustZone	170: Software-controlled voltage differentials-based hardware fault attack
U
Unclonable	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
Unrolled Architectures	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers
USIM	148: Portable Power Tracer for USIM with Smart Analyzer
V
verification	Enabling a Secure Development Lifecycle for Hardware
Voltage differential	170: Software-controlled voltage differentials-based hardware fault attack
Vulnerability Database	CAD for Security
W
watermarking	FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Z
zynq	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Zynq-7000	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs