Talk Author Index

TALK AUTHOR INDEX

Shortcuts: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A
Acar, Burak	150: Security analysis of chaos-based no-equilibrium chaotic system
Aftabjahani, Sohrab	Enabling a Secure Development Lifecycle for Hardware
Aghassi-Hagmann, Jasmin	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Ahmad, Sagheer	Enabling a Secure Development Lifecycle for Hardware
Alam, Manaar	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Ampadu, Paul	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Ariando, David	164: Authentication of Consumables using Portable NQR Spectrometer
Asadizanjani, Navid	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Ashraf, Mohammed	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Aysu, Aydin	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
B
Baehr, Johanna	Improving on State Register Identification in Sequential Hardware Reverse Engineering
Bai, Yunkai	143: RASC: Enabling Remote Access to Side-Channels
Becker, Joachim	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Beerel, Peter	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Bete, Nahome	156: A SCA-resilient Design Based on Dynamic Reconfiguration 162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Bhattacharya, Sarani	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Bhunia, Swarup	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment SURF: Joint Structural Functional Attack on Logic Locking 172: A CAD Framework for Machine Learning based Hardware IP Trust Verification 169: System level attacks on HaHa platform 164: Authentication of Consumables using Portable NQR Spectrometer
Brunner, Michaela	Improving on State Register Identification in Sequential Hardware Reverse Engineering
C
Calhoun, Jeff	163: PUF-based eCash
Carloni, Luca	152: Securing Accelerators with Dynamic Information Flow Tracking
Castillo, Melissa	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Chakraborty, Prabuddha	SURF: Joint Structural Functional Attack on Logic Locking 172: A CAD Framework for Machine Learning based Hardware IP Trust Verification
Chatterjee, Baibhab	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Chattopadhyay, Anupam	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Chawla, Nikhil	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 159: Application Inference using ML based Side Channel Analysis
Che, Wenjie	163: PUF-based eCash
Chen, Suyuan	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
Cheng, Chia-Lin	160: Hardware Trojan Detection Using Backscattering Side Channel
Chielle, Eduardo	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Colombier, Brice	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Cronin, Patrick	A Fetching Tale: Covert Communication With The Hardware Prefetcher
Cruz, Jonathan	SURF: Joint Structural Functional Attack on Logic Locking 172: A CAD Framework for Machine Learning based Hardware IP Trust Verification
D
Danger, Jean-Luc	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Das, Debayan	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
De, Vivek	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Deng, Shuwen	154: RISC-V Secure Caches Demo on FPGA Secure Processor Architectures in the Era of Spectre and Meltdown
Di Guglielmo, Giuseppe	152: Securing Accelerators with Dynamic Information Flow Tracking
Diehl, William	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Dinu, Daniel	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Dong, Xiaofei	148: Portable Power Tracer for USIM with Smart Analyzer
Doroslovacki, Milos	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Duncan, Adam	143: RASC: Enabling Remote Access to Side-Channels 142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Dutertre, Jean-Max	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Dutta, Raj Gautam	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Dutta, Swastika	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
E
Ergün, Salih	151: Experimental Cryptanalysis : Case study on chaotic random number generators 150: Security analysis of chaos-based no-equilibrium chaotic system
F
Fang, Hongyu	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Faramandi, Farimah	CAD for Security
Forte, Domenic	143: RASC: Enabling Remote Access to Side-Channels
French, Matthew	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation 149: The Hardened Adversarial VET Challenge
Fritzmann, Tim	Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
G
Gerstlauer, Andreas	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
Ghosh, Santosh	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Ghosh, Swaroop	ENTT: A Family of Emerging NVM-based Trojan Triggers
Gnad, Dennis	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
Gui, Yutian	156: A SCA-resilient Design Based on Dynamic Reconfiguration 158: Boot and Runtime Bitstream Authentication for FPGAs
Guin, Ujjwal	146: Remote Authentication of Low-Cost Devices using Unclonable IDs Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Guo, Xiaolong	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
H
Hamilton, Denzel	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain
Haroldsen, Travis	149: The Hardened Adversarial VET Challenge
Harper, Charles	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Harvey, Paige	167: MUD "IRL" - Implementing Manufacture Usage Description
Hasan, Md	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
He, Jiaji	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Henderson, Khir	167: MUD "IRL" - Implementing Manufacture Usage Description
Herkle, Andreas	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Hoque, Tamzidul	172: A CAD Framework for Machine Learning based Hardware IP Trust Verification
Hu, Yinghua	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
I
Iyer, Vishnuvardhan	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
J
Javaheripi, Mojan	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Jemal, Ahamed	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain
Jin, Yier	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection On the Impossibility of Approximation-Resilient Circuit Locking QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment 169: System level attacks on HaHa platform
K
Kar, Monodeep	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 159: Application Inference using ML based Side Channel Analysis
Kastner, Ryan	Property Driven Hardware Security
Khan, Mohammad Nasim Imtiaz	ENTT: A Family of Emerging NVM-based Trojan Triggers
Kolhe, Gaurav	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Kornegay, Kevin	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain 167: MUD "IRL" - Implementing Manufacture Usage Description
Koushanfar, Farinaz	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Krautter, Jonas	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
L
Labrado, Carson	147: Hardware Demo of a Piezoelectric Based PUF for Hardware Security in IoT Devices
Lee, Chiou-Yng	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
Li, Ge	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Lu, Hangwei	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Lukefahr, Andrew	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Lyu, Yongqiang	170: Software-controlled voltage differentials-based hardware fault attack
M
Mahmod, Jubayer	146: Remote Authentication of Low-Cost Devices using Unclonable IDs
Majumder, Md Badruddoja	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
Makris, Yiorgos	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Mandal, Soumyajit	164: Authentication of Consumables using Portable NQR Spectrometer
Mandry, Holger	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Maniatakos, Michail	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Masna, Naren Vikram Raj	164: Authentication of Consumables using Portable NQR Spectrometer
Mathew, Sanu	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Mathew, Sanu	Circuit Techniques for Energy-efficient Hardware Security
Menu, Alexandre	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Minwalla, Cyrus	163: PUF-based eCash
Mizanur Rahman, Nael	Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 159: Application Inference using ML based Side Channel Analysis
Mohammad, Mezanur	171: Demonstration of Exfilteration of Data through Smart Light Bulb (Internet of things)
Monson, Joshua	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation 149: The Hardened Adversarial VET Challenge
Moradi, Amir	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
Moëllic, Pierre-Alain	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Mukhopadhyay, Debdeep	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Mukhopadhyay, Saibal	Circuit Techniques for Energy-efficient Hardware Security Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 159: Application Inference using ML based Side Channel Analysis
Mukhopadhyay, Saibal	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Mulet, Miles	169: System level attacks on HaHa platform
N
Nabeel, Mohammed	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
Nagarajan, Karthikeyan	ENTT: A Family of Emerging NVM-based Trojan Triggers
Nahiyan, Adib	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Nath, Mayukh	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Nguyen, Luong	160: Hardware Trojan Detection Using Backscattering Side Channel
Nuzzo, Pierluigi	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
O
Oberg, Jason	Enabling a Secure Development Lifecycle for Hardware
Orshansky, Michael	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems ** Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Ortmanns, Maurits	In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
P
Park, Jungmin	143: RASC: Enabling Remote Access to Side-Channels
Patel, Chintan	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Piccolboni, Luca	152: Securing Accelerators with Dynamic Information Flow Tracking
Plusquellic, Jim	156: A SCA-resilient Design Based on Dynamic Reconfiguration 158: Boot and Runtime Bitstream Authentication for FPGAs Side Channel Attacks and Countermeasures 163: PUF-based eCash 162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Prvulovic, Milos	160: Hardware Trojan Detection Using Backscattering Side Channel
Q
Qiu, Pengfei	170: Software-controlled voltage differentials-based hardware fault attack
Qu, Gang	170: Software-controlled voltage differentials-based hardware fault attack
R
Rahman, Fahim	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Rajan, Anand	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator
Ramanidharan, Bharath	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Ramezanpour, Keyvan	A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Ray, Sandip	System-on-Chip Platform Security Assurance: Architecture, Implementation, Validation, and Deployment
Riazi, M. Sadegh	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Rigaud, Jean-Baptiste	Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Robucci, Ryan	162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Rose, Garrett	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
S
Santhana Krishnan, Archanaa	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Saqib, Fareena	156: A SCA-resilient Design Based on Dynamic Reconfiguration 158: Boot and Runtime Bitstream Authentication for FPGAs Side Channel Attacks and Countermeasures 163: PUF-based eCash 162: Side-channel Power Resistance for Encryption Algorithms using Dynamic Partial Reconﬁguration (SPREAD)
Schaumont, Patrick	SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
Schellenberg, Falk	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs
Schmidt, Andrew	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Scholz, Alexander	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Sechen, Carl	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Sen, Shreyas	STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis **
Sepulveda, Johanna	Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
Shamsi, Kaveh	On the Impossibility of Approximation-Resilient Circuit Locking
Shanta, Aysha	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
Shen, Haoting	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Sherer, Adam	Enabling a Secure Development Lifecycle for Hardware
Shi, Qihang	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Shihab, Mustafa	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Siddiqui, Ali Shuja	156: A SCA-resilient Design Based on Dynamic Reconfiguration 158: Boot and Runtime Bitstream Authentication for FPGAs
Sigl, Georg	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists Improving on State Register Identification in Sequential Hardware Reverse Engineering
Sikora, Axel	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Singh, Adit	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Singh, Arvind	145: A 128-bit AES Engine with Higher Resistance to Power & Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low Dropout Regulator Extracting side-channel leakage from round unrolled implementations of lightweight ciphers 159: Application Inference using ML based Side Channel Analysis
Sinha, Sayan	RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Skipper, Grant	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Smith, Edmund	168: Securing IoT Devices in Heterogenous Network Setting using Blockchain 167: MUD "IRL" - Implementing Manufacture Usage Description
Stern, Andrew	143: RASC: Enabling Remote Access to Side-Channels 142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Swany, Martin	142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Szefer, Jakub	154: RISC-V Secure Caches Demo on FPGA Secure Processor Architectures in the Era of Spectre and Meltdown
T
Tahoori, Mehdi	155: Software-based Fault and Power Side-Channel Attacks inside Multi-Tenant FPGAs 153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform
Tamore, Suyash Mohan	156: A SCA-resilient Design Based on Dynamic Reconfiguration
Taştan, Ibrahim	151: Experimental Cryptanalysis : Case study on chaotic random number generators
Tehranipoor, Bahar	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Tehranipoor, Mark	143: RASC: Enabling Remote Access to Side-Channels 142: Infrared Applications of FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection CAD for Security FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Tempelmeier, Michael	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Thapliyal, Himanshu	147: Hardware Demo of a Piezoelectric Based PUF for Hardware Security in IoT Devices
Tian, Jingxiang	161: Structural Obfuscation of Sensitive Designs through Selective Post-Fabrication Transistor-Level Programming
Tiwari, Mohit	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
Tsoutsos, Nektarios	CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
U
Uddin, Mesbah	166: Demonstration of a Chaos based Unclonable RISC V Processor with Logic Locking Scheme
Umar Hussain, Siam	MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
V
Valamehr, Jonathan	Enabling a Secure Development Lifecycle for Hardware
Vashistha, Nidish	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
Vemuri, Ranga	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
Venkataramani, Guru	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Venugopalan, Vivek	157: MIRAGE: A System-Level Framework for Inserting and Evaluating Logic Obfuscation
Vosatka, Jason	143: RASC: Enabling Remote Access to Side-Channels
W
Wang, Dongsheng	170: Software-controlled voltage differentials-based hardware fault attack
Wang, Wendong	Detecting Recycled SoCs by Exploiting Aging Induced Biases in SRAM Cells
Wei, Shijia	Using Power-Anomalies to Counter Evasive Micro-architectural Attacks in Embedded Systems **
Werner, Maximilian	Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists
Woodard, Damon	Golden Gates: A New hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging ##
X
Xie, Jiafeng	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over $GF(2^m)$ based on MSPB ##
Xiong, Wenjie	154: RISC-V Secure Caches Demo on FPGA Secure Processor Architectures in the Era of Spectre and Meltdown
Xu, Guorui	148: Portable Power Tracer for USIM with Smart Analyzer
Xu, Qian	170: Software-controlled voltage differentials-based hardware fault attack
Y
Yang, Bolin	148: Portable Power Tracer for USIM with Smart Analyzer
Yang, Chengmo	A Fetching Tale: Covert Communication With The Hardware Prefetcher
Yang, Kun	143: RASC: Enabling Remote Access to Side-Channels
Yang, Shuo	169: System level attacks on HaHa platform
Yao, Fan	COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
Yellu, Pruthvy	171: Demonstration of Exfilteration of Data through Smart Light Bulb (Internet of things)
Yimer, Tsion	167: MUD "IRL" - Implementing Manufacture Usage Description
Yu, Qiaoyan	165: Demonstration of Enhancing the Resilience against CPA Attacks for Three-Dimensional Chips with Power Distribution Network Noise
Z
Z. Pan, David	On the Impossibility of Approximation-Resilient Circuit Locking
Zajic, Alenka	160: Hardware Trojan Detection Using Backscattering Side Channel
Zhang, Fan	148: Portable Power Tracer for USIM with Smart Analyzer
Zhang, Yiran	148: Portable Power Tracer for USIM with Smart Analyzer
Zhang, Zhiming	165: Demonstration of Enhancing the Resilience against CPA Attacks for Three-Dimensional Chips with Power Distribution Network Noise
Zhao, Xinjie	148: Portable Power Tracer for USIM with Smart Analyzer
Zhao, Yiqiang	144: An On-Chip Electromagnetic Sensor Network for Analog Trojan Detection
Zimmermann, Lukas	153: Demonstration of Differential Circuit (DiffC)-PUF Addressing and Readout Platform