ABSTRACT. Tensor contractions are a core computational primitive in scientific computing, machine learning, and quantum simulation. Achieving high performance for these operations on modern hardware requires not only selecting efficient computation kernels but also carefully orchestrating tensor memory layouts to match hardware-friendly formats. However, existing approaches such as TTGT and GETT either incur high data movement costs or sacrifice peak compute utilization. We present a compiler-based framework for optimizing tensor contraction expressions by systematically managing data layout to maximize throughput. At its core is an intermediate representation (IR) that explicitly separates transposition from computation and explicitly encodes associated layout constraints, enabling a two-phase optimization strategy: first, full expansion of the IR to expose all layout transformation opportunities; second, selective permutation fusion based on profile-guided optimization(PGO) to balance memory movement and compute efficiency. The optimized IR is lowered to high-performance backends, using BLAS to leverage hardware-accelerated matrix operation where beneficial, and fused GETT for bandwidth-sensitive cases. Experimental results on 24 binary contraction benchmarks and 8 tensor network expressions demonstrate substantial runtime improvements over state-of-the-art libraries. These results highlight the critical role of layout orchestration in unlocking the full potential of modern hardware tensor computation.

ABSTRACT. Hardware-based power capping is essential for managing electrical consumption constraints and operational costs in data centers and High-Performance Computing. While the Intel Running Average Power Limit (RAPL) interface offers fine-grained control capabilities on modern servers, the interaction between its configuration parameters and the hardware's dynamic performance boost mechanisms remains complex and often misunderstood. This paper provides a comprehensive understanding of these mechanisms and their effects on power consumption and Quality of Service. First, we conduct a sensitivity analysis to characterize how each parameter influences the processor's throttling behavior. Based on the underlying exponential weighted moving average logic, we derive an analytical model to predict the effective duration of high-performance states. We validate this model through extensive experiments on four Intel Xeon microarchitectures. Furthermore, we quantify the impact of power capping on overall energy efficiency. Our experiments confirm that restricting power does not systematically lead to energy savings, highlighting a critical efficiency threshold below 50\% of the Thermal Design Power, where the increase in execution time severely outweighs the power reduction. This work provides system administrators and researchers with the necessary insights to effectively configure power constraints while avoiding performance pitfalls.

ABSTRACT. Wearable biomedical devices increasingly require on-device privacy guarantees through Zero-Knowledge Proofs (ZKPs), yet the underlying cryptographic kernels, based on modular exponentiation over prime fields, far exceed what low-power microcontrollers can deliver. Coarse-Grained Reconfigurable Arrays (CGRAs) offer near-ASIC efficiency with the reprogrammability needed to track evolving ZKP standards, but programming them requires manual, cycle-by-cycle scheduling across a spatial processing-element mesh. We present CASTM, a CGRA API & Spatial Temporal Mapper for the OpenEdgeCGRA architecture. CASTM preserves explicit spatial-temporal control while raising the abstraction level through structured abstractions and architecture-aware operators that encapsulate recurring modular-arithmetic idioms. For the S-box layer, a key component of the popular ZKP-friendly hash function Poseidon2, CASTM achieves 1.26× speedup w.r.t. the hand-optimized version while reducing source code by approximately 6.0×. We also identify that for long ZKP kernels multi-batch configuration reload is the dominant bottleneck, and show that increasing the Configuration Register File from 32 to 512 entries (+4.5% FPGA area) allow us to deploy the full Poseidon2 kernel on the CGRA achieving 1.33× speedup and 33.7% of energy savings over a ultra-low power RISC-V CPU core.

ABSTRACT. The symbiotic scaling of artificial intelligence models and high‑performance computing systems continually creates algorithmic challenges in their convergence. Foundation models (FMs) are a crucial example, requiring months‑long training on thousands of cutting‑edge GPUs. Sharded data parallelism (DP) is the dominant strategy to accelerate such computations by splitting data and models across multiple GPUs. However, it incurs prohibitive communication overhead when deployed at scale, particularly on multi-tier interconnects with heterogeneous performance. Inspired by the efficient communication principles of federated learning (FL), this work introduces two hybrid algorithms—FL+FSDP and FL+HSDP—interleaving sharded DP with FedAvg‑style aggregations. Such approaches decouple large DP deployments into smaller, loosely‑coupled federation groups, requiring minimal inter‑group traffic while keeping the global batch size bounded by the groups' size. Formal analysis of communication costs and experimental validation prove their scalability and flexibility. A Llama3.1 8B pre-training on 512 A100 GPUs shows that, under identical hyperparameters, FL+FSDP and FL+HSDP achieve up to 8.04x faster data processing and 4.48x lower evaluation perplexity than their counterparts, demonstrating superior computational efficiency and improved model quality. These properties stem from reduced communication overhead and the bounded growth of the global batch size relative to the federation group size.

ABSTRACT. The list ranking problem is one of the classical problems of parallel computing, with nontrivial algorithms and many applications as a subroutine for solving other problems.

While it has been intensively studied in the early days of parallel computing, few things happened in the last 20 years. In particular, there is little work on scaling list ranking to large machines and input sizes.

We reconsider list ranking starting from the ground-breaking results of Sibeyn a quarter century ago. We employ algorithm and performance engineering to improve his sparse ruling-set algorithm, making it capable of scaling to many processors, and provide a more detailed analysis of the impact of the algorithm's parameters, further guiding our practical implementation.

We perform an extensive experimental study across a variety of input instances with different structural properties. We demonstrate that indirect communication, exploiting input locality, and message coalescing allows scaling to billions of elements on up to 24 576 cores.

ABSTRACT. Multi-Agent Reinforcement Learning (MARL) enables multiple agents to learn coordinated behaviors through interaction with a shared environment, but its training process is computationally intensive and difficult to scale efficiently across heterogeneous hardware platforms. We present a hardware-agnostic MARL training protocol that accelerates MARL training on systems composed of diverse computing devices, including CPUs, GPUs, etc. Our protocol systematically coordinates training tasks across devices, manages workload partitioning, and ensures efficient synchronization to maximize hardware utilization across various MARL algorithm classes while preserving algorithm semantics. To adapt to performance variability across heterogeneous resources, we incorporate a Runtime Load Balancer that dynamically distributes training workload based on device execution characteristics during runtime. We evaluate our approach using representative MARL algorithms spanning decentralized and centralized training paradigms across multiple benchmarks and heterogeneous platforms. Our implementations achieve up to 10.37x speedup over state-of-the-art baselines. We open-source our work at https://anonymous.4open.science/r/Hetero-MARL/.

ABSTRACT. The SW26010Pro processor in the next-generation Sunway system introduces bigshare mode, in which a single process spans multiple Core Groups (CGs) and accesses an aggregated memory space larger than that of the conventional one-process-per-CG model. However, programs in bigshare mode often underperform. Our analysis suggests that a primary cause is asymmetric execution-image placement: the execution image is placed in memory associated with a single CG, concentrating accesses on one memory controller (MC), increasing instruction-fetch latency, and limiting effective bandwidth. To address this issue, we repurpose the cross-segment space—originally designed for sharing data across CGs—as an execution space for execution images. The space is system-defined and interleaved across all six CGs at a fixed 256 B granularity. We implement swcrun, a loader that enables this placement without modifying application source code. Compared with the default bigshare mode, swcrun achieves average speedups of 1.64× on the swRodinia benchmark suite and 1.83× on SWBWA. We further analyze its implications in multi-node communication.

ABSTRACT. Spiking neural networks (SNNs) are a promising paradigm for energy-efficient event-driven computation, but large-scale SNN execution remains challenging because sparse spike communication and synchronization can dominate runtime. Existing solutions across CPU, GPU, ASIC, and FPGA platforms offer different trade-offs between programmability, efficiency, and scalability. To address this gap, we present NeuroRing, a modular and scalable SNN accelerator based on a stream-dataflow architecture and a bidirectional ring topology, implemented in High-Level Synthesis (HLS) on programmable FPGAs. NeuroRing supports modular single- and multi-FPGA deployment and is compatible with existing SNN workflows through integration with the NEST simulator. We evaluate NeuroRing on the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. Results show that NeuroRing preserves the key activity statistics of the NEST reference model, achieves faster-than-real-time execution of the full-scale cortical microcircuit with a real-time factor (RTF) of 0.83, exhibits meaningful strong and weak scaling, and provides competitive energy efficiency on two programmable FPGAs. These results position NeuroRing as a flexible and scalable platform for both neuroscience simulation and broader event-driven applications.

ABSTRACT. The currently dominant AI/ML workloads, such as Large Language Models (LLMs), rely on the efficient execution of General Matrix-Matrix Multiplication (GEMM) operations. Thus, most systems are equipped with dedicated matrix hardware accelerators built on square Systolic Arrays (SAs) of Processing Elements (PEs). While this organization was effective for traditional Deep Neural Networks (DNNs), LLMs introduce input-dependent and highly skewed matrices, leading to underutilized SA resources. To address this challenge, we propose SISA (Scale-In Systolic Array), a novel SA architecture that partitions the traditional square array into horizontal rectangular slabs. With minimal overhead, SISA exposes parallelism through independently scheduled slabs for efficient execution of small or skewed matrix shapes, while retaining full-array operation for large GEMMs. SISA achieves up to 8.52× speedup and 93% energy-delay-product (EDP) reduction for representative LLMs compared to a state-of-the-art monolithic SA with the same number of PEs.

ABSTRACT. Vision Transformers (ViTs) achieve strong accuracy but incur high inference latency. Semi-structured N:M sparsity can reduce arithmetic cost, yet its theoretical savings often fail to translate into proportional end-to-end speedups on modern GPUs. This mismatch arises because deployment latency depends not only on arithmetic reduction but also on execution regularity and hardware scheduling under sparsity. Achieving practical acceleration, therefore, requires coordinated design across sparse execution and sparsity configuration. To this end, we propose a hardware-software co-design framework for N:M sparse ViT inference. On the hardware side, we design MD-SpMM, an N:M sparse CUDA kernel that reorganizes sparse GEMM into micro-dense, Tensor-Core-aligned dataflow and uses inference-aware adaptive parallelism to sustain utilization. On the software side, we perform layer-wise sparsity search under explicit end-to-end latency budgets using a three-stage heuristic search with constraint relaxation to avoid premature convergence and enable deployment-aware sparsity allocation. Experiments on multiple ViT/Swin models and GPU platforms show that the framework achieves over 2.2× latency speedup while maintaining comparable accuracy and delivering superior accuracy under the same latency constraint. The code will be publicly released.

ABSTRACT. Symmetric positive-definite system solvers based on Cholesky factorization are fundamental to many scientific applications, such as climate modeling. We present a portable, nested recursive mixed-precision solver designed for Matrix Processing Units (MXUs), including NVIDIA Tensor Cores (H200) and AMD Matrix Cores (MI300X), that assigns low-precision FP16 arithmetic to large off-diagonal blocks, while preserving high precision on diagonal blocks to ensure numerical stability. The solver is implemented in Julia, providing a high-level, hardware-agnostic interface. We demonstrate up to a 5.07× speedup relative to the diagonal-precision vendor baseline, with 100× better accuracy than pure half precision on H200, providing higher accuracy than low-precision at higher speed than high-precision. Positive performance trends are also observed on MI300X, demonstrating broad applicability across GPUs.

ABSTRACT. Power management methods such as power capping or dynamic frequency capping have long been considered as primary mechanisms to cope with the power constraints of exascale computing and beyond. However, GPU-accelerated HPC applications are inherently multi-kernel, with heterogeneous computational and memory behaviors across execution phases. As a result, improvements observed at the kernel level may not translate into better application-level performance. In this work, we investigate how device-level power capping and frequency capping affect the performance–energy behavior of GPU applications on the Frontier exascale supercomputer. We evaluate multiple power and frequency configurations across three representative applications (Cholla, Pennant, and HACC) to identify those that deliver the best performance–energy trade-offs. Using these configurations, we perform an intra-kernel analysis combining GPU hardware counters with runtime profiling to examine how power management policies influence kernel execution and distributed runtime behavior. Our results show that faster kernels do not necessarily lead to faster applications. For example, in Pennant running across 32 nodes, the dominant kernel executes up to 20% faster under power capping, yet these gains are partially offset by higher communication costs and load imbalance across MPI calls. Similarly, in Cholla, synchronization imbalance increases from 30.6% to 39.8% and communication imbalance from 5.8% to 16.6%, leading to longer MPI wait times despite faster kernel execution.

ABSTRACT. Sparse Matrix-Vector Multiplication (SpMV) is a key kernel in numerical linear algebra, and its performance depends strongly on the distribution of nonzero elements. When nonzeros are concentrated near a few diagonals, the matrix can be stored efficiently in DIA form. We present a band-specialized DIA-style SpMV kernel using High-Level Synthesis (HLS) for High Bandwidth Memory (HBM)-equipped FPGAs and compare it with AMD's Vitis SpMV kernel. On densely banded matrices, our design achieves geometric-mean gains from 9.5× to 1.2× in GFLOPS and from 9.5× to 1.5× in GFLOPS/W. On sparse-banded matrices derived from SuiteSparse, the advantage decreases as the band widens due to zero padding, but remains strong for narrow bands, reaching 9.5× at band size 8. Against a multithreaded OpenMP DIA baseline on a Xeon Silver 4208, the FPGA achieves up to 4.08× higher GFLOPS and up to 6.39× higher GFLOPS/W. Overall, the proposed throughput-oriented banded kernel consistently outperforms a general-purpose HLS SpMV design for small and moderate band sizes, with clear energy-efficiency gains.

ABSTRACT. Zero-knowledge proofs (ZKPs) have emerged as powerful privacy-preserving primitives with broad applications. However, the immense computational overhead of proof generation remains a critical obstacle. Existing hardware accelerators are tightly coupled to specific ZKP protocols, lacking the adaptability to support diverse protocols with varying computation kernels and arithmetic bit-widths. This paper presents OmniZK, a versatile accelerator architecture designed to efficiently support a broad spectrum of ZKP protocols. OmniZK employs homogeneous arrays of Unified Processing Elements (UPEs) interconnected via flexible mesh networks as its hardware substrate. It abstracts and maps heterogeneous ZKP computation kernels—including polynomial operations, multi-scalar multiplication, and Merkle tree construction—onto this unified finite-field arithmetic layer. Each UPE utilizes a hardware-efficient divide-and-conquer strategy to dynamically support arithmetic bit-widths ranging from 64 to 768 bits. Furthermore, OmniZK introduces optimized kernel mapping strategies that exploit multiple levels of parallelism to eliminate pipeline stalls, alongside a fast batched inversion method that substantially reduces vector inversion latency. Experimental results show that OmniZK achieves average speedups of $3.93\times$ and $1.69\times$ over the state-of-the-art elliptic-curve-based accelerator LegoZK and hash-based accelerator UniZK, respectively.

ABSTRACT. Hardware failures pose a significant threat to the successful execution of supercomputer applications. Two failure types are particularly important: hard errors that cause process aborts, and soft errors that silently corrupt calculation results. Task-based parallel programs can profit from tailored techniques for failure protection, which can be transparently applied in the runtime system and are often more efficient than general-purpose techniques. The talk surveys existing approaches with a focus on own contributions. These refer to task-level checkpointing and task-level replication as well as to different task models such as nested fork-join programs and dynamically spawned tasks that cooperate through the future construct.

ABSTRACT. Quantum computing promises computational capabilities that extend beyond the representational and computational limits of classical systems. It is widely regarded as a candidate technology for addressing scalability and tractability challenges in domains such as large‑scale molecular simulation, complex optimization, and AI. Yet, classical high‑performance computing (HPC) infrastructures remain foundational to the quantum computing ecosystem.

Modern HPC platforms—spanning massively parallel CPU and GPU clusters, accelerators, and high‑bandwidth interconnects—are indispensable for the full quantum workflow. They support tasks such as large‑scale quantum device calibration, quantum state preparation and control, sophisticated error mitigation and noise characterization, and compute‑intensive data pre‑ and post‑processing.

In this talk, we critically examine the role of classical HPC in conjunction with quantum systems. We discuss key lessons learned from the first generation of hybrid quantum–classical and HPC–quantum systems, and highlight current research directions. Particular attention is given to state‑of‑the‑art hybrid algorithms, including the Quantum Approximate Optimization Algorithm (QAOA) and Variational Quantum Algorithms (VQA), and to how they are orchestrated and scaled on HPC platforms. We conclude by exploring novel interaction paradigms—such as digital shadows and their practical implementations—which are designed to run in synergy with HPC backends.

ABSTRACT. Distributed information systems are evolving to support increasingly complex workloads, ranging from massive training of AI agents to real-time edge computations, across highly heterogeneous infrastructures. To address these challenging computing needs, new knowledge-based paradigms for resource management are emerging, in which automation moves beyond simple rule-based systems to incorporate autonomous decision-making and goal-oriented planning. These advancements are redefining resource orchestration strategies, marking a transition from reactive scaling to predictive and adaptive strategies. The talk aims to provide a forward-looking analysis on the necessity of moving beyond human-coded heuristics toward self-optimizing distributed environments that bridge the gap between technical infrastructure performance and user-centric objectives, ensuring that infrastructure performance remains dynamically synchronized with actual application demand.

ABSTRACT. Modern scientific applications increasingly execute across heterogeneous computing infrastructures combining HPC systems, cloud resources, accelerators, and emerging computing platforms such as quantum computers. While workflow technologies provide a powerful abstraction for managing complex applications, portability and interoperability across diverse execution environments remain significant challenges. This talk presents an intermediate representation for scientific workflows that decouples workflow specification from deployment and execution. By providing a common abstraction layer, it enables workflow portability across heterogeneous infrastructures while supporting different orchestration and scheduling strategies. The talk will show how workflow models can be transformed into distributed execution plans and illustrate how intermediate representations facilitate scalable, reproducible, and adaptable workflow execution.

ABSTRACT. Large Language Models are rapidly finding their way into software development workflows, but can they also help bridge the gap between different compiler ecosystems? In this talk, I will present our experiences building IRIS-14B, the first LLM designed to translate between compiler intermediate representations, specifically from GCC's GIMPLE to LLVM IR. Rather than focusing only on accuracy numbers, I will discuss the practical lessons learned while turning IR-to-IR translation into a real machine learning problem: constructing large-scale compiler datasets, choosing among multiple compiler representations, dealing with context-length limitations, handling evolving compiler versions, and developing evaluation methodologies capable of pinpointing translation failures. The talk will provide a behind-the-scenes view of the challenges and opportunities that arise when combining modern AI models with compiler technology. It will also explore how neural IR translation differs from traditional compiler engineering approaches and what it may mean for the future of compiler interoperability, program analysis, and neural compilation.

ABSTRACT. Time-Sensitive Networking (TSN) guarantees deterministic communication for cyber-physical systems. To ensure high availability under network faults, existing TSN fault tolerance solutions rely on static redundancy, leading to high hardware costs. Adaptive fault detection and recovery could address this limitation. However, existing TSN fault detection and recovery cannot adapt to different network faults due to the tightly coupled architecture, resulting in high costs, inflexible scaling, and prolonged downtime. To achieve adaptive TSN fault tolerance, this paper proposes a software-hardware decoupled framework called Adapt-TSN, which incorporates programmable fault detection and context-aware fault recovery. Programmable fault detection adapts to different network faults by utilizing software-defined policies to perform dynamic coarse-to-fine detection on lightweight hardware. Context-aware fault recovery adapts to different fault feedback by employing spatial-temporal scheduling based on runtime context. FPGA-based evaluation shows that Adapt-TSN cuts memory usage by 93.1% and logic usage by 75.6% versus static redundancy, while restoring deterministic transmission for each flow within 6.5ms under diverse faults and preserving µs-level delay and ns-level jitter.

ABSTRACT. Edge clusters increasingly serve interactive large language models (LLMs) under strict latency service-level objectives (SLOs), notably time-to-first-token (TTFT) and time-per-output-token (TPOT). Multi-turn conversations retain a growing key--value (KV) cache whose footprint inflates with session length, making GPU memory the dominant bottleneck and rendering late interventions prohibitively expensive. Existing compute-centric or threshold-based policies react only near saturation, often triggering burst-time tail spikes and unnecessary state movement. We present EdgeKV, an online control framework for multi-tenant edge LLM servicing that treats the KV cache as a first-class resource and performs closed-loop control over admission, edge--cloud routing, per-tenant KV quotas, and KV relocation/eviction. EdgeKV is driven by a Lyapunov drift-plus-penalty controller with per-tenant virtual debt queues for TTFT/TPOT, coupling accumulated SLO debt with KV pressure and state-movement costs. Evaluated in a trace-driven discrete-event simulator calibrated with GPU profiling on BurstGPT-derived conversational workloads, EdgeKV reduces TTFT P99 by up to 43% compared with reactive offloading and token-recompute baselines, highlighting the value of proactive, cost-aware KV-state management for SLO-compliant edge LLM servicing.

ABSTRACT. GPU checkpointing and restore promises to enable emerging tasks, such as deep learning, to benefit from functionalities like task scheduling and fault tolerance. However, existing GPU checkpointing/restore solutions suffer from updateruntime overhead, bloated checkpoint images, and correctness issues.

This paper presents FlowGPU, a system-level GPU checkpointing/restore mechanism that overcomes all aforementioned limitations. Our key insight is that the limitations of prior mechanisms implicitly stem from their architectural design, which tightly couples checkpointing/restore with a legacy virtualization technique: API forwarding. In response, the design of FlowGPU decouples checkpointing/restore from virtualization with two key techniques: per-task interception and ghost process, thereby overcoming these limitations. Furthermore, FlowGPU comes with a set of novel techniques to further improve performance and ensure correctness under complex scenarios, such as a task operating on multiple GPUs. Our evaluation shows that FlowGPU outperforms prior mechanisms by up to 4.5x.

ABSTRACT. Sparse Matrix-Vector Multiplication (SpMV) performance on modern GPUs is frequently bottlenecked by the inherent mismatch between sparse data irregularity and regular hardware parallelism. Existing libraries typically rely on rigid ``one-size-fits-all'' configurations, struggling to adapt to diverse sparsity patterns. Moreover, they often neglect preprocessing efficiency, leading to severe overheads that negate kernel-level optimizations. To address these limitations, we introduce AtSpMV, an adaptive framework driven by a dual-stage performance model. It combines offline hardware profiling with a low-overhead online phase. By integrating the offline hardware model with the specific features of the incoming matrix, AtSpMV dynamically determines optimal parameters such as tile shape and load distribution. Furthermore, it features a GPU-accelerated, load-balanced preprocessing workflow to drastically reduce matrix preparation time. Comprehensive evaluations on NVIDIA A100 and H100 GPUs across 2,798 matrices demonstrate that AtSpMV achieves average speedups of 1.28x to 5.45x (up to 585x) over state-of-the-art libraries, including cuSPARSE, CSR5, DASP, and amgT. In real-world PageRank applications, AtSpMV delivers up to a 4.18x end-to-end speedup.

ABSTRACT. Earthquake-cycle simulations with implicit time integration require solving a large sparse elliptic system at every time step, making repeated linear solves the dominant cost. We present a task-parallel hybridized finite-difference solver for multi-core CPUs, based on SBP-SAT discretizations and designed for this solve-dominant regime. Hybridization decomposes each solve into sparse local subproblems and a sparse global trace system; interior unknowns are eliminated by solving the subproblems and assembling the trace system. In standard high-order hybridized finite element methods (e.g., HDG), element-local systems are algebraically dense, so local solve costs grow rapidly with element size and polynomial order; in contrast, hybridized finite differences preserve sparse, stencil-structured local operators, making subproblem size a freely tunable parameter. We exploit this structure to build a dependency-aware task-parallel algorithm that overlaps local subproblem solves with global trace assembly, reduces bulk-synchronous barriers, and improves cache reuse. We further develop a Roofline-based performance model that selects the subproblem size minimizing end-to-end solve time by balancing local solve costs against the global trace solve.

On 64-core Sapphire Rapids and 104-core Ice Lake systems, our solver outperforms IC(0)-preconditioned CG by up to 4.7× and a sparse multifrontal QR direct solver by up to 12×. Against a baseline hybridized solver, the task-parallel algorithm achieves up to 9.1× speedup, and the model-guided subproblem sizing adds a further improvement of up to 31× over commonly used fixed sizes, reducing per-solve costs for earthquake-cycle simulations.

ABSTRACT. Weighted Back-Projection (WBP) is a classical and widely used reconstruction method in tomography and cryo-electron tomography (cryo-ET). Given a tilt series acquired at different angles, WBP forms a 3D volume by applying weighting and accumulating geometry-dependent back-projection contributions across all tilts, making it attractive for its simplicity and robustness. However, modern cryo-ET datasets continue to grow in tilt count, volume size, and resolution, and often incorporate costly three-dimensional CTF correction (3D-CTF correction). As a result, WBP increasingly dominates end-to-end runtime, while conventional CPU pipelines suffer from insufficient throughput and limited scalability.

We propose GWBP, a highly optimized GPU implementation of the WBP parallel algorithm. First, GWBP performs kernelization of per-tilt operators and maintains persistent residency of intermediate data on the GPU. This design bypasses redundant correction steps on the host and minimizes host-device communication. Next, to enhance computational efficiency, we propose fragmentation-aware task batching and temporal buffer reuse. This synergistic approach effectively minimizes memory access. Finally, a stream-oriented scheduling scheme is introduced to overlap communication with computation, thereby eliminating pipeline bubbles and enhancing overall throughput.

Compared to the state-of-the-art multi-core CPU implementation, GWBP reduces end-to-end runtime from 3.131 s to 0.655 s, achieving up to a 4.78× speedup.

ABSTRACT. Space data centers built from Low-Earth Orbit (LEO) satellite constellations are gaining increasing attention as a scalable computing infrastructure. With access to abundant solar energy and high-throughput optical inter-satellite links, such constellations can run AI workloads directly in orbit, enabling new in-space application types while optimizing existing ones such as Earth observation. However, managing satellite constellations that combine heterogeneous satellite roles introduces a cost optimization challenge. Determining the appropriate constellation size and satellite role ratio for a given workload is challenging, as over-provisioning processing satellites increases system cost, while under-provisioning limits system efficiency. To enable cost-efficient execution of AI inference workloads in such space data centers, we present Constella, a novel framework that leverages DNN splitting for distributed AI inference in LEO satellite constellations. Constella comprises an offline resource identifier that determines the optimal ratio of processor-to-communicator satellites and an online assignment algorithm. The algorithm utilizes constellation telemetry to adaptively route data within the constellation and to ground stations. We evaluate Constella on a real-world satellite dataset across scenarios of increasing complexity. Results demonstrate a reduction in system cost by up to two orders of magnitude and lower end-to-end inference latency by up to 2.7x compared to other approaches, while maintaining no less than 81.9% inference success rate.

ABSTRACT. Advancements in large language models (LLMs), including base model improvements, various chain-of-thought approaches, and agentic tool use, have substantially increased their capacity for autonomous programming and software engineering. Their performance on such tasks is widely studied, tracked, and publicized; however, the majority of evaluations are based on Python, Java, or other high-level languages, with application domains in the web, business logic, or data analysis.

From the perspective of parallel language, programming interface (API), and systems research in the field of high-performance computing (HPC), the question arises whether these results translate to the capability of effectively parallelizing applications. In order to answer this question, we design and carry out a comprehensive study, tasking 8 state-of-the-art LLM agents with the parallelization of 11 small-to-medium-sized HPC benchmark applications. For each, we evaluate shared-memory, distributed memory, accelerator, and hybrid parallelization goals with appropriate APIs, and multiple agent invocations are performed for every data point to quantify random variance in outcome quality.

Our experimental setup includes validation in several steps, comprising semantic inspection, compilation, monitored execution, internal result checking, and external verification via known-good comparisons. For all valid programs, we also perform comparative performance benchmarking on a production supercomputer. We synthesize overall conclusions and quantify to what extent parallelization performance of LLMs correlates with time and tokens spent. All benchmark code, experiment and evaluation scripts, and generated data are fully available for analysis, replication and extension.

ABSTRACT. Communication overhead remains a major bottleneck in distributed training of large multimodal models. Existing gradient sparsification methods typically over-look both the structural heterogeneity across modalities and the stage-dependent dynamics of training, leading to inefficient communication performance trade-offs. In this paper, we propose CCGS, a cross-modal collaborative gradient spar-sification approach for efficient distributed multimodal training. CCGS explicitly models modality and layer-level structural heterogeneity via a computational-graph-based representation, and adaptively adjusts gradient sparsity across differ-ent training stages, enabling effective preservation of critical gradients while re-ducing redundant communication. Experiments on COCO, Flickr30k, and AIC-ICC demonstrate that CCGS significantly accelerates distributed training while maintaining comparable Top-1 and Top-5 accuracy, achieving up to 70.8% speedup over the uncompressed baseline and consistently outperforms state-of-the-art gradient compression methods like DGC, DFS, and JointSQ in terms of time-to-accuracy.

ABSTRACT. Data centers are the fastest-growing source of new electricity demand, driven above all by AI, and the grids that supply them can no longer treat that demand as fixed. This talk argues that sustainable supercomputing must be pursued on two fronts: design and demand. The design front builds efficient, sustainable loads. At the hardware-software co-design level, the Swiss-French SEAMS project (Sustainable and Energy Aware Methods for SKA) will be showcased for its domain-specific and reconfigurable accelerators for the SKA telescopes. At the data-center level, the CEO-DC framework will be presented, modeling when upgrades, modular servers, and carbon incentives actually cut operational and embodied emissions for AI and HPC workloads. The demand front operates those loads as flexible assets. As renewables grow, grids need large consumers that can adjust their power within sub-second windows to help keep frequency stable, a service called fast frequency response (FFR). GridPilot will be presented as a proof of concept and roadmap for giving GPU clusters this capability, with measured response well inside the strictest published European FFR budget. But fast response only helps with enough flexible load to commit. That margin comes from f-SLA, a flexible Service-Level Agreement: a user-side contract in which the user declares how long a job can wait, from run-now to a one-week deferral, and earns service credits, turning hidden flexibility into a declared resource and increasing the carbon-free energy a cluster can reach. These methods and tools will be illustrated throughout the talk on two case studies, SKA telescope imaging and AI, showing together how to make megawatts flexible and turn data centers from passive consumers into grid-responsive, carbon-aware citizens.

ABSTRACT. Efficiency, aiming to reduce the energy or resource cost per unit, is the main sustainability strategy considered in resource management. Despite decades of research, the global impacts of ICT are still growing. Faced with such limitations, this talk tries to go beyond efficiency and rather explores sufficiency strategies. My approach relies on feedback, i.e. dynamical adaptation based on measured system states. Objectives are formulated either as chosen constraints (I/O limits, graceful application degradation, platform consolidation) or imposed ones (grid power availability, heat production). I will provide examples of various architectures (HPC and Cloud) using learning and control theory tools. Exploring such runtime tradeoffs allows setting hard limits on the usage of resources, a path towards sufficiency in computing platforms.

ABSTRACT. The open Instruction Set Architecture (ISA) RISC-V is attracting growing interest within the High Performance Computing (HPC) community as a potential alternative to established architectures such as x86 and ARM. Its open and extensible design offers unique opportunities for architectural innovation, customization, and long-term technological independence. However, beyond the attractiveness of the ISA itself, a critical question remains: are current RISC-V hardware implementations and the associated HPC software ecosystem sufficiently mature to support demanding scientific workloads at scale? This presentation provides an overview of the current state of RISC-V in HPC. We discuss the capabilities of available hardware platforms and evaluate the readiness of the software stack, including compilers, libraries, and programming environments. Through a series of case studies involving real-world scientific applications, we investigate achieved performance, scalability, and energy efficiency on contemporary RISC-V systems. The analysis highlights the opportunities offered by the open RISC-V ecosystem, while also identifying current limitations and remaining challenges. The presented results provide practical insights for researchers, developers, and HPC centers interested in evaluating or adopting RISC-V for scientific computing workloads.