ABSTRACT. Sparse Matrix–Matrix Multiplication (SpMM) is a key op- eration in scientific computing, machine learning, and graph-based ap- plications. Modern CPUs incorporate specialized matrix units such as Intel Advanced Matrix Extensions (AMX), which deliver high through- put for dense matrices; however, irregular sparsity patterns and highly imbalanced row lengths significantly limit AMX utilization, and exist- ing AMX-based SpMM optimizations remain preliminary. We propose SparX, a cache-aware, high-performance SpMM implementation tai- lored for AMX. SparX introduces an architecture-aligned tile-block rep- resentation and a static tile-level execution model that eliminates fine- grained indexing and runtime decoding overhead, along with a dense matrix B reuse-aware prefetcher that dynamically refreshes frequently accessed dense blocks to improve cache efficiency. Experimental results on over 600 SuiteSparse matrices demonstrate that SparX achieves ge- ometric mean speedups of 6.1× over AMX-enabled oneDNN and 2.9× over AVX-512-enabled Intel MKL, while improving the L1 cache hit rate for dense matrix B by an average of 7.7%. The source code is available at https://github.com/amx-sparse/SparX.

ABSTRACT. Non-volatile main memory (NVMM) has enabled the design of fast fault-tolerant applications. The paper presents two algorithms for saving the state of Cloud applications in remote NVMM-equipped persistent servers. To be suited for a disaggregated approach, where a persistent server has little computing resources, the algorithms are based on RDMA operations for data transfers. The two algorithms allow high-frequency checkpoints in remote NVMM and provide different advantages. DisPM-DC is an eager algorithm that consumes no computing resources on the remote server, and works well when checkpoints are very frequent. DisPM-RL relies on redo logging to optimize data transfer, and achieves better performance when a larger portion of the application state is modified between two checkpoints. Experiments run with memory-intensive cloud applications, show that the overhead of our algorithms can be as low as 6% while checkpointing the application state several times per second.

ABSTRACT. Delta Debugging (DD) is a widely used technique for isolating minimal failure-inducing subsets within a given search space. While classical DD algorithms efficiently identify a single minimal cause, several applications — notably the analysis of floating-point instabilities in scientific computing — require a full enumeration of disjoint minimal failure-inducing subsets. In such contexts, DD relies on repeatedly evaluating a test function, which in practice may correspond to executing a full and potentially costly simulation code. Consequently, the total number of evaluations becomes the main performance bottleneck.

Under reasonable structural assumptions on the test function — consistent with empirical observations in many applications — we design a reduction algorithm capable of finding a full enumeration of disjoint minimal failure-inducing subsets while provably reducing the number of required evaluations compared to existing approaches. Crucially, the proposed formulation removes the intrinsic sequential dependency of classical DD algorithms, thereby eliminating the constraint that traditionally forces sequential exploration and enabling effective parallel execution without redundant computations.

We establish correctness and termination and derive explicit upper bounds on both sequential and parallel complexity. These bounds demonstrate a strict theoretical improvement over existing DD-based enumeration strategies, making the proposed approach particularly well suited for costly simulation-based analyses.

ABSTRACT. Statistical static timing analysis (SSTA) is a critical component of modern Electronic Design Automation (EDA) flows for modeling on-chip process variations. Among various SSTA methods, first-order block-based SSTA (FB-SSTA) supports efficient level-by-level timing propagation with high data parallelism, making it particularly suitable for GPU acceleration. However, existing GPU-based FB-SSTA solutions assume that the entire timing graph and data fit in GPU memory, an assumption that breaks down as circuit size increases. To overcome this challenge, we propose G-STAR, a GPU-accelerated FB-SSTA algorithm designed for memory-constrained FB-SSTA workloads. G-STAR enables efficient levelized FB-SSTA via level-by-level replication, combined with a replicated-pin scheduler that reuses GPU memory and avoids redundant phase propagation. Compared to a state-of-the-art GPU solution, G-STAR achieves up to 9.24× speedup on large designs and successfully completes FB-SSTA on multi-million-pin circuits where the baseline fails due to GPU out-of-memory errors.

ABSTRACT. Python-based array computation frameworks such as JAX are now considered viable alternative GPU programming approaches alongside established C++ portability frameworks. This work presents a comparative study of two single-GPU implementations of a three-dimensional second-order magnetohydrodynamics (MHD) solver with MUSCL–Hancock reconstruction: one developed in C++/Kokkos and one using JAX. The C++ implementation serves as a pre-existing, highly optimized reference code and provides a performance baseline for comparison with the JAX version. Both implementations are evaluated on multiple GPU architectures, including NVIDIA V100, A100, and H100, as well as AMD MI250 and MI300. The analysis focuses on two main key performance indicators: compute throughput and peak memory usage, complemented by performance observations on JAX’s just-in-time compilation behavior. The impact of JAX-specific optimization techniques—such as array concatenation and compiler fusion effects—is examined with respect to these metrics. The results highlight differences in JAX performance across hardware architectures and variations in memory requirements. Overall, JAX demonstrates competitive computational performance for kernels on structured data while offering a simpler implementation workflow compared to traditional C++ approaches. This study provides a quantitative basis for understanding trade-offs between programming models when targeting modern GPU platforms for scientific HPC workloads.

ABSTRACT. The Monte Carlo Method (MCM) is an invaluable tool for modeling and analyzing complex systems across multiple domains. For most applications, the MCM is massively parallelizable since the domain can be decomposed independently. However, as processing capacities continue to rise, this paper demonstrates that the common parallelization approach can exhibit a poorer than expected scalability, yielding diminishing efficiency gains as more processors are used. We propose an alternative approach based on task-based parallelism and the concepts of autonomic computing to address the root causes: load imbalance, synchronization, performance heterogeneity, and resource sharing. Our proposal leverages fine-grained tasks, dynamic scheduling, and the hierarchical management of the EasyGrid AMS middleware to achieve better scalability, sustaining efficiencies of more than 90% in both dedicated and heterogeneous computing scenarios when running an MCM simulation of thermal dispersion in porous media on an on-premises cluster. Additional evaluations on AWS EC2 cloud infrastructure further validate the scalability of our proposal.

ABSTRACT. This work presents a characterization study which demonstrates that, despite the potential for GPU-CPU cooperative execution of generative inference, existing offloading-based systems exhibit low performance due to frequent GPU-CPU communications and the lack of optimizations for hardware extensions for machine learning and heterogeneous memory. Guided by the characterization results, this work proposes Harmonia, a system for QoS-aware and high-throughput generative inference through locality- and heterogeneity-aware tensor placement and efficient cooperative execution. Our quantitative evaluation demonstrates that Harmonia provides QoS guarantees and delivers high performance across various models, QoS targets, and sequence lengths.

ABSTRACT. Open-source ecosystems have made state-of-the-art transformer models widely accessible, accelerating innovation and reproducibility. As these models scale for better performance, their memory demands frequently exceed single-device limits, making model partitioning crucial for distributed training. However, existing approaches make partitioning decisions at a fixed-granularity, limiting partition units to hand-crafted schemes or the model’s high-level architecture. This often requires additional engineering effort to adapt models for partitioning and substantially restricts the partition space. In practice, these constraints prevent effective workload balancing across devices, which in turn limits training scalability. This paper presents DAG-P, a fine-grained partitioning mechanism that automatically derives adaptive-granularity partitions of open-source transformer models. DAG-P optimizes model partitioning by leveraging heuristic rules guided by data-flow dependencies to group operators into partition units. Each partition unit is then encoded in a Partition Intermediate Representation (PIR), which serves as a basic element of the partition plan. This design enables a more expressive partition space that subsumes prior fixed-granularity approaches. While this generality increases search complexity, DAG-P employs greedy search to explore the expanded space and identify a plan with low cross-partition dependencies to limit cross-partition interactions and keep planning time practical. Experimental results show that DAG-P achieves up to 1.51× and 1.81× higher throughput compared to representative baselines, while incurring only seconds-level planning overhead.

ABSTRACT. As large language model inference environments expand toward consumer devices, it remains challenging to efficiently run models that exceed GPU memory capacity in single-GPU settings. The latency of transferring weights that do not fit in GPU memory accounts for about 98% of inference time and remains a major obstacle. In this paper, we focus on the fact that during the decode phase, layer computation time on the CPU can be shorter than weight transfer time, presenting an opportunity to hide weight transfers by utilizing this computation time. Therefore, we propose a method to hide transfer latency by executing certain layers on the CPU during the decode phase while asynchronously transferring the next layer's weights to the GPU in the background of that computation. To realize this scheduling, we formulate the placement of CPU/GPU computation and weight transfers as a latency minimization problem and perform optimization using an approximation model with relaxed temporal constraints. Evaluation results confirm that in a consumer desktop environment, our approach accelerates OPT-30B inference by 3.6 times compared to Hugging Face Accelerate and 6.5 times compared to DeepSpeed Zero-Inference.

ABSTRACT. Speculative decoding is a widely used technique for accelerating the inference step of large language models (LLMs) by generating draft tokens with smaller models and verifying them with a larger target model. While multi-level speculative decoding frameworks have been proposed, the optimal choice of parameters to maximize throughput remains poorly understood.

We present a probabilistic analysis of the multi-level speculative decoding and derive expressions to compute the optimal draft lengths via dynamic programming. We also introduce a novel adaptive drafting technique based on token confidence, and show how to compute optimal thresholds using discretized integrals to estimate the expected throughput for two-model generations.

We also provide simulations of multi-level decoding through empirical measurements of open-source LLMs, which confirm that we can derive near-optimal parameters for token generation, and that the new adaptive drafting schemes allow for increased throughput.

ABSTRACT. Real-world edge devices differ widely in memory and connectivity, so they cannot all split a shared model at the same layer. Allowing heterogeneous split depths, however, produces conflicting gradient signals that destabilize training. SuperSFL addresses this challenge with a single weight-sharing supernetwork whose prefix each client executes up to a depth matching its resources. To stabilize optimization across these mismatched splits, we introduce Three-Phase Gradient Fusion (TPGF). TPGF merges client- and server-side gradients using loss- and depth-aware weights that follow from a bias–variance analysis of the two supervision sources. A lightweight local classifier further enables clients to continue training locally during server outages and seamlessly reintegrate their updates when connectivity returns. Experiments on CIFAR-10 and CIFAR-100 show that SuperSFL converges up to 4.4× faster while reducing communication and energy consumption by up to 4× and 4.6×, respectively, compared with prior split and heterogeneous FL methods.

ABSTRACT. Accurate prediction of basic block throughput is essential for compiler optimization and microarchitectural performance analysis. However, existing data-driven approaches rely on large labeled datasets that are costly to collect and often fail on rare yet performance-critical instruction patterns. This paper presents Bada, an adaptive data augmentation with Bayesian optimization for basic block throughput prediction. Bada first constructs a feature representation to quantify the characteristics of basic block patterns, then applies Bayesian optimization to efficiently locate informative vectors, and finally employs a constraint-aware generator to map the selected vectors into executable basic blocks. We evaluate Bada on three representative RISC-V microarchitectures with two deep learning models. Experimental results show that Bada achieves 13.5%–23.1% relative reduction in MAPE under the same data scale. Remarkably, it reaches comparable or better MAPE using only one-fourth of the original data while preserving high cross-architecture generalization.

ABSTRACT. Efficient VM management in cloud environments remains challenging due to dynamically varying CPU requirements and diverse VM lifetimes. Existing approaches typically forecast average utilization, but overlook peak demands and remaining lifespans, causing unnecessary migrations and service-level objective (SLO) violations. We introduce PeakLife, an end-to-end management framework featuring a lightweight, multi-task deep surrogate model that jointly forecasts average CPU, peak CPU, and remaining VM lifetimes. PeakLife translates these predictions into proactive scheduling via (i) burstiness-aware, adaptive, utilization threshold tuning, and (ii) a lifetime-aware migration heuristic. Evaluated on public cloud traces, PeakLife reduces migrations by up to 29.25% and SLO violations by 25.91% over standard baselines. Ultimately, PeakLife closely matches the performance of an Oracle strategy that assumes perfect future knowledge of workload characteristics, offering an effective solution for adaptive cloud resource management.

ABSTRACT. Achieving peak GPU performance remains a significant challenge as the system throughput is constrained by host-device synchronization delays and kernel scheduling overheads, even with aggressive kernel optimizations and batch processing. Furthermore, existing approaches often underutilize hardware resources such as compute cores and copy engines due to scheduling overheads. To address these problems, we propose a CUDA runtime framework for task-parallel pipelines to minimize the synchronization overheads and the gap between kernel executions. The proposed solution combines two innovations: (1) a multi-stream task-parallel pipeline programming model that leverages event-chaining and work-stealing mechanisms to fully utilize available hardware resources; (2) a graph-based execution flow with per-stream buffers to ensure memory safety for multiple in-flight jobs running concurrently. Extensive evaluations on representative real-world workloads show 1.15--1.44x speedup and reduce scheduling overheads by 18--54% compared to state-of-the-art CUDA graph baselines.

ABSTRACT. The rise of large language models (LLMs) has led to intense communication contention in multi-job GPU training clusters. Existing communication schedulers typically adopt a resource-centric perspective, prioritizing flows based on static metrics, such as GPU intensity. However, this approach ignores a fundamental complexity: the inextricable entanglement of intra-job execution dependency and inter-job network contention.

In this paper, we present Moirai, a communication scheduler adopting the paradigm of dependency-impact-based scheduling. Moirai explicitly models the entanglement and is built on two core innovations to address the system's circular causality and vast search space: (1) a Dependency Resolution Engine that uses an analytical fixed-point iteration model to decouple the entangled dependency loops and precisely quantify the global impact of each flow; and (2) an Impact-Guided Strategy Explorer that navigates the exploded strategy space using heuristic optimization signals to identify flow-level strategies. Evaluations in a high-fidelity, ns-3-based simulator show that Moirai improves average JCT by 1.38×--1.52× and boosts GPU utilization by 13.8%–22.2%, consistently outperforming state-of-the-art schedulers like CASSINI and Crux.

ABSTRACT. Despite its ability to compute directly on encrypted data, Fully Homomorphic Encryption (FHE) is severely hindered by computational overhead. Leveraging multi-node hardware accelerators with fine-grained parallelism can \red{alleviate this bottleneck}, but introduces significant communication overhead. In this paper, we propose Thunder, an efficient multi-node FHE acceleration framework that reduces communication overhead through in-transit computation, thereby improving FHE performance. At the algorithm level, we propose a streaming Base Conversion (BConv) algorithm. It eliminates \red{global data dependencies} in \red{BConv computation}, thereby hiding communication latency. At the architecture level, we migrate BConv computation units from the compute nodes to the fabric, \red{the communication hub of the multi-node hardware accelerators}. This migration \red{eliminates global data synchronization} and \blue{reduces inter-node data traffic.} Together, the algorithm-architecture co-optimization reduces communication overhead by up to 92.7\%. Thunder is implemented on both FPGA and ASIC platforms. Compared to single-node FPGA accelerators, FPGA-based Thunder achieves up to 10.05× speedup; against state-of-the-art multi-node accelerators, Thunder delivers 2.09× (FPGA) and 1.33×–2.92× (ASIC) performance improvements.

ABSTRACT. With the continued decline in sequencing costs, genomics-based precision medicine is gaining increasing importance. The Genome Analysis Toolkit (GATK) is the standard framework for converting raw genomic data into actionable variants, but one of its most expensive steps is base quality score recalibration (BQSR), which corrects systematic sequencing errors. Despite significant work on accelerating other parts of the variant calling pipeline, BQSR has not been systematically explored on GPUs. In this work, we analyze BQSR to identify computational and I/O bottlenecks and show that simply offloading key stages to an accelerator is insufficient to achieve overall gains. We then present X-BQSR, a holistic redesign of the entire BQSR pipeline, including I/O, compression, and kernel execution, to better leverage GPU parallelism. We implement X-BQSR using portable SYCL kernels for NVIDIA, AMD, and Intel GPUs, along with native CUDA and HIP backends for comparison, and we evaluate its performance against previous FPGA work. Our evaluation shows up to 141.7× acceleration compared to standard GATK and 8.7× acceleration compared to a proprietary GPU-accelerated solution.

ABSTRACT. The rapid growth of AI has significantly increased data center energy demand, placing increasing pressure on power grids. In collaborative data center demand response (DR), multiple data centers share information with an external coordinator for optimal power dispatch and improved quality of service for their workloads. However, disclosing sensitive information such as power usage and workload performance to an untrusted third party raises significant privacy concerns. To address this, we replace the untrusted coordinator with a Multi-Party Computation (MPC)-based system that performs secure power dispatch without revealing sensitive inputs. To meet real-time DR latency requirements, we optimize our system by tailoring fixed-point bitwidths and substituting expensive secure divisions with polynomial approximations and Newton-Raphson iterations. Evaluated using the MP-SPDZ library, our optimizations yield up to 36x fewer communication rounds and a 46x speedup, delivering sub-second latency for up to 16 data centers while matching the power dispatch accuracy of the plaintext baseline.

ABSTRACT. Accurately computing dynamic correlation energy (DCE) is critical for characterizing strongly correlated systems in quantum chemistry simulations. However, DCE calculations involve massive tensor contractions that incur prohibitive computational costs and form the dominant bottleneck. Although modern heterogeneous architectures provide high-throughput low-precision tensor units, DCE workloads struggle to benefit from these hardware gains due to strict precision requirements, irregular computation patterns, and limited scalability. In this work, we propose TAIN, a novel tensor-aware solver for efficient DCE computation. TAIN leverages 1) an orbital-aware tensor compression algorithm to identify and approximate over 80% of non-critical tensor contractions while preserving chemical accuracy. 2) a heterogeneity-aware scheduling strategy to retain communication-bound contractions on CPUs and batch other tensor contractions on GPUs. 3) pipelined execution and a decoupled task–load partitioning strategy to reduce redundant work and achieve efficient load balancing. Experiments show that TAIN achieves up to 36.7x speedup over the state-of-the-art library on a single node. TAIN reaches 97% strong and 93% weak scaling on 4,000 nodes, reducing the time-to-solution for the bioluminescence system from days to a single hour.

ABSTRACT. Qubit mapping is a crucial step in quantum compilation for noisy intermediate-scale quantum (NISQ) hardware, where abstract quantum circuits must be adapted to physically constrained devices. We present a massively parallel branch-and-bound algorithm for the exact resolution of qubit mapping—formulated as an NP-hard combinatorial optimization problem—designed to address the inherent exponential complexity of this task. Our approach leverages both intra-node and inter-node parallelism, combining asynchronous exploration of independent subproblems with a dynamic and hierarchical work stealing mechanism across thousands of concurrent processes. Extensive experiments on a modern supercomputer demonstrate near-linear strong scaling at the intra-node level, and substantial strong scaling across compute nodes in distributed settings. Leveraging these capabilities, together with an appropriate bounding operator and guiding heuristics, we achieve state-of-the-art performance and compute reference optimal solutions for benchmark circuits of sizes exceeding previously solved instances. These results establish efficient large-scale parallelization as a practical enabler for exact qubit mapping, while paving the way for future extensions to GPU-accelerated HPC platforms.

ABSTRACT. Current quantum processors are too limited to solve large combinatorial optimization problems directly, motivating hybrid executions that combine quantum processors with classical HPC resources. This paper presents QSplit, a workflow-oriented hybrid quantum-classical framework for distributed optimization. QSplit targets problems expressed in the Quadratic Unconstrained Binary Optimization form, decomposes large instances into smaller sub-instances, dispatches them to heterogeneous classical or quantum backends, and reconstructs a global solution within a portable and reproducible workflow. The orchestration layer of the QSplit workflow is managed by StreamFlow WMS, enabling configurable execution across cloud, HPC, and remote quantum infrastructures. We evaluate QSplit on Knapsack and Max-Cut instances to study how problem structure affects decomposition quality. Results show that QSplit achieves competitive behavior on sparse instances, where decomposition preserves enough structure for effective aggregation, while dense instances expose the limits of purely structural splitting due to the loss of global correlations. These findings suggest that QSplit provides a framework for studying hybrid HPC-quantum optimization pipelines and their current scalability boundaries.

ABSTRACT. AlphaFold2 has achieved remarkable accuracy in protein structure prediction, yet its high computational and memory costs remain a significant barrier to large-scale deployment. While prior optimization efforts have been predominantly GPU-centric, the potential for CPU acceleration remains largely unexplored. This paper introduces MatrixFold, the first systematic study of quantized AlphaFold2 inference on a many-core CPU architecture. Targeting 72F processor with dedicated matrix units and on-package memory, we implement a series of computation and communication optimizations. These include highly optimized GEMM kernels, hardware-based communication mechanisms, and adaptive parallelism strategies to efficiently leverage the many-core resources. On CASP14 benchmarks, MatrixFold demonstrates high structural accuracy with TM-scores above 0.7. While its performance is comparable to GPU-based FastFold on short sequences, it shows a significant advantage on long sequences, achieving inference speedups of 1.3x to 3.4x over FastFold on the NVIDIA A800 GPU and 1.5x to 5.5x over Open-Omics-AlphaFold on Intel Xeon w9-3495X.

ABSTRACT. Inspired by the design of client caching in Content Delivery Networks (CDNs), PTStore distributes and replicates popular tensors that form reusable KV cache prefixes, which are the main technique used by state of art approaches to accelerate inferences. This reduces the latency of accessing the KV cache and alleviates load imbalance caused by a disproportionately large number of requests on servers containing popular tensors. Furthermore, thanks to decentralization, PTStore allows the expansion of the size of the KV cache for LLM inference by orders of magnitude. As a result, PTStore can execute inferences on long passage Q&A datasets 5-6 times more efficiently than current baselines, which do not aggregate memory across different nodes and GPUs and therefore require regenerating the KV cache.

ABSTRACT. Increasing adoption of large language models (LLMs) is leading to growing demand for inference. Although GPUs dominate LLM inference, their cost-effectiveness is questioned by their high acquisition and operational cost, and they show low utilization in the decode stage. Alternative AI accelerators such as Tenstorrent have recently emerged, yet their performance characteristics remain largely unexplored. This paper presents a systematic performance characterization of LLM inference on the Tenstorrent Wormhole accelerator. Using multiple LLMs, we analyze the performance of the decode stage according to batch sizes, KV cache sizes and processor count, and identify key bottlenecks. Our experiments reveal that the existing tensor parallelism incurs significant overheads in inter-device communication and does not scale well in multi-processor settings. To overcome this limitation, this paper proposes Chip-Pipe, a chip-level pipeline parallelization scheme that partitions the decode stage across Tensix processors in a load-balanced manner, reducing the communication overhead. Our evaluation with four LLMs demonstrates that the Chip-Pipe improves throughput by 1.64×–2.06× over tensor parallelism, achieving up to 2,689 tokens/s for Llama 3.1 8B.