ABSTRACT. Parallel programming is essential yet error-prone, motivating the use of languages such as Rust that promise memory safety and data-race freedom by construction. However, the 'unsafe' keyword, whose presence is amplified through transitive dependencies, leads to the majority of Rust programs not being provably safe in practice. This is also the case in widely reused parallel frameworks, raising the question of whether fully safe parallelism can be achieved, and if so, at what cost? To explore this, we present Velvet, a divide-and-conquer parallel programming model implemented entirely in safe Rust. Velvet adopts a Cilk-style spawn–sync abstraction with work-stealing scheduling, and integrates with the standard Rust toolchain without compiler modifications, preserving Rust’s language-enforced safety guarantees. An evaluation with representative benchmarks shows that Velvet incurs minimal overhead despite its fully safe design. Furthermore, it achieves competitive performance and scalability with state-of-the-art Rust and C frameworks, namely Rayon, Cilk and OpenMP, on up to 128 cores. Based on our experience, we discuss the interplay between Rust’s safety and performance, highlighting when both can be achieved simultaneously and where trade-offs emerge.

ABSTRACT. SmartNIC Data Processing Units (DPUs) offer a promising solution for saving high-end CPU resources by offloading tasks to programmable cores near the network interface. In this work, we explore the feasibility of SmartNIC DPUs in supporting an asynchronous communication model called "fire-and-forget", particularly its core message routing service. We design a communication offloading engine called Buddy that decouples communication tasks from the application process. Buddy runs flexibly on SmartNIC DPUs such as the Nvidia BlueField-3 DPU and generic x86 CPUs. Our evaluation results in five applications identify the memory-to-communication ratio as a key predictor of the offloading performance. Host-dominated workloads, such as Quicksilver and Sparse Matrix Transpose, achieved up to 1.55x speedup with communication offloaded to the DPU. We further identify a 625x increase in DRAM traffic due to the absence of Direct Cache Access support on the DPU, highlighting a critical need in future SmartNIC designs.

ABSTRACT. Fine-grained memory profiling is critical for optimizing software on modern hierarchical memory systems, yet it is fundamentally limited by the static–dynamic semantic gap. During compilation, high-level program semantics, such as variable names, types, and structural relationships, are lost. This loss makes it challenging to map low-level memory accesses back to their corresponding source-level constructs, particularly for complex, pointer-intensive data structures in C/C++. To bridge this gap, we introduce MemBridge, a profiling framework built on variable-centric instrumentation. MemBridge integrates compile-time semantic information directly into a dynamic binary instrumentation pipeline. This integration enables fully automatic and precise attribution of memory accesses to their corresponding source-level variables, including accesses to heap objects reached through multi-level pointers. By focusing instrumentation only on developer-specified data structures, MemBridge significantly reduces runtime overhead, making iterative, fine-grained analysis practical. The framework is cross-architecture (supporting x86 and ARM) and extensible through plug-in runtime analyzers. In its optimal configuration, MemBridge introduces only about 40% runtime overhead on average, representing a substantial improvement over DINAMITE and Gleipnir, which often incur slowdowns of tens to hundreds of times. Using its built-in false‑sharing analyzer to guide code optimization, we demonstrate over 4× performance improvement in large-scale applications.

ABSTRACT. Symmetric rank-2k update (SYR2K) is a core BLAS-3 routine but remains hard to optimize on GPUs because only triangular output is valid. However, few existing methods pay enough attention to the triangular characteristics of the output matrix, reducing memory access efficiency and computational performance. We present $TBF$, a tunable blocking-and-fusion framework that treats off-diagonal and diagonal regions differently: fused GEMM-like kernels for off-diagonal blocks and shape-aware batched SYR2K kernels for diagonal blocks. $TBF$ includes joint Batch-$K$ flattened tiling, dual-term shared-tile buffering, and cross-platform parameter tuning. On NVIDIA A100, A800, AMD MI210, and HYGON Z100, $TBF$ achieves up to 1.4$\times$ over cuBLAS and up to 1.7$\times$ over rocBLAS on regular sizes, with larger gains on short-wide cases.

ABSTRACT. Edge devices operate under strict physical thermal limits. When running continuous AI workloads, traditional static operators frequently push hardware beyond these boundaries, triggering severe thermal throttling. This mismatch causes a precipitous throughput collapse and unpredictable latency spikes, violating the strict Quality of Service (QoS) of edge AI. To ensure resilient execution, we present MoProteus, a cloud-edge framework that formulates thermal mitigation as a dynamic operator synthesis and dispatching problem. MoProteus integrates offline LLM-driven synthesis of diverse operator variants with sub-millisecond online edge dispatching via a zero-shot AST-GAT predictor. By preempting reactive OS-level DVFS, this architecture enables edge nodes to instantly switch operators and dynamically adapt to thermal constraints. Extensive evaluations on ARM and RISC-V platforms demonstrate that MoProteus virtually eliminates thermal throttling, reducing the Throttling Time Ratio (TTR) to 1.2\% and improving the Energy-Delay Product (EDP) by up to 39\%. These results highlight a general paradigm for achieving highly stable, energy-efficient AI execution.

ABSTRACT. Computing providers offer flexible, scalable and heterogeneous resources. However, their usage often leads to energy waste due to bad user choices. During a job submission, users may choose a cluster more powerful than needed for workloads, or leave the choice to scheduler. In both cases, the lack of guidance can lead to unnecessary energy consumption. We study this problem by evaluating energy gains achieved by a recommendation system that assists users with more energy efficient cluster choices. We analyze historical workloads from a resource provider to extract consumption and performance patterns. Using these profiles, we recommend clusters that can run similar jobs more efficiently.

To evaluate the accuracy of recommendations, we execute evaluation workloads. Workloads are first executed on a cluster chosen by job scheduler, then submitted to the system to obtain a recommended cluster, and finally executed on the recommended cluster and all other clusters of the computing provider. Results show that the clusters recommended by the system achieve an average relative position score of 0.97, where 0 corresponds to the worst observed cluster for a workload, and 1 to the best.

ABSTRACT. As datacenters continue to grow in scale, their energy con- sumption and resulting carbon footprint have become pressing concerns. With the increasing share of renewable energy in a datacenter’s mixed energy supply, shifting task execution to periods of high green-power availability is a promising strategy to reduce carbon emissions. However, in heterogeneous computing environments, also the power consumption of compute nodes in a datacenter can vary. In practice, workloads sub- mitted to datacenters are often not isolated tasks, but entire workflows consisting of interdependent tasks with precedence constraints. A fur- ther challenge arises from the fact that carbon emission reductions must typically be achieved under strict workflow deadlines. In this work, we show that the problem posed by these challenges for the scheduler is NP-hard and admits no constant-factor approximation even for the uni- processor case. Motivated by this hardness, we present a novel algorithm CWM that combines carbon-aware mapping and scheduling to construct feasible solutions. Our approach integrates dynamic programming with efficient heuristics to exploit renewable energy availability and infras- tructure heterogeneity. To assess the quality of the new algorithm, we evaluate it against the state-of-the-art approach CaWoSched and show that CWM achieves significant reductions in terms of carbon emissions in experiments. In particular, we are able to achieve a median carbon cost reduction of 42% over the best version of CaWoSched when the dead- line is two times the makespan of a carbon-agnostic baseline. Note that CaWoSched itself already reduces the carbon-agnostic baseline by 36%.

ABSTRACT. Cloud computing has become an increasingly popular choice for handling the computational demands of bioinformatics analyses, which are often complex and data-intensive and where computational demands vary widely across different analyses. Running bioinformatics workflows in the cloud in many cases requires assigning resources considering worst-case scenarios, to prevent execution failures due to insufficient memory. While this approach minimizes failures, it also leads to significant resource waste and increased costs. Equally, under-allocating resources can extend execution times or even cause analyses to fail. Finding the right balance is crucial for ensuring efficiency, cost-effectiveness, and overall workflow reliability.

In this study, we explore the use of machine learning to estimate the actual resource needs of the bioinformatics tasks from our use case. We analyze one year of resource usage data from a company utilizing AWS Batch for bioinformatics processing. This dataset includes CPU and memory consumption metrics, along with metadata such as input file counts, file sizes, and algorithm parameters for each of the jobs. By training predictive models on this data, we aim to improve resource allocation, reducing both waste and the risk of failure while maintaining performance.

Moreover, we consider different strategies for integrating predictive models into real-world scientific workflow runners and identify challenges such as variability in resource usage patterns and unexpected behaviors. Our findings highlight key factors that influence prediction accuracy and suggest potential enhancements, including incorporating data complexity features, adaptive learning techniques, and real-time resource monitoring. This research contributes to more intelligent cloud resource management, optimizing bioinformatics workflow execution while reducing operational costs.

ABSTRACT. The Needleman-Wunsch (NW) algorithm, essential for DNA and protein sequence alignment, faces unique challenges when implemented on Graphcore's Intelligence Processing Unit (IPU). This work presents the first comprehensive characterization of NW on the IPU, exploring memory optimization strategies within the platform's 900MB on-chip SRAM architecture. We develop multiple implementation variants with dynamic workload distribution across 8,832 threads (1,472 tiles x 6 threads). Our benchmarks on the GC200 IPU demonstrate performance of 3-7 GCUPS for realistic workloads and up to 36 GCUPS for sustained diagonal computations, exceeding a GPU baseline (15 GCUPS on NVIDIA A30) by 2.4x. Memory optimization, reducing per-vertex data from seven variables to one, achieves 45% reduction in exchange code and 60% reduction in vertex instances. However, Poplar's static compilation overhead limits maximum sequence lengths to approximately 9,000 elements. We identify critical trade-offs between vertex granularity, memory footprint, and parallelism, providing practical guidelines for mapping wavefront algorithms to this emerging architecture.

ABSTRACT. Sparse graphs are ubiquitous in real and virtual worlds. With the phenomenal growth in semi-structured and unstructured data, sizes of the underlying graphs have witnessed a rapid growth over the years. Analyzing such large structures necessitates parallel processing, which is challenged by the intrinsic irregularity of sparse computation, memory access, and communication. It would be ideal if programmers and domain-experts get to focus only on the sequential computation and a compiler takes care of auto-generating the parallel code. On the other side, there is a variety in the number of target hardware devices, and achieving optimal performance often demands coding in specific languages or frameworks. Our goal in this work is to focus on a graph DSL which allows the domain-experts to write almost sequential code, and generate parallel code for different accelerators from the same algorithmic specification. In particular, we illustrate code generation from the StarPlat graph DSL for NVIDIA, AMD, and Intel GPUs using CUDA, OpenCL, SYCL, HIP, and OpenACC programming languages. Using a suite of ten large representative graphs and four popular algorithms, we present the efficacy of StarPlat's versatile code generator. Our experiments reveal that there is no single framework that outperforms others in all the cases.

ABSTRACT. Transformer-based models are widely used in modern artificial intelligence, and the attention mechanism is a major determinant of their runtime efficiency. To accelerate matrix-intensive workloads, such as attention, ARMv9 introduces the Scalable Matrix Extension (SME) to enhance matrix processing capabilities on ARM CPUs. However, efficiently accelerating attention with SME remains challenging because of suboptimal compute-unit utilization, inefficient memory access, and limited task-level parallelism. To address these challenges, we present SMEAtten, a fast and memory-efficient attention design for ARMv9 CPUs with SME. SMEAtten incorporates three key techniques: throughput-driven interleaved matrix-vector attention kernels, an SME-adapted data layout and access scheme based on blocking, packing, buffering, and access-compute overlap, and inter-task parallelism exploitation. Experimental results show that SMEAtten delivers an average speedup of 13.62× over state-of-the-art baselines and achieves up to 56.09× acceleration in PyTorch integration evaluations. SMEAtten also supports efficient execution on different ARMv9 platforms, including LX2 and Apple M4.

ABSTRACT. Spatial accelerators are critical for achieving high performance and energy efficiency in domain-specific computing, but fully exploiting their potential requires efficient compiler support. Recent reinforcement learning (RL)-based mappers have shown promising results; however, state-of-the-art approaches typically employ dual-GNN encoders that model mapping-state components using isolated graphs. This structural separation creates an information barrier that limits the extraction of higher-order cross-graph relationships and severely degrades the semantic representation of partial mapping information. To address this limitation, this paper presents HGNNMap, a heterogeneous graph neural network (HGNN)-based framework that unifies the dataflow graph, hardware abstraction graph, and partial mapping into a single Heterogeneous Mapping State Graph (HMSG) and learns their joint representations. Experimental results show that HGNNMap achieves average compilation speedups of 9.35$\times$ on ADRES and 2.77$\times$ on HyCUBE over state-of-the-art dual-GNN-based mappers, demonstrating the effectiveness of introducing HGNNs into spatial accelerator mapping.

ABSTRACT. This paper proposes the causality relation for mobile multiagent systems and examines whether this relation can be detected in the presence of faulty agents. Towards this end, we first adapt the happened before or the causality relation over events from distributed message-passing systems to mobile multiagent systems. We propose three variants of this new relation -- regular causality, weakly correct causality, and strongly correct causality -- and examine each for its fault-tolerance in the face of Byzantine agents. We establish some fundamental results on the solvability and unsolvability of causality detection in multiagent systems where some of the agents may be Byzantine. Specifically, we show that regular causality and weakly correct causality cannot be detected in the presence of even a single Byzantine process, whereas strongly correct causality, where there is no influence of Byzantine agents, can be detected.

ABSTRACT. We present efficient parallel algorithms for computing maximal matchings in hypergraphs. Our algorithm finds locally maximal edges in the hypergraph and adds them in parallel to the matching. In the CRCW PRAM models our algorithms achieve $O(\log{\log{\Delta}}\log{m})$ time with $O(\kappa\log {m})$ work w.h.p. where $m$ is the number of hyperedges, and $\kappa$ is the sum and $\Delta$ is the maximum of all vertex degrees. The CREW PRAM model algorithm has a running time of $O((\log{\Delta}+\log{d})\log{m})$ and requires $O(\kappa \log {m})$ work w.h.p. It can be implemented work-optimal with $O(\kappa)$ work in $O((\log{m}+\log{n})\log{m})$ time. We prove a~$1/d$-approximation guarantee for our algorithms. We evaluate our algorithms experimentally by implementing and running the proposed algorithms on the GPU using CUDA and Kokkos. Our experimental evaluation demonstrates the practical efficiency of our approach on real-world hypergraph instances, yielding a speed up of up to 76 times compared to a single-core CPU algorithm.

ABSTRACT. Computing the inner product of vectors with long-integer entries is a fundamental operation in cryptographic and linear algebra workloads. While sub-quadratic multiplication algorithms like the Toom-Cook family are widely used to accelerate these operations for practical input sizes, existing optimizations have primarily targeted arithmetic complexity. Consequently, the significant performance bottleneck of communication (I/O) costs in parallel and memory-constrained environments has remained largely unaddressed. In this paper, we present a communication-avoiding algorithm for computing long-integer inner products using parallel Toom-Cook-$k$ algorithms (for $k \in \{2, 3, 4, 5\}$). Our approach builds upon I/O-optimal Toom-Cook representations by adapting the lazy interpolation technique to prioritize the reduction of communication over arithmetic costs. Furthermore, we introduce a novel scheduling strategy parameterized by $\epsilon \in (0, 1]$, which strategically leverages recomputation. This parameter controls a trade-off, allowing us to drastically reduce the leading coefficient of the communication cost in exchange for a modest increase in a lower-order arithmetic term. Theoretical analysis demonstrates substantial improvements: for $\epsilon = 0.05$, our algorithm reduces the leading communication coefficient from $34.5$ to $14.81$ for Karatsuba ($k=2$), with analogous reductions for Toom-$3$, Toom-$4$, and Toom-$5$. Our comprehensive cost analysis confirms these bounds hold in both parallel and sequential ($P=1$) computational models, offering a highly efficient, I/O-conscious framework for large-scale inner-product computations.

ABSTRACT. We focus on the problem of checkpointing (or taking a snapshot) in fully replicated eventually consistent distributed databases. In particular, we consider the problem of taking Distributed Transaction-Consistent Snapshots (DTCS). A typical example of such a system is a replicated main-memory database that provides strong eventual consistency. This problem is important and challenging for several reasons: (1) eventual consistency often creates anomalies that the users do not anticipate. Hence, frequent snapshots that can be used to ascertain desired invariants are highly beneficial in their maintenance, and (2) traditional distributed snapshot algorithms lead to significant overhead and/or inconsistencies such as storing dirty writes of incomplete transactions.

A key benefit of DTCS is that it summarizes the computation by a sequence of snapshots that are strongly consistent even though the underlying computation is only weakly consistent. In essence, when anomalies arise in an eventually consistent system, DTCS enables one to concentrate solely on the snapshots surrounding the time point of the anomaly.

By showing that traditional distributed snapshots lead to inconsistencies and/or excessive overhead, we define the notion of size-minimal DTCS for fully replicated databases. We present MuFASA, an algorithm for a size-minimal DTCS with minimal checkpointing overhead (only O(n) new messages and the addition of a single counter for existing messages). MuFASA also provides a significant benefit over existing checkpointing algorithms for distributed systems and replicated main-memory databases by being a fully asynchronous protocol.

ABSTRACT. Writing high-performance GPU kernels for transformer workloads remains a significant engineering challenge. Nvidia's cuTile library, introduced in December 2025, offers a tile-centric programming model that aims to simplify kernel authoring while retaining near-expert performance. In this work, we evaluate cuTile against Triton, Nvidia Warp, and optimized baselines (PyTorch) across three representative transformer primitives: general matrix multiplication (GEMM), Flash Attention, and Paged Attention. Various batch sizes and sequence lengths were compared for GEMM, and Flash Attention respectively. All experiments are conducted on an Nvidia Blackwell GPUs (Blackwell sm_120) and profiled with Nvidia Nsight Systems. We find that cuTile delivers competitive kernel-level performance on GEMM and Flash Attention, but needs careful optimization to close the gap with Triton on Paged Attention. Optimizations include compile-time index tiling, disabling gather bounds checking, memory latency hints, target architechture selection, optimization hints, and changes in math expressions. Our results suggest that cuTile's tile abstraction is well-suited for regular, compute-bound kernels but faces challenges on memory-bound workloads. We discuss the implications for GPU kernel productivity and outline directions for improvement.

ABSTRACT. The RISC-V Vector Extension~(RVV) is a cornerstone for sustaining compute throughout in scientific and machine learning workloads. However, compiler support and performance monitoring on RVV~1.0 hardware remain actively evolving. In this work, we design a suite of assembly microbenchmarks to calibrate performance counters on the BananaPi-F3 RVV hardware. Using the benchmarks, we find that predication overhead and stride load pose performance bottlenecks that current compiler cost models do not yet fully capture. Evaluating GCC 15 and Clang 21 across six scientific and ML applications, GCC 15 produces more stable and efficient code generation, outperforming Clang 21 in four of six benchmarks. Clang 21 achieves superior performance only in SGEMM and DGEMM, attributable to more aggressive instruction reduction as confirmed by our validated perf counters. Default LMUL selection proves near-optimal in most cases, though GCC 15 shows greater potential for performance gains through larger LMUL tuning than Clang 21. Finally, we contribute an RVV backend for Google's Qsim quantum circuit simulator implemented using RVV intrinsics, where GCC 15 again outperforms LLVM 21 on this complex, real-world workload.

ABSTRACT. Dense matrix operations are among the few numerical tasks where modern processor architectures can achieve throughput near the peak of floating-point operations. Implementations of commonly utilized mathematical library functions such as gemm necessitate advanced optimization adhering to recognized implementation strategies. The most difficult aspect continues to be a microkernel. To achieve optimal performance on a specific processor solution, this micro-kernel must be meticulously optimized, considering various aspects of the processor's micro-architecture and L1 data cache design. Due to the necessity for strict control over the used instructions, it remains prevalent to depend on implementations of these micro-kernels crafted in assembly language.

Currently, an increasingly diverse set of processor solutions is available in the market. This renders the conventional method of manually crafted micro-kernels progressively less viable. To address this problem, we propose an assembler generator utilizing suitable abstractions to enable the generation of high-performance code for various processor solutions across diverse instruction set architectures. The software framework facilitates the semi-automatic generation of micro-kernels that can be incorporated into the existing BLAS library implementation BLIS. This paper presents results for a diverse array of processors that support x86, Arm, and RISC-V SIMD and vector instruction sets. The results indicate that the throughput attained is comparable to, and in certain instances surpasses, the performance of open-source or vendor-supplied BLAS libraries.

ABSTRACT. Modern multi-core processors increasingly combine cores of different sizes to balance performance and power. However, when energy efficiency is the primary objective, selecting the optimal core types, number of cores, and operating frequencies for a given workload is not always straightforward. In this study, we experimentally evaluate eight hybrid processors from Intel’s Alder Lake, Raptor Lake, and Arrow Lake architectures, as well as AMD's Zen 4 and Zen 5 platforms. We conduct our experiments across three bottleneck-oriented workloads, compute-bound, bandwidth-bound, and latency-bound, measuring energy consumption and performance while varying the number of active cores and the operating frequencies. To provide practical guidance, we compare power- and performance-efficient cores across these different configurations. Our results highlight how energy consumption differs across successive processor generations under different workloads, providing a practical classification between core types for modern hybrid processors. Additionally, we examine how energy efficiency scales with respect to die area.

ABSTRACT. Static scheduling of task DAGs on homogeneous parallel platforms is NP-hard, and existing list-scheduling heuristics rely on local task attributes or single-path estimates that may overlook global structural patterns. We introduce Longest Betweenness Centrality (LBC), a graph-theoretic metric that quantifies a task's importance by measuring its participation in long dependency paths within a DAG, computed efficiently via an adaptation of Brandes' algorithm that exploits the topological structure of DAGs. Building on LBC, we propose several list-scheduling heuristics, with a focus on LBC-SRL, an iterative variant that recomputes task priorities as the DAG is progressively reduced. Experiments on five synthetic task DAG models and three real-world scientific workflows show that LBC-SRL consistently outperforms MinMin, HCPT, and PEFT and matches or exceeds HEFT in more than half of all synthetic test cases. Real-world evaluation across three scientific workflow domains reveals that LBC-SRL and HEFT capture complementary DAG properties. Across all the experimented real-world domains, LBC-SRL consistently produced shorter makespans than both PEFT and MinMin.

ABSTRACT. Retrieval-Augmented Generation (RAG) effectively mitigates hallucination in Large Language Models (LLMs) by incorporating external knowledge bases. However, augmenting prompt with numerous external documents leads to significant Time-To-First-Token (TTFT) latency. While existing work addresses the computational bottleneck of long prompts in the prefill stage by pre-computing and storing Key-Value (KV) chunks of documents on disk, this approach introduces a severe I/O overhead. This paper proposes ApproxRAG, an optimization framework that accelerates RAG inference by co-scheduling the data flow among the disk, host memory, and device memory. This framework consists of three key components. Firstly, before loading data into memory, it introduces a hybrid compression method to reduce disk footprint. Secondly, in the event of a cache miss, a similarity-based KV cache reusing mechanism is triggered to prioritize retrieving semantically similar data already in memory, avoiding costly disk access. Finally, for data resident in memory, we design a cache eviction policy, which holistically considers the frequency, recency, and initial retrieval score of chunks to maximize the utility of limited memory space. We evaluated our framework on LLaMA 2-7B and LLaMA 2-13B, using Wikipedia as the knowledge base and Natural Questions (NQ) and Massive Multitask Language Understanding (MMLU) as benchmarks. Experimental results demonstrate that, compared with naive RAG, ApproxRAG achieves up to a 3.66X speedup in TTFT with negligible impact on generation quality.

ABSTRACT. Utilizing heterogeneous GPU clusters for training large language models (LLMs) is becoming a prevalent trend in the future. Existing work is only effective on a given number of GPUs, often neglecting the complexities involved in manually determining the specific types and quantities of GPUs needed, which can be a significant burden for developers. To address this issue, we propose Frenzy, a memory-aware serverless computing method for heterogeneous GPU clusters. Frenzy allows users to submit models without worrying about underlying hardware resources. First, Frenzy predicts the required number and type of GPUs by estimating the GPU memory usage of the LLM. Then, it employs a low-overhead heterogeneity-aware scheduling method to optimize training efficiency. Finally, Frenzy implements a fault-tolerant elastic resource orchestrator to ensure stable system operation. We validate Frenzy's performance by conducting multi-task LLM training tests on large-scale heterogeneous GPU clusters both on physical clusters and simulator. The results show that, compared to state-of-the-art solutions, Frenzy reduces average task completion time by 12%-50%, decreases scheduling overhead by 10 times, and achieves over 92% accuracy in predicting GPU memory usage.

ABSTRACT. This paper presents Dodoor, a randomized decentralized scheduler for heterogeneous clusters. Dodoor removes hot-path probing via batched cache refreshes and introduces a heterogeneity-aware resource-load score that ranks sampled candidates using multidimensional fit and queued-duration pressure. On a 101-node CloudLab cluster, Dodoor cuts scheduler messages by 55--66% while improving throughput by up to 33.2% (Azure VM) and 21.5% (FunctionBench) compared with decentralized baseline schedulers. Dodoor also reduces mean makespan latency by up to 12.1% and 7.2%, and tail latency by up to 21.9% and 24.6%.

ABSTRACT. Spin-transfer torque MRAM (STT-MRAM) is a promising technology for scaling GPU L2 caches thanks to its high density and near-zero leakage power. However, its high write latency and energy make simply replacing SRAM with STT-MRAM unattractive under the massive write traffic and concurrency of modern GPUs. This work observes that GPU writes exhibit strong coarse-grained spatial locality, such that cache blocks mapped to the same region tend to share similar write intensity. Motivated by this insight, we propose Region-Level Write-Intensity Prediction (RWIP) for GPU L2 cache based on hybrid-retention STT-MRAM. The L2 cache is partitioned into a low-retention (LR) region for write-intensive data and a high-retention (HR) region for read-dominant and long-lived data. RWIP instantiates a lightweight per-subpartition Region Predictor Table (RPT), which is accessed only after a write miss in both the LR and HR regions. RWIP leverages early region-level write activity to predict the write intensity of incoming cache blocks, thereby proactively allocating write-intensive blocks into the LR region. On average, compared to baseline GPU with SRAM-based L2 cache and the prior typical work, RWIP improves IPC by 19% and 6%, respectively, and reduces L2 dynamic power by 20% and 14%, respectively. Moreover, the high density of STT-MRAM allows RWIP to provision a larger L2 cache under an equal on-chip area, reducing DRAM power by 54% on average relative to the baseline.

ABSTRACT. GPUs have become central to high-performance computing and machine learning, yet efficiently using their full capabilities requires a thorough understanding of low-level runtime behaviors, many of which remain insufficiently documented. Among those, the data transfer warm-up, an initialization overhead usually associated with the first cudaMemcpy (the data transfer instruction) in a CUDA program, is commonly acknowledged yet poorly understood in the literature. In this paper, we revisit this phenomenon and present three contributions that extend its understanding. First, we demonstrate that the data transfer warm-up is not a fixed overhead bound to cudaMemcpy but rather a floating overhead that attaches itself to different CUDA operations depending on the context of the program. Secondly, we show that this overhead can be measured in CUDA programs that do not perform any cudaMemcpy at all, establishing that it is not tied to the transfer mechanism but rather to the internal memory management of GPUs. Thirdly, we report abnormal measures of the profiled duration for CUDA operations when CPU computation is interleaved in between them, even though the profiler confirms the absence of any temporal overlap between CPU activity and GPU operations. All the experiments were performed on an NVIDIA RTX 4080 Super using CUDA and were profiled using NVIDIA Nsight Systems 2025.1.3. These findings challenge the common assumption about GPU initialization costs and expose limitations in conventional benchmarking practices. We argue that a refined understanding of GPU warm-up behavior is necessary for accurate performance modeling and reproducible experimentation.

ABSTRACT. Modern multi-socket architectures offer a single virtual address space, but physically divide main-memory across multiple regions, where each region is attached to a CPU and its cores. While this simplifies the usage, developers must be aware of non-uniform memory access (NUMA), where an access by a thread running on a core-local NUMA region is significantly cheaper than an access from a core-remote region. For example, if the query answering within a database system is parallelized across the cores of multiple regions, then the portion of the database on which the query is operating should be distributed across the same regions to ensure local accesses. As the present data placement might not fit this, migrating pages from one NUMA region to another can be performed to improve the situation. To do so, different options exist: One option is to rely on automatic NUMA balancing integrated in Linux, which is steered by the observed access patterns and frequency. Another option is to actively trigger migration via the system call move_pages(). Unfortunately, both variants have significant downsides in terms of their feature set and performance. As an alternative, we propose a new user-space migration method called page_leap() that can perform page migration asynchronously at a high performance by exploiting features of the virtual memory subsystem. The method is (a) actively triggered by the user, (b) ensures that all pages are eventually migrated, (c) handles concurrent writes correctly, (d) supports pooled memory, (e) adaptively adjusts its migration granularity based on the workload, and (f) supports both small pages and huge pages.

ABSTRACT. With the widespread deployment of data-intensive applications such as big data and machine learning, hardware-accelerated compressed memory swap (CMS-H) is emerging as a promising solution to build high-performance and cost-efficient tiered-memory systems. However, prior works on CMS-H lack a performance comparison of CMS-H with various swap backends and detailed performance analysis of CMS-H based on a production-quality OS and commodity CPUs with support for Intel In-Memory Analytics Accelerator (IAA). To bridge this gap, this work compares the performance of CMS-H with representative swap backends including the one with the state-of-the-art NVM Express (NVMe) SSD technology, presents an in-depth performance analysis of CMS-H, and identifies its inefficiencies. Guided by the characterization results, we propose three optimization techniques (i.e., parallel page compression and decompression, zero-copy page decompression, and eager zspage allocation) for CMS-H.

ABSTRACT. Distance-based ISA is a class of architectures that specify operands using relative distances between instructions instead of register indices. This unique operand specification enables out-of-order execution without conventional register renaming, a critical bottleneck in scaling up wide-frontend processors. The practical efficiency of this hardware-software co-design relies heavily on Distance Adjustment (DA), which is a specialized compilation process that ensures consistency of reference distances across different branch paths. However, existing DA optimization methods cannot guarantee feasibility under all required constraints, leading to frequent fallbacks to inefficient baseline algorithms. This paper proposes Constraint-Based Distance Adjustment (CoDA), a novel approach that formulates the DA task as a constraint optimization problem. By incorporating previously unaddressed constraints into a mathematical model, CoDA provides a mathematical guarantee of solution feasibility, thereby eliminating optimization uncertainty. Evaluation results using the STRAIGHT ISA demonstrate that while the state-of-the-art method incurs fallbacks in 16.7% of cases on average, CoDA consistently achieves successful adjustment without any fallbacks. Furthermore, CoDA reduces additional MOVE instructions by 13.2% and total instructions by 3.8%, achieving up to 9.8% cycle reduction per benchmark and 2.2-2.9% on average. Energy consumption is also reduced by 1.4-2.5%, with CoDA-optimized STRAIGHT outperforming RISC-V by up to 9.2% on a future wide-frontend processor design.

ABSTRACT. Data layouts can significantly impact application performance. However, choosing the best-performing layout for a given application, especially one using complex data structures, remains a challenge: how the data-layout performance depends on factors such as the data access pattern and machine parameters is not sufficiently understood.

In this paper, we present a \textit{2D design space exploration (DSE)} approach to systematically study the performance impact of data layouts. Starting from a given array of (complex) data structures and a set of representative C++ kernels that read the array, our approach (1) generates all possible data layouts for the input array via structure splitting and data member reordering, (2) generates and executes the kernels with each layout, and (3) collects performance data. Through exhaustive testing, we empirically quantify the impact of different layouts and observe patterns that can help develop data layout selection guidelines.

To demonstrate our approach, we apply it to a set of kernels representing common high-energy physics computations and a particle structure with 7 data members. We generate and measure over 37500 versions of each kernel for 4 different architectures (2 Intel and 2 AMD CPUS), and collect over 6 million data points. Our results indicate that data layouts do have a significant impact on runtime performance when the input is sufficiently large. We identify several causes for the large performance gaps (up to 67%) between layouts and, based on these observations, suggest empirical guidelines for (semi-)automated data layout refactoring.

ABSTRACT. Traces are essential for HPC root-cause analysis, but full tracing at scale without countermeasures incurs prohibitive overheads and data volume. Selective tracing is one approach to combat this issue, by restricting trace collection on a structural and temporal level. Configuring such selective tracing typically requires iterative profiling, source code modifications and often recompilation. We present a process for systematic selective tracing that combines static whole-program analysis with insightful efficiency metrics. At compile time, it extracts an annotated call graph and embeds runtime-reconfigurable instrumentation based on LLVM XRay. At runtime, a low overhead profiling identifies performance-critical regions, while a lightweight validation mechanisms resolve statically unresolvable call-graph issues caused by dynamic function calls. Analysts can then derive a selective tracing configuration according to analysis requirements without the need to rebuild the application. This enables targeted tracing with reduced overheads and trace sizes. A case study using this workflow on Vlasiator, reduced initial profiling overhead from 300% to 17%. The generated traces maintained critical insight, while reducing trace size by 10x compared to the default tracing approach.

ABSTRACT. he computational demands of modern Deep Neural Networks (DNNs) pose significant challenges for deployment on resource-constrained edge devices with heterogeneous CPUs and GPUs. Conventional static GPU-only execution leads to inefficient resource utilization and high energy consumption due to limited coordination between computation and data movement. This paper presents a coordinated runtime system that integrates dynamic task scheduling with bidirectional prefetching to optimize DNN inference. The system intelligently distributes layers between CPU and GPU based on real-time workload, cache status, and memory access patterns, while a hardware-aware prefetcher proactively migrates data to hide access latency. Evaluated on an Intel Core i7-10875H and NVIDIA RTX 2080 Super with ImageNet-scale models (AlexNet, ResNet-50, VGG16), our approach reduces energy consumption by 16-23% compared to GPU-only execution while maintaining within 8% of its performance, and improves cache hit rates by up to 17.8%. For compute-intensive models like VGG16, it achieves balanced CPU-GPU utilization (55.4% and 74.6%), demonstrating effective resource coordination for energy-efficient edge inference.

ABSTRACT. In resource-constrained edge intelligence environments, Neural Processing Units (NPUs) have become the mainstream accelerators for Deep Learning Inference (DLI) tasks. However, the absence of fine-grained preemptive scheduling in existing NPUs limits their ability to meet the strict real-time requirements of concurrent DLI workloads. To sustain performance in complex, multi-DNN collaborative workloads, edge intelligence devices often rely on NPU overprovisioning, which leads to inefficient resource utilization and increased system cost. This paper presents MARS, a Multi-model Aware Real-time Scheduler designed for coordinated DLI execution on NPUs. MARS formulates the scheduling challenge as a real-time optimization problem for heterogeneous job chains with blocking constraints and addresses it through a three-phase framework. In the offline phase, a Utility-driven Partition Scheme Selection (UPSS) algorithm determines efficient model partitioning strategies to reduce the scheduling search space. During the online phase, the Simulated Annealing-based Earliest Deadline First for Heterogeneous Job Chain Real-Time Scheduling (SAEDF-HCRS) algorithm dynamically optimizes task scheduling decisions. Finally, the pipeline execution phase applies multidimensional optimization to manage heterogeneous job chains, while maintaining responsiveness. Simulations show that MARS achieves millisecond-level response latency for concurrent tasks and improves success rates for multi-DLI scheduling by up to 25% compared with state-of-the-art methods under high-load conditions.

ABSTRACT. High-performance computing (HPC) systems commonly rely on the EASY backfill scheduler to maximize resource utilization. This scheduler uses runtime estimates to determine reservation lengths and identify backfill opportunities. While machine learning (ML)-based approaches produce runtime predictions that support more efficient scheduling, prior work has evaluated these predictions using conventional accuracy metrics such as mean squared error, which do not capture scheduling-relevant behavior. To mitigate job termination risk, runtime prediction methods can use high-quantile estimates (e.g., the 99th percentile). However, this approach yields non-uniform prediction coverage across job durations: short jobs achieve near-100% coverage at the cost of severe overprediction, whereas long jobs fall below the target coverage (i.e., 99% job success rate). As a result, aggregate scheduling metrics mask the underlying disparity in per-stratum prediction coverage and the resulting wasted reservation time. We identify this non-uniformity as a previously uncharacterized structural source of scheduling waste. To quantify its impact, we decompose wasted reservation time by runtime percentile bin and show that the severity of overprediction varies by orders of magnitude across job durations. We propose Stratified Conformal Quantile Regression (S-CQR), a calibration method that replaces the single global correction of standard CQR, whose residual distribution is dominated by the numerically prevalent short jobs, with stratum-specific corrections. Each correction is computed to jointly control reservation waste from overprediction and kill risk from underprediction within its runtime stratum. We evaluate S-CQR on five job traces (Mira, Theta, Intrepid, Aurora, and Cooley) from the Argonne Leadership Computing Facility (ALCF). S-CQR reduces the non-uniformity in prediction coverage across all strata, while maintaining scheduling coverage above 99%. In EASY backfill simulations, S-CQR reduces mean wait time by up to 28.3% on near-saturated workloads (Mira), with wait time reductions ranging from -1.2% to -28.3%.

ABSTRACT. Graph Neural Networks (GNNs) have attracted significant attention for supporting a wide variety of graph-based applications, including recommender systems, drug discovery and traffic forecasting. However, training GNNs at scale remains challenging, as real-world graphs impose substantial computational and memory demands while exhibiting irregular access patterns that limit hardware efficiency. The limited memory capacity of the GPUs despite their high computational throughput, often prevents large graphs from fitting on a single device. Consequently, CPU-based distributed training is commonly adopted to leverage aggregate DRAM capacity. However, this introduces additional challenges related to graph partitioning, workload imbalance and inter-node communication, which increase both runtime complexity and energy consumption. In this work, we propose RAGNN, a Resource-Aware framework for Graph Neural Network training at scale, which addresses the aforementioned challenges. RAGNN partitions the input graph into smaller subgraphs for distributed execution, enabling scheduling decisions that explicitly balance runtime performance and energy efficiency. Our extensive experiments on real-world datasets, GNN models and sampling strategies demonstrate that our approach outperforms METIS-based partitioning by up to 67.61%.

ABSTRACT. High-level synthesis (HLS) enables FPGA design from high-level languages, but searching for high-quality hardware directive configurations remains expensive. Recent GNN-based predictors estimate latency and resource utilization for design space exploration, yet they often treat HLS prediction data as a flat distribution, making it difficult to capture both kernel-level shared structure and pragma-induced configuration-level variation. In addition, joint prediction of latency and multiple resource metrics introduces gradient conflicts in multi-task learning. We propose a two-stage GNN-based framework that learns HLS design points in a coarse-to-fine manner: it first organizes a stable kernel-level representation distribution and then refines pragma-guided configuration-level differences within that distribution. The framework combines Indirect Intra-Kernel Distance Loss (IIKDL) for Stage-1 regularization, a Residual Fitting Module (RFM) for Stage-2 refinement, and Magnitude-Aware PCGrad (MA-PCGrad) for stable joint optimization. Experiments show that, compared with HARP and Hier-MoE, our method reduces mean squared error by 41\% and 17\%, respectively. When integrated into downstream cross-kernel design space exploration, it achieves 41\% and 12\% geometric-mean speedups over HARP and Hier-MoE, respectively. Additional cross-version adaptation results further support the scalability and reuse of the proposed framework over heterogeneous HLS design spaces. Code: \url{https://github.com/Pahdor/DS2-HLS}.

ABSTRACT. Modern large language model (LLM) applications increasingly consist of high-frequency short-sequence workloads that form long chains of data-dependent GPU kernels, leading to low hardware utilization. We present DACOS, a dependency-aware cross-kernel overlapping framework. Leveraging programmatic dependent launch, DACOS pre-launches successor kernels and executes dependency-independent work, such as operand preparation and data preloading, before the required data from preceding kernels becomes available. DACOS combines dependency analysis, cross-kernel overlap construction, and cost-model-driven configuration to determine when kernels should be triggered and what work should be advanced. Evaluation with real-world LLM workloads shows that DACOS achieves up to 3.5× and 1.2× end-to-end speedups over TorchEager and TorchInductor, respectively, demonstrating the effectiveness of dependency-aware cross-kernel overlapping.

ABSTRACT. Converged computing architectures like AMD's MI300A Accelerated Processing Unit (APU) and Nvidia's Grace Hopper Superchip (GH200) are now featured in world's most powerful supercomputers. On these architectures, both CPU and GPU are on the same chip. However, fundamental design choices separate MI300A and GH200: the first comes with a single physically unified memory for the CPU and GPU cores, while the other has two separate memories, but with the ability for compute units to fetch information from both, through NVLink-C2C.

Heterogeneous compute applications (i.e. with latency and/or throughput sensitive tasks) are expected to get the most out of these new chips, without the CPU-GPU communication bottleneck of PCIe-based architectures. In this paper, we study how the different design choices in GH200 and MI300A can impact the performance of a balanced latency-and-throughput-sensitive simulation software. We also evaluate how converged architectures can reduce memory transfer costs. Finally, we suggest options to get the most out of these architectures based on our performance measurements.

Our findings show that, depending on the balance of latency-bound and throughput-bound tasks in simulation software, some converged architectures will be more suited than others for executing these codes, with differences in speed of up to 2.78x in our case.

ABSTRACT. Scheduling algorithms in parallel computing strive to produce as good schedules as possible, yet slack is not an unusual occurrence in multiprocessor schedules. Slack refers here to the difference of the earliest and the latest possible execution start time of an available task, when a processor is available. Knowing the total slack in a schedule is an interesting indicator as it shows flexibility that is in a schedule. Slack is prominently used in slack reclamation algorithms, which attempt to save energy by using slack in combination with dynamic voltage and frequency scaling (DVFS) to slow down task execution. Such an approach is based on the premise that common task schedules have significant slack. But is that true? There is no wide knowledge or study analysing the amount and characteristic of slack in schedules of typical parallel programs.

In this paper we first investigate how slack can be identified and maximised in a given schedule. This uses existing slack reclamation algorithms, but none of them maximises slack in general. We propose a new slack reclamation algorithm, called Maximal-Antichain. Subsequently, we propose a methodology to investigate slack in schedules produced by list scheduling and cluster scheduling and undertake an extensive experimental study to examine the amount and characteristic of slack in multiprocessor schedules. We analyse the produced schedules, distinguishing between slack, idle time, and unused processors. Our findings show Maximal-Antichain identifies more slack than existing algorithms. The results also inform under which conditions slack reclamation algorithms can be efficient and when it is better to simply use less processors instead.

ABSTRACT. Sequence Parallelism (SP), such as DeepSpeed-Ulysses, has emerged as the de facto standard for scaling high-resolution video generation for its superior memory efficiency in handling long contexts and reduced communication. However, the bandwidth-intensive All-to-All communication inherent in SP still becomes a critical bottleneck, severely limiting scaling efficiency. We propose Sparsh, a distributed video diffusion inference framework with predictive sparse communication. Unlike standard Ulysses-style sequence parallelism which indiscriminately transmits attention tensors in all diffusion steps, Sparsh eliminates the transmission of Key and Value tensors entirely in most steps by exploiting their temporal redundancy. Particularly, instead of remotely fetching KV tensors via All-to-All communication, Sparsh introduces a fidelity-aware predictive synthesis mechanism that reconstructs remote KV states locally. Further, Sparsh employs an online adaptive controller that dynamically adjusts prediction strategies based on real-time error feedback, ensuring that the communication reduction does not compromise generation quality. Experiments on multiple models demonstrate that Sparsh reduces communication latency by 50% in predictive steps and by 28% overall compared to state-of-the-art Ulysses baselines, offering a scalable solution for distributed high-resolution video generation.