ABSTRACT. An 8-bit time-to-digital converter (TDC) for alldigital frequency-locked loops is presented. The selected architecture uses a Vernier delay line where the commonly used D flip-flops are replaced with a single enable transistor in the delay elements. This architecture allows for an area efficient and power efficient implementation. A prototype chip has been implemented in a 65 nm CMOS process with an active core area of 75μm × 120μm. The time resolution is 5.7 ps with a power consumption of 1.85 mW measured at 50 MHz sampling frequency.

ABSTRACT. This paper proposes two surfing architectures of the front-end for cardiac ultrasound imaging systems by removing the high voltage (HV) transmitter/receiver (Tx/Rx) switch in traditional ultrasound imaging systems, and connecting the input and the local ground of the Rx to the output of the Tx directly. Both advantages and challenges are presented. During the emitting phase, the Rx is on reset mode and voltages at all internal nodes in the Rx will follow the transmitting pulse, and this phenomenon exhibits the Rx is in the surf as the transmitting pulse. By removing the Tx/Rx switch, the Rx can avoid saturating status during the pulse emitting phase in Tx, and can receive the reflected echo signals in an efficient way after the emitting phase. While the input of the Rx connecting to the PZT transducer directly without the Tx/Rx switch, the received echo signals will not be distorted by the Tx/Rx switch, and the switched-capacitor (SC) front-end of the Rx can be relaxed in the design. Currently the bulk CMOS technology may not support this architecture because of its intrinsic process limitation and relatively large parasitic capacitance of the PN junctions. SOI CMOS technology could be a feasible CMOS technology because its parasitic capacitance of the PN junction is much smaller and its process is different from the bulk CMOS technology. The simulation is based on an inverter-based SC amplifier in a high voltage 0.18 µm 50 V / 1.8 V bulk CMOS technology, and a HV switch is based on a model which cannot be implemented in a bulk CMOS technology.

ABSTRACT. Abstract— In the paper we present fast and effective method of modeling of coupled interconnect in Spice simulator by means of S-parameters. The paper presents an approach based on the method of successive approximations, but taking into account the dependence on the frequency of line parameters. The concept is to use the rational approximation of the matrix of per-unit-length parameter of the line calculated for each frequency. In our approach we implemented the scattering parameters of transmission line to the Spice simulator.

ABSTRACT. Nowadays, Dynamic Partial Reconfiguration of digital circuits like Field Programmable Gate Arrays (FPGA) appears as a sustainable hardware evolution phenomenon. Like many other architectures, Cellular Nonlinear Networks (CNN) are able to be adjusted or reprogrammed, when the characteristics of the problem are changed. Currently, changing memory content like parameters effects only the operation of architecture which has all functions, including momentarily redundant ones. The appeared question is how the overhead created by functional redundancy of hardware can be decreased. As discussed and studied in this paper, hardware pieces can be reconfigured to completely different designs when the characteristic of the problem is changed in run-time. The paper aims to exhibit the benefits of Dynamic Partial Reconfiguration feature of contemporary FPGAs on CNNs varying/evolving in time under the Network of Networks concept. For this purpose, trigger-wave generating sub-networks are combined using different reconfigurable partitions of an FPGA and a primary network is constituted which generates different trigger-wave patterns. This conceptual design unrolls how dynamic partial reconfiguration is capable to realize irregular/asymmetric network components.

ABSTRACT. A CMOS image pixel circuit is proposed which is able to be tested by an electrical test method in this paper. The image pixel circuit is tested as an analog circuit without irradiating light to it. A CMOS image sensor circuit is designed with the image pixel circuit. It is examined by Spice simulation whether open defects in the image pixel circuit can be detected by the electrical test method. The results show that 89% of our inserted open defects can be detected by the test method.

ABSTRACT. In this paper, a new forward body biasing scheme is proposed for CMOS inverters used in subthreshold ring oscillators (ROs). In the proposed scheme by using auxiliary transistors higher forward body biasing voltage magnitudes are achieved compared with the conventional forward body biasing (FBB) schemes. In the literature swapped body biasing (SBB) and dynamic threshold MOSFET (DTMOS) are conventionaly used to obtain forward body biasing in the transistor. Threestage ROs are designed for the target frequency of 13.56 MHz by using the proposed and the conventional FBB techniques in CMOS inverters. The architectures are implemented in a standard 0.18um CMOS technology. Post layout simulations (PLS) are performed using the Cadence Spectre simulator. The power dissipation is selected as a figure of merit (FOM) to evaluate the performances of ROs. PLS results show that with subthreshold supply voltages, the RO using the proposed forward biasing scheme consumes 451nW of power. This power dissipation is 30% less compared with SBB based RO and 48% less compared with DTMOS based RO.

ABSTRACT. A recent innovative technology in the field of plasma-wall interaction in nuclear fusion experiments is represented by the Liquid Lithium Limiter (LLL), a Limiter with a cooling system based on Liquid Lithium. Since its performance depends on the spatial temperature distribution, a thermal load analysis is important for long term developments. Furthermore, temperature is often not uniformly distributed leading to hot spots formation, that should be detected in real time to avoid any plasma disruptions. In this paper, an approach based on the definition of a suitable Cellular Nonlinear Network algorithm for the real-time image processing of thermal images taken during a plasma experiment is introduced. It allows both to map the LLL temperature and to detect hot spots over the limiter surface. Off-line testing of the proposed procedure reveals the effectiveness of the approach paving the way to the modeling of the limiter surface temperature providing reliable information.

ABSTRACT. This work proposes a procedure for generating a loop filter state-space model used in MATLAB-simulations. The proposed procedure is a useful add-on to the well-known Schreier's Delta-Sigma toolbox, especially in complex domain. For complex domain, novel optimization methods for quadrature-noise insensitive noise transfer function are also presented.

ABSTRACT. This work proposes a novel Center-Of-Gravity (COG) defuzzifier circuit based on memristors. The proposed circuit overcomes the prime disadvantage of COG defuzzifiers, which is area occupancy, via the use of memristors. The main idea in the circuit is to store the singletons (output fuzzy sets) in the memconductance (reciprocal of the memristance). This reduces the multiplication into Ohm’s Law which provides significant area reduction. Meanwhile, the proposed circuit avoids the use of extensive analog processing in order to maintain high robustness. Simulations were conducted to validate the functionality of the circuit. Observed results deviate from the theoretical predictions by less than 4%.

ABSTRACT. In recent years, graph-cuts method has became increasingly useful methods for some kind of image processing problems. Graph-cuts is the method to formulate these problems as a probability model such as Markov random field, and the method to solve these problems as energy minimization problems. In graph-cuts, energy minimization problems are solved by getting minimum cut in grid graphs which are generated form images. However, the conventional graph-cuts algorithm cannot be obtained only a single minimum cut even if a graph has multiple-minimum cuts. Multiple-minimum cuts show that plural cuts with a same minimum cut capacity exist on the same graph. Therefore, little is known about the importance of obtaining multiple-minimum cuts in graph-cuts image processing. In this research, we propose a new image denoising method using multiple-minimum cuts based on the maximum-flow neural network. The maximum-flow neural network is our proposed max-flow / min-cut algorithm based on the nonlinear resistive circuit analysis, and can find all minimal cuts simultaneously when the graph has multiple-minimum cuts. In this simulation, we show an importance of getting multiple-minimum cuts for the image denoising.

ABSTRACT. This paper presents a quick and easy method for establishing the design conditions for a CMOS amplifier such that the design achieves near-optimum performance with respect to gain, bandwidth, noise, distortion, power and cost. The method is based on re-formulating the small-signal equations of circuit behavior in terms of an independent set of physically accessible design parameters. These new equations will enable one to easily identify a design and optimization procedure for any amplifier.

ABSTRACT. Actively simulated grounded inductors have been used in several applications ranging from filter to oscillator design as well as cancellation of parasitic inductances. In this work, we present new topologies for realizing four grounded inductors employing a single current differencing current conveyor (CDCC) and a minimum number of passive components, two resistors and one grounded capacitor. Furthermore, the circuits do not require any conditions of component matching. Finally, using the proposed inductance simulator a second-order high-pass filter is constructed. The performance of the proposed inductance circuit and filter circuit are verified and simulated by using SPICE.

ABSTRACT. Self-adaptivity is becoming a key feature of modern embedded systems to meet performance and power constraints in increasingly common situations where embedded application workloads show highly dynamic behavior. This paper presents a scalable framework for adaptive MultiProcessor System-on-Chip (MPSoC) systems that allows for adaptivity throttling.

ABSTRACT. Hand held battery powered devices are becoming increasingly complex, with embedded applications that regularly demonstrate very dynamic behavior and requiring advanced functionality. To avoid prohibitively high power consumption, novel techniques are needed to handle the increased dynamicity and complexity, e.g., through use of system scenario based design. In this paper a framework for system scenario resource management is presented and evaluated with a part of the H264/AVC video codec on an EFM32 microcontroller. By using DFS as a system knob, we obtain significant power reductions for different system scenarios occurring dynamically while the application is running. The framework overhead is negligible.

ABSTRACT. System scenario is a proactive methodology that classifies system operations from cost perspective, overcoming design complexity issues. The current study focuses on scenario implementation cost, evaluating two different hardware architectures. The first realizes the scenario detector on the same chip that the scheduling is applied, while the second exploits an extra off-chip hardware. For each option, a Look-Up-Table and a decision-tree detector is implemented. Design tradeoffs between scenario detection time and realization cost are explored. More precisely, a case study examines scenario-scheduling instantiations of a wireless application on a FPGA. Metrics like performance, chip area and power are taken into consideration. The scope is to extract a scenario implementation cost evaluation.

ABSTRACT. Photovoltaics, and renewable energy sources in general, are becoming an increasingly significant part of power generation in a worldwide scale. Though this development is hopeful for a sustainable future, it also creates additional challenges for the design and monitoring of grids and installations. Decisions cannot be permanently made during design time and several forms of dynamism have to be imported on every level of power production and distribution. In this work the potential of the System Scenario methodology in the aforementioned setting is showcased, for the level of power production. Specifically, System Scenarios are applied on the problem of reconfigurable topologies for photovoltaic modules. A comparison is made between traditional static designs and novel approaches, where the intra-module connections of a PV module can be altered dynamically. Building integrated PV is a field that could directly benefit from such advancements, so an example is presented for such an installation. Energy gains of 23.9 % are reported from the application of a dynamic methodology.

ABSTRACT. Systems on Chip (SOC) are powerful multiprocessor systems capable of running multiple independent applications, often with both real-time and non-real-time requirements. Scenarios exist at two levels: first, combinations of independent applications, and second, different states of a single application. Scenarios are dynamic since applications can be started and stopped independently, and a single application’s behaviour can depend on its inputs, on different stages in processing, and so on. In this paper we describe how the CompSOC platform offers system integrators and application writers the capability to implement multiple scenarios.

ABSTRACT. The pinched hysteresis loop area increasing with the square of the frequency of driving harmonic signal on the assumption of constant charge delivered within the half-period belongs to the less known fingerprints of ideal memristor. The paper proves that this fingerprint holds not only for the harmonic excitation: the v-i characteristic of a memristor driven by n-times accelerated and simultaneously n-times amplified signal of arbitrary waveform is a homothetic entity with respect to the original characteristic, with the homothetic center at the v-i origin and with the homothety ratio n. This rule holds for an arbitrary ideal memristor but not for an arbitrary general memristive element. Breaking this rule indicates reliably that the element analyzed is not an ideal memristor.

ABSTRACT. The phase equation of oscillators driven by signals at a frequency multiple of the free-running oscillation frequency is studied. This equation, describing the behavior of many injection locked circuits, extends the applicability of the well-known Adler’s equation, which is limited to forcing signals close to the free-running frequency. The exact solution of the phase equation in time domain is derived for pulling operation and its utility in the calculation of the frequency spectrum of the system response is shown with reference to a widely used divide-by-2 frequency divider. Finally, a comparison of the results obtained by presented formulas with the results obtained by numerical integration and by SPICE simulations based on BSIM3 models is presented.

ABSTRACT. Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This can happen for a range of constant and periodic inputs. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can produce spurs in the output spectrum. We call pseudorandom dithering effective if it breaks up periodic cycles in the modulator without producing its own spurs in the output spectrum. This paper presents rigorous mathematical analysis and a design methodology to achieve effective dithering.

ABSTRACT. Several physical and mathematical models have been proposed to describe all 2-terminal non-volatile memory devices based on resistance switching (i.e. memristors), regardless of the device material and physical operating mechanisms. A complete and precise classification of memristor, including memcapacitor and meminductors as well, is instrumental in matching model parameters to physical phenomena and in boosting applications of memristors in unconventional computing systems.

The aim of the paper is to provide a theoretical approach to the various classes of mem--devices (i.e. memristors, memcapacitors and meminductors) as nonlinear dynamical systems whose characteristic curves (i.e. dynamic characteristics) are pinched at the origin when driven by bipolar excitations. %Focusing on memristor, off-origin dynamic characteristics are discussed and mathematical criteria to model such devices are provided as well. This theory provides a practical tool to describe mem--devices developed for non--volatile memory applications and neuromorphic systems.

ABSTRACT. A class of memristor circuits is obtained by cascading a static nonlinear two-port with a dynamical one-port. These class of circuits can be split in two sub-classes which are current- and voltage-controlled, as real memristive elements. Since memristors are widely studied and the applications theorized exploiting this technology are getting more and more broader, circuital implementations that afford to obtain the same dynamics become properly relevant. This paper has the scope to present a possible implementation of these class of circuits which have been rendered and simulated on PSpice. The complex nonlinear dynamical behavior of the proposed circuit is investigated and the proof of concept hereby described gives further study and optimization possibilities in all the fields of the application.

ABSTRACT. A tutorial discussion of negative resistance oscillators based on simple RLC circuits is presented. Two cases are based on parallel RLC circuits and two cases are based on series RLC circuits. Distortion is minimized by introducing symmetry in the movement of the complex pole-pair of the small signal model.

ABSTRACT. We present a description in terms of phase and amplitude fluctuations for nonlinear oscillators subject to white Gaussian noise, described by Ito stochastic differential equations. The equations derived for the amplitude and the phase are rigorous, and their validity is not limited to the weak noise limit. We show that using Floquet's theory, a partial decoupling between the amplitude and the phase is obtained. The decoupling can be exploited to describe the oscillator's dynamics solely by the phase variable. The resulting phase reduced model is analyzed, and the asymptotic values of probability density function, auto-correlation matrix and power spectral density are found.

ABSTRACT. VCO-based ADC is an attractive candidate for the synthesis of all-digital ADCs using standard cells. However, the non-linearity of a synthesizable VCO appears in the converter transfer function, requiring digital post-processing to retrieve performance. An alternative solution is proposed in which the input analog signal is pre-coded into a delta-modulated pulse stream, which when used to drive a VCO-based converter, causes the oscillator to operate at two distinct frequencies thereby eliminating the VCO non-linearity from the converter transfer function. A circuit is proposed to implement the scheme, which consists of a synthesized digital block realizing all the active parts of the circuit and a passive RC net used as an integrator. Spectre simulation of the netlist synthesized using a 65~nm standard cell library shows that a performance of 8.2~bit ENOB over a 3~MHz bandwidth can be achieved without using any digital post-processing.

ABSTRACT. This paper presents a differential inverter-based switched-capacitor (SC) oscillator in 65 nm CMOS technology. The proposed SC oscillator is based on the continuous-time two-integrator oscillator, and the differential version is formed by the inverter-based pseudo-differential operational trans-conductance amplifier (OTA). By employing the inverter-based OTA in the SC oscillator, the power consumption can be reduced because inverters operate at the class-AB mode compared with traditional OTAs which operate at the class-A mode. The oscillating frequency can be tunable by changing the capacitor ratios. The SC oscillator can be applied as a frequency divider for the clock frequency, while it can be adopted as an oscillator at the lower frequency band which requires huge values of the inductor and the capacitor if the LC oscillator is employed. The oscillating frequency in this work is 4.2 MHz, the power consumption is 0.14 mW at a 0.7 V supply voltage, and the clock frequency for the switches is 100 MHz. Arrays of such oscillators may find use in analog image processing applications.

ABSTRACT. In this work, the temperature compensated frequency generating circuit is designed using a standard 0.18um CMOS technology. The architecture of the proposed circuit is based on the differential current controlled ring oscillator. The temperature independent frequency signal from the circuit has been obtained by using the principle of the reversal of the temperature behaviour with the supply voltage. In the temperature ranging from -40C to 85C this behaviour appeared at the supply voltage value of 1V+/-10 % during the measurement of eight prototypes. In this temperature range, with an average power consumption of 2.3uW the proposed circuit generates an average frequency of 355 KHz with the mean frequency inaccuracy of 1.53% with respect to the temperature.

ABSTRACT. Argo is a network-on-chip developed for use in a multi-core platform designed specifically for hard real-time applications and it supports message passing across virtual end-to-end channels. Argo implements these channels using time-division multiplexing (TDM) of the resources in the NOC following a static schedule. This requires some form of global synchrony across the platform. At the same time it is generally accepted that a large chip should employ some form of globally-asynchronous locally-synchronous (GALS) organization. By using asynchronous routers and by rethinking the microarchitecture of the network interfaces we have managed to combine TDM and GALS and obtain a very hardware-efficient implementation of the NOC. The paper gives a brief overview of the Argo NOC and focuses on two important issues: (i) timing analysis of the network of asynchronous routers and (ii) how to safely bring the NOC out of reset.

ABSTRACT. The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions. This constrains the silicon to operate at worst-case frequencies and at conservative supply voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed can suffer from multiple issues, including being susceptible to metastability and requiring often complex changes to the architecture to support replay-based recovery from timing errors. These problems respectively lead to circuit failures and/or incur high timing penalties when errors occur. This paper reviews a recently proposed asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. It also describes some open issues and new research opportunities this template presents, including automation problems to target average-case operation, specific circuit optimizations to minimize resiliency overhead, and the need for new test procedures to tune delay lines and screen out bad chips.

ABSTRACT. Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

ABSTRACT. Autonomous wireless sensor nodes are creating a great opportunity for non-volatile memories as, very often, those systems are recovering their energy from their surrounding environment. Those systems require low leakage and data back-up when the circuit is sporadically turned off. We propose, in this paper, volatile and non-volatile asynchronous circuits using UTBB FDSOI specificities to minimize leakage and read/write energy cost. This is done by efficiently coupling asynchronous design techniques based on activity detection, FDSOI back-biasing and MRAM C-Elements implementation. It is possible to use request/acknowledgment mechanism implemented in each asynchronous block of the circuit to automatically detect its activity and therefore locally reduce the leakage. We also demonstrate by mixed-signal simulations that Back Biasing mechanism can reduce the non-volatility energy cost by 30%.

ABSTRACT. Pausible clocking is an efficient means to establish communication between different timing domains without suffering from the risk of metastable upsets, as seen with synchronizer based solutions. On the downside, pausible clocks are usually ring-oscillator based and hence exhibit relatively bad accuracy and stability. In this paper we extend an existing solution to pausible clocking that allows to synchronize the ring oscillator to a high precision reference like a crystal clock. In the basic solution there is a 50% probability that when resuming the clock after a pause, it runs out of sync with the reference during a synchronization phase. Our extension decouples the communication interface in a suitable way, so as to avoid the need for synchronization by (a) allowing a data transfer without actually pausing the clock, and (b) carefully aligning the signal timings. This finally yields a clock source that combines the benefits of being stable like a crystal clock and allowing hazard-free pausing, like a ring-oscillator based pausible clock.

ABSTRACT. In this micropanel, the session organisers, Alex Yakovlev and Andrey Mokhov, will try to engage the speakers and the audience on speculation about the future of asynchronous circuits. The following questions will be posed and hopefully answered.

• What role will asynchronous circuits play in the technology revolution, in particular in the following hot topics: Internet of Things, big data, many-core processors, biomedical devices?
• What will be the key winning factors: low power, robustness, performance, modularity, design productivity, easier mixed signal integration?
• Or will they affect the quality of the final products: size, cost, ease of use, broader market?
• Finally, what are the low-hanging fruit in asynchronous circuits today that you would be ready to conquer given an Investor X happy to invest $1M in asynchronous design?

ABSTRACT. In this study, in order to demonstrate the versatility of the active building block so-called current differencing transconductance amplifier (CDTA), a current-mode (CM) frequency-agile filter (FAF) application is designed. The investigated 2nd-order class 1 CM FAF employing three CDTAs and two capacitors provides three basic filtering functions i.e. low-, band-, and high-pass. The band-pass filter was studied in details and by both regular and post-layout simulations performed using CADENCE Spectre tool with TSMC 0.18 µm level-49 CMOS technology process BSIM3v3 parameters. In addition, corner and Monte-Carlo analyses are given to prove the accuracy of centre frequency of the CM FAF.

ABSTRACT. This paper proposes an analytical design method for a class of two-dimensional recursive zero-phase filters with a shape specified in polar coordinates in the frequency plane. The design begins with a given 1D prototype filter, then a frequency transformation is applied, which leads to the 2D filter with a desired shape. For each specific filter the design consists in finding the appropriate frequency transformation, which uses the bilinear Z transform. Three types of 2D filters are designed as examples to the proposed method. The resulted filters are efficient, of low complexity and relatively high selectivity. Simulation results are provided for one type of filter, to show its capabilities in image filtering.

ABSTRACT. In this paper, a new passive RC circuit realization of voltage-mode (VM) first-order all-pass filter (APF) is presented. The proposed VM APF scheme is composed of a single grounded capacitor and three resistors. Main advantage of the circuit is the common ground terminal between the input and the output. For proper functionality passive element matching is required and one of passive components must be of negative resistance that is implemented with Arbel-Golminz operational transconductance amplifier. The theoretical results are verified by SPICE simulations, where PTM 90 nm level-7 CMOS process BSIM3v3 parameters were used.

ABSTRACT. In this paper, the impact of variations on the most representative CMOS differential flip-flops. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.

ABSTRACT. A closed form design of narrowest possible band-pass finite impulse response filters is presented. The underlaying generating polynomial has equiripple behaviour in two separate intervals. A novel degree equation is introduced. One example demonstrates the robustness of the design procedure.

ABSTRACT. Many subsystems in the brain require an estimate of neural activity to function properly. For example, models of neural homeostasis and synaptic plasticity incorporate these estimates. Here we present a method for estimating a neuromorphic neuron's firing rate using floating-gate transistors. This technology allows for the long time constants required for rate estimation and homeostatic plasticity. As a neuron fires, the floating-gate's terminals are modified such that the steady-state voltage on the floating-gate represents an estimate of the neuron's firing rate. The primary benefits of this scheme are low power consumption and compactness.

ABSTRACT. This paper presents an inverter-based low-power low-noise switched-capacitor variable gain amplifier (SC-VGA), and an 8-channel sample-and-hold (S/H) analog beamformer (ABF) for 2-6 MHz second harmonic cardiac ultrasound imaging probes. The sampling frequency is 40 MHz in both the SC-VGA and the ABF. The SC-VGA has 8-bit gain control and achieves the dB-in-linear gain range from -14 dB to 32 dB. To suppress the second harmonic distortion (HD2), the SC-VGA completes the single-ended to differential conversion. By using a 2D piezoelectric transducer (PZT) model as the signal source, the SC-VGA performs the signal-to-noise ratio (SNR) of 45.4 dB, HD2 of -50 dB at the output swing of 820 mVpp, and power consumption of 214 µW at a supply voltage of 0.9 V. An 8-channel pipelined S/H ABF based on the SC analog memory following the SC-VGAs can improve the SNR to 54 dB and the HD2 to -54.3 dB. Each channel in the ABF consists of eight SC analog memories, and the total delay is up to 200 ns with the resolution of 25 ns. The summation amplifier in the ABF is an inverter-based differential SC amplifier, and its power consumption is 228 µW at a 0.9 V supply voltage. The simulation is based on 0.18 µm CMOS technology.

ABSTRACT. Electronic devices for measuring body parameters in healthcare environments generally exhibit hygienic problems. Furthermore, they require regular battery replacement or recharging. This paper presents an electronic wristband for medical measurements that can be charged wirelessly. Its power supply is equipped with a Qi compatible inductive power receiver, an EDLC energy buffer and a series of voltage regulators that can be disconnected from the energy buffer by a microcontroller. Because the wireless power receiver was placed behind a display, a study was performed of the effects of the display on receiver coil characteristics and system performance. For the selection of the EDLC, a selection process is presented, making a trade-off between device autonomy and charging time. The result is a completely sealable and thus sterilizable device that can be charged in less than 5 seconds while being worn on the wrist.

ABSTRACT. An analog circuit, based on a negative impedance converter and a capacitor, for damping oscillations in an array of mean-field coupled neuronal FitzHugh–Nagumo (FHN) type oscillators is described. The circuit is essentially a two-terminal feedback controller. When coupled to an array of the FHN oscillators, it stabilizes their unstable steady states. Both, numerical simulations and hardware experiments with the analog electronic circuits have been performed. The results for an array, composed of three mean-field coupled FHN oscillators, are presented.

ABSTRACT. This paper investigates the potential of an image sensor that combines event-based asynchronous outputs with conventional integration of photocurrents. Pixels voltages can be read out following a traditional approach with a source follower and analog-to-digital converter. Furthermore, pixels have circuitry to implement Pulse Density Modulation (PDM) sending out pulses with a frequency that is proportional to the photocurrent. Both read-out approaches operate simultaneously. Their information is combined to render high dynamic range images. In this paper, we explain the new vision sensor concept and we develop a theoretical analysis of the expected performance in a standard AMS 0.18 um HV technology. Moreover, we provide a description of the vision sensor architecture and its main blocks.

ABSTRACT. Recently, several low and mid-level vision algorithms have been successfully demonstrated at high-frame rate on a low power-budget using compact programmable CPA (Cellular Processor Arrays) vision-chips that embed a Processing Element (PE) at each pixel. Because of the inherent constraint in the VLSI design of these devices, algorithms they run are limited to scarce resources, in particular memory -that is the number of registers available per pixel. In this work, we propose an algorithmic procedure to trade off the pixel resolution of a programmable CPA vision-chip against the number of its registers. By grouping pixels into "super-pixels" where pixel registers are interlaced, we virtually expose more registers in software allowing to run more sophisticated algorithms. We implement and demonstrate on an actual device an algorithm that could not have been executed on an existing CPA at full resolution due to its memory requirements.