ABSTRACT. Models of System-on-Chip (SoC) designs at the Electronic System Level (ESL) are commonly used as extensions to standard SoC design flows. Verification techniques for ESL descriptions have become available that can efficiently explore the system’s global behavior. Yet, in industrial practice, due to the wide “semantic gap” between ESL models and their implementation at the RTL, sign-off verification still largely relies on RTL as the point of reference. RTL chip-level simulations are unavoidable and often dominate design costs. The situation is aggravated by the shrinking scope of hardware verification in SoC design in general. A trend can be observed where certain SoC functions traditionally implemented in hardware (e.g., main control, bus communication, power management) are now shifted into the firmware. This calls for new verification methods which complement HW verification by analyzing the precise effects of firmware on the underlying hardware. While most techniques of software verification operate at a hardware-independent level this talk will elaborate on the possible merits of a hardware-dependent software view. It describes a computational model recently developed for hardware-dependent SW verification and its application in formal property checking and equivalence checking of firmware. These techniques, in combination with formal hardware verification, are envisioned to pave the way towards new design flows closing the semantic gap between ESL and RTL models and, thus, drastically reducing in design and verification costs. The talk will describe recent results and new practices already explored in industrial case studies.

ABSTRACT. MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross- coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezo- electric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

ABSTRACT. We investigate the effects of fluidic damping on packaged energy harvesters using numerical simulations in COMSOL Multiphysics. In particular, we compare two models for including squeeze film damping in the case the harvester is operating close to a wall; an equivalent mass damping based on approximate modal coefficients and the numerical solution of the Reynolds equation in the air gap between the wall and the structure. The models are evaluated on a bridge design harvester intended for automotive applications.

ABSTRACT. This paper combines both the well-known power transfer and electromechanical coupling analogy theories for calculating the electrical power output of d33-based piezoelectric harvesters. The proposed methodology utilized the direct mechanical-to-electrical analogy, electromagnetic and power system theories to develop analytical models to compute the power output taking into account the dimensions and material properties of the piezoelectric generator. The developed method has been experimentally validated and it was found that the current technique provides significant additional information that crucial for enhancing the device design and operation in a straightforward manner when compared to other conventional reported methods.

ABSTRACT. Drivers for 3D packaging solutions are manifold and each requirement calls for different answers and technologies. Main goal is miniaturization, but component density and performance, simplification of design and assembly, flexibility, functionality and finally, cost and time-to-market have been found to be the core drivers for going 3D as well. Besides die and package stacking and folded packages, embedding dies is a key technology for heterogeneous system integration. Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics for heterogeneous system integration. Mold embedding for this technology is currently done on wafer level up to 12”/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18”x24” or even larger. Already today PCB technologies offer the potential for large area panel packaging up to 24”x18”/610 x 457 mm² and can be applied to form a redistribution layer [RDL] for large area reconfigured wafers or panels, replacing thin film redistribution. In summary this paper describes the technological path from wafer level embedding to 24”x18” fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as autonomous sensor nodes, packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.

ABSTRACT. This paper introduces an all-digital; CMOS zero current switching (ZCS) circuit that enables a wide dynamic and a fine resolution zero current detection range for high gain (50mv input to 1.35v output) inductor-based DC-DC converter. Using only a 3-bit design, more than 1.5 μs dynamic range with 50 ns delay resolution is achieved. The prototype chip is designed and simulated using 65 nm low-power CMOS technology and occupies less than 0.04 mm2 area. Post-layout SPICE simulation results confirm that 85% efficiency can be achieved for the overall system. The proposed circuit is part of a system that targets energy harvesting from human body thermal energy to enable long lifetime for wearable and biomedical devices.

ABSTRACT. In the proposed low-jitter delay locked loop (DLL), the analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve the problem of achieving small loop gains and mirroring small currents. Also, the problem of leakage currents during the lock state is removed when DAC provides a fixed analog voltage based on the ACC’s output digital code. A simple lock detector is utilized to deactivate ACC and to generate a fixed control voltage for delay elements when the loop locks. Another loop is also applied to dynamically control loop-gain and lock time. Loop-Gain decreases (increases) when DLL moves toward (away from) the lock condition to not only guarantee the loop stability but, provide a fast lock time. Smaller jitter is expected on the generated phases comparing to the analog CPs. Here, a fixed control voltage is provided by DAC and the leakage currents cannot affect the control voltage. RMS jitter of less than 33.5ps and 1.6ps are achieved at 20MHz and 625MHz operating frequencies, respectively. Lock time is reduced from 38µs to 2µs at 20MHz and also from 900ns to 45ns at 600MHz where loop-gain is multiplied by 16, 8 and 4 for out of lock region. Total power consumption is 7.85mW at 1.8V supply voltage in a 0.18µm CMOS process.

ABSTRACT. The paper presents a continuous-time (CT) Delta-Sigma analog-to-digital converter (ADC) using a current output digital-to-analog converter (DAC) for the feedback. From circuit analysis it is shown that using a current output DAC makes it possible to relax the noise requirements of the 1st integrator of the loopfilter, and thereby reduce the current consumption. Furthermore, the noise of the current output DAC being dependent on the ADC input signal level, enabling a dynamic range that is larger than the peak signal-to-noise ratio (SNR). The current output DAC is used in a 3rd order multibit CT Delta-Sigma ADC for audio applications, designed in a 0.18 um CMOS process, with active-RC integrators, a 7-level Flash ADC quantizer and current output DAC for the feedback. From simulations the ADC achieves a dynamic range of 95.0 dB in the audio band, with a current consumption of 284 uA for a 1.7 V supply voltage; the resulting figure-of-merit is 262 fJ/conversion.

ABSTRACT. This paper present the high resolution time-todigital converter(TDC) using the new delay time measurement circuit. To generate tick mark on the time axis, the coupled oscillator, ORIGAMI, is used for precise scale marks. The minimal scale mark of the proposed method is ticked by the multiphase oscillator ORIGAMI, then the high resolution T-to-D conversion can be realized. The proposed TDC output is coded by the specific code, which is called as the center of gravity code, CGC. The CGC to binary decoding scheme is also discussed. To verify the proposed TDC performance, SPECTRE simulation results are shown, where 0.18 μm 1-poly 4-metal CMOS process is used.

ABSTRACT. Bangap voltage references (BGRs) are widely used in today’s circuits as references with a low temperature coefficient. Especially measurement circuits and metering applications demand a very low temperature coefficient to maintain the desired precision over the entire temperature range. Today’s BGR designs use analog circuits to correct for the effects which lead to a temperature drift. In this paper a bandgap reference voltage which uses a digital correction technique is presented. The proposed design includes a temperature sensor to measure the current chip temperature and a bandgap reference which is controllable by a 3-bit digital input. The input to the bandgap block is calculated using a digital correction algorithm. The proposed design was implemented in a 0.35μm CMOS process and occupies 0.437 mm2. After calibration, a 3σ temperature coefficient of 3.8 ppm/K is achieved over a temperature range from −40 °C to 100 °C. With the proposed design, high performance measurements over a large temperature range have become possible. The digital design allows for an easy adaptation to various needs and temperature coefficients.

ABSTRACT. This paper presents a method to synthesize the noise transfer function (NTF) for tunable bandpass delta-sigma modulators, where the quantization noise stopband can be programmed over the whole Nyquist range. Instead of relying on traditional filter design theory, the proposed method allows to create NTFs of arbitrary order by directly placing the zeros and poles on the z-plane. The advantage is that the NTF can be re-calculated for each center frequency by using simple closed form expressions, thus avoiding the need of large lookup tables to store multiple pre-computed coefficient sets. Extensive system-level simulations show that our method yields equal performance as the Chebyshev-II design method. As an example, the synthesis of a binary 12th-order tunable bandpass delta-sigma modulator is demonstrated, and its stability is proven for any choice of the center frequency.

ABSTRACT. This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28~nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28~nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6~dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70~dB, unity-gain frequency = 4.3~MHz and phase margin = 68$^\circ$ while consuming 2.9~$\mu$W with a $V_{DD}$ = 1~V. A high linearity $>$ 12~bits without the use of degeneration resistors and a settling time of 5.8~$\mu$s (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [$-$20$^\circ$C $+$85$^\circ$C].

ABSTRACT. This paper presents a current sense amplifier (CSA) capable of performing measurements at high input common mode (CM) voltages independent of the power supply rail. The proposed circuit employs a fully low voltage amplifier cell, a correction block for maintaining the linearity of the input stage over the entire input CM and a protection circuit against high differential input voltages (DIFF). Furthermore, a trimming procedure that enables the use of typical polysilicon gain resistors without losing accuracy and precision is discussed. The proposed architecture has been implemented in a standard 0.25µm BCD technology and its performances have been confirmed by both simulations and measurements.

ABSTRACT. This paper presents the design of an op-amp free voltage reference generator which utilizes a pulse width regulated loop. The proposed voltage reference circuit has been designed and simulated in a standard 0.18-um CMOS technology. Post layout simulation results show that it is capable of operating with supply voltages down to 0.7 V while generating an output voltage of 202 mV. The achieved temperature coefficient is 54 ppm/°C for temperatures ranging from 0 to 100°C. The simulated power consumption at the room temperature is 400 nW.

ABSTRACT. When a current-mode approach is exploited to read-out high-gain photodetectors, preamplifiers with input resistance as low as possible and very large bandwidth are commonly used to optimize the time resolution of the detection system. In our study we show that, due to the effects of the parasitic inductance associated with the interconnection between the detector and the front-end electronics, extremely low input resistance and very large bandwidth are not optimal design choices, as commonly assumed. To support the study, we refer as an example to a detection system based on a Photo-Multiplier Tube read-out by a simple BJT common base current buffer and demonstrate by simulation the existence of values of input resistance and bandwidth which optimize the timing accuracy of the system.

ABSTRACT. Deployment of automated traffic surveillance systems play an important role in traffic law enforcement. Existing devices use RADAR or LIDAR technologies for speed measurement, as well as cameras for license plate recognition. It would be profitable to replace those relatively expensive active systems with a single camera for both tasks. An optical based vehicle speed measurement method is presented in this paper. The proposed method calculates speed estimates based on a single, superimposed frame, which contains information of the movement of certain objects during exposure, and can be obtained through modified shutter control. An applicable sensor structure and exposure-control are also shown, as well as some experimental results.

ABSTRACT. A compensation technique for low-power high-capacitive-load three-stage operational transconductance amplifiers is presented in this paper. The compensation network is made of passive components only and, as an example, the proposed technique was used to design a three-stage amplifier in a standard CMOS 65-nm technology. The amplifier achieves a 2.64-MHz gain-bandwidth product when driving a 1-nF capacitance by consuming only 155 uW from a 2.5-V supply. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over previously reported solutions.

ABSTRACT. Hybrid DC-DC regulators are structures that combine both a linear voltage regulator and a switching DC-DC converter. The main objective of this hybrid topology is to converge, in a single circuit topology, the best of both alternatives: One the one hand, obtaining small voltage output ripple, which is typical of linear regulator structures, and, on the other, achieving good energy efficiency, as in switching alternatives. While the linear regulator fixes the required output voltage to a fixed value with negligible steady-state ripple without the necessity of an output capacitor, the switching converter is devoted to drive most of the load current. In addition, the linear one supplies the required current when the load changes at transient intervals. Current paper deals with the design of an on-chip hybrid converter for low output currents. The design has been designed and tested with simulations using a standard 180 nm CMOS technology. The simulation results presented in the paper shows suitable performance of the design.

ABSTRACT. Energy harvesting techniques have been developed more than a decade and received much attention in realizing long-term energy autonomous microsystems. Many converter topologies and circuit techniques have been reported to effectively convert the harvested energy to usable outputs. In this paper, an overview of major green energy sources as well as the equivalent circuits are presented. In addition, maximum power point tracking (MPPT) technique and power conversion topologies are also included.

ABSTRACT. With the emergence of nanoscale material-based energy harvesters such as thermoelectric generator and microbial fuel cells, energy-harvesting-assisted self-powered electronics systems are gaining popularity. The state-of-the-art low-voltage CMOS boost converter, a critical voltage converter circuit for low power energy harvesting sources will be reviewed in this paper. Fundamentals of the boost converter circuit start-up problem are discussed and recent circuit solutions to solve this problem are compared and analyzed. Necessary design considerations and trade-offs regarding circuit topology, component and CMOS process are also addressed.

ABSTRACT. Analytical theory and simulation-based analysis for optimizing sensitivity of RF energy harvester are discussed. A target harvester is a widely-used MOSFET Dickson charge- pump harvester from a small-signal RF power with a voltage booster at the front end. Charging time is also analyzed. Derived expressions show good match with simulation results. The results provide an insight for design optimization based on circuit and device parameters.

ABSTRACT. A 100-MHz radio-frequency energy harvester is designed and implemented for passively powered devices. The proposed design achieves high power conversion efficiency over wide input power range by adjusting the effective loading and setting the rectifier's output voltage adaptively. Reconfigurable structure further extends the operating range. As a self-contained energy harvester, the sensitivity is simulated to be -23 dBm which supplies an output voltage of 1 V over a 1-Mohm load. More than 30% of power conversion efficiency can be achieved for input available power from -20 to 0 dBm.

ABSTRACT. This work presents an innovative bendable module for solar-energy harvesting. The module consists of a mechanically flexible organic photovoltaic device (OPV), a rechargeable battery, and an a-IGZO TFT charge-control circuit. The total thickness of the module is 1.1 mm. We present measurements of hardware implementations and simulations. On this basis, voltage converter schemes based on a charge pump in the flexible a-IGZO TFT technology are explored, to enhance the range of operation of the module, particularly under low-light conditions. All investigations and data are presented with focus on two variants of the energy harvesting module that differ in nominal output voltage and capacity: a 6 V variant with capacity of 14.4 mAh and a 24 V variant with capacity of 5.5 mAh. Under exposure to 1 sun, both can be charged in less than 4 hours.

ABSTRACT. The quality of RF N-path filtering is limited by the performance of the involved multiphase clock. The paper presents analysis of critical clock imperfections. The phase imbalance that gives rise to an extra image band located at second harmonic frequency is analyzed by a linear periodically varying (LPV) model of a 4-path filter where the respective rejection ratio is estimated and verified by simulation. We also analyze the clock phase noise and devise that the reciprocal mixing is not diminished by the attained blocker rejection, however, in this case one can benefit from band limitation by the output capacitance of the driving transconductance amplifier (LNTA). The analysis is supported by simulation results.

ABSTRACT. This paper presents a procedure for creating a small signal parameterized circuit model of an two-port RF module (an amplifier in the case study) characterized in frequency domain. The black-box electrical circuit model is created using Vector Fitting routines and parameterized by circuit operating conditions. Generated model is useful for the analysis of various high-frequency electronic circuits using commonly available generic circuit simulation tools from SPICE family. The paper is focused on the case study of an RF amplifier model, used to illustrate both model generation as well as its usefulness in SPICE simulator.

ABSTRACT. Harmonic balance suffers of the main drawback of requiring prohibitive numerical resources when the simulated circuit leads to waveforms with very sharp variations, since a large number of harmonics has to be used. The main reason is due to the fact that the numerical effort increases as a polynomial function of the number of harmonics. This drawback can be mitigated if peculiar solvers that need to neither store nor LU-factorise the Jacobian matrix related to the harmonic balance problem are used (e.g., gmres). Another approach is to adopt oversampling, i.e. still "well"evaluating the characteristics of the highly nonlinear devices while using a limited number of harmonics. This aspect is investigated in this paper and, by showing how the harmonic balance is a peculiar version of the more general Galerkin's method, a new version of the latter is introduced that potentially lowers the problem dimensionality. Furthermore it allows us to rigorously introduce and describe an oversampling technique that aids convergence by pushing aliasing effects to the high frequency portion of the spectrum. Its effectiveness is shown through a test circuit and numerical simulations.

ABSTRACT. This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40-nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

ABSTRACT. An estimation method for the S-parameters of 4-port connection circuits that is connecting 2-port device to its one end is presented with a novel algorithm to improve the estimation accuracy. To obtain the 4-port S-parameters for the connection circuit are estimated using indirect measurements. That is, several known loads are connected to the 2 ports at the far end of the connection circuit in turn and the reflection and transmission characteristics among the near end 2 ports of the connection circuit are measured. The estimation method is constructed in the framework of linear algebra that eliminates the needs to solve nonlinear equations numerically, which enables application of theoretical analysis. This method can be applied to obtain the S-parameters of the 2-port device connected at the far end of the connection circuit by de-embedding the estimated 4-port connection S-parameters.

ABSTRACT. When using standard multi-$V_{t}$ CMOS processes to build logic gates, often for example Low-$V_{t}$ (LVT), or Standard-$V_{t}$ (SVT) or High-$V_{t}$ (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR circuit. We show, to the contrary, how a combination of different types within a single logic circuit, may be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short Channel Effects (RCSE) are combined by using non-minimum gate lengths for increased robustness agains process variations. Also, a recently proposed technique using very regular layouts accompanying the above mentioned techniques in a 16-bit adder implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of the adder for a voltage range of 119 mV to 350 mV. Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12 $\%$ while at the same time reducing probability of failure by up to several orders of magnitude and reducing energy per operation slightly, when compared to conventional design methods using minimum, or relatively short, gate lengths.

ABSTRACT. This paper presents the design, implementation and characterization of an integrated power efficient cascode amplifier in a flexible a-IGZO thin-film transistors (TFTs) with minimum channel lengths of 25 µm. The circuit consists of a two-stage cascode amplifier for the audio baseband amplification and a source-follower as a buffer to drive printed loudspeakers. The proposed amplifier is fabricated on a 50 µm-thick flexible polyimide foil, and characterized with a 20 V dc supply voltage (VDD) and an output load capacitance of 15 pF. The measured voltage gain exceeds 15 dB from 4.5 kHz to 15 dB at 25 kHz. The measured 3 dB bandwidth of the unloaded audio amplifier spans from 2.2 kHz to 60 kHz. The amplifier consumes a dc power of 40 mW and delivers 10 dBV of output signal at the 1 dB compression point; this is sufficient to drive printed piezoelectric loudspeakers. The simulated frequency response of the loaded amplifier shows that the amplifier can drive a wide range of capacitive loads from 15 pF to 500 nF. The simulated 3 dB bandwidth of the amplifier loaded with the printed loudspeaker is 29 kHz.

ABSTRACT. Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

ABSTRACT. A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-µm BCD process to improve latchup immunity.

ABSTRACT. This paper describes the development of a 65nm standard cell library designed for building highly energy-efficient digital circuits. In total 43 logic cells and 19 special cells for clocktree synthesis and place and route purposes are implemented using a commercial 65nm bulk technology. As a result fullchip implementation of low-power systems operating at ultra-low voltage is feasible. The benefits of this subthreshold cell design are demonstrated by synthesis and analysis of a sample circuit for supply voltages from 250mV to 1.2V. Power analysis at gatelevel shows an improvement in energy consumption by a factor of 9.25 with a total energy consumption of 11.7 pJ per clock cycle in the subthreshold domain.