ABSTRACT. Hardware Trojans (HTs) are identified as an emerging threat for the integrity of Integrated Circuits (ICs) and their applications. Attackers attempt to maliciously manipulate the functionality of ICs by inserting HTs, potentially causing disastrous effects (Denial of Service, sensitive information leakage, etc.). Over the last 10 years, various methods have been proposed in literature to circumvent HTs. This article introduces the general context of HTs and summarizes the recent advances in HT detection from a French funded research project named HOMERE. Some of these results will be detailed in the related special session.

ABSTRACT. In this paper, we present how SEMBA, a fast invasive technique for white team Hardware Trojan detection, has been used to differentiate between a maliciously infected integrated circuit and a genuine one. Our methodology is based on the observation of the component’s hardware structure and includes the use of wet etching, Scanning Electron Microscopy and Multiple Image Alignment. Once the Integrated Circuits’ image have been fully reconstructed, image processing allows to detect the presence of the Hardware Trojan (HT). SEMBA is a fully automated approach with a 100% success rate, detecting any ‘transistor-size’ HTs and requiring ‘affordable’ resources and time.

ABSTRACT. Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention techniques through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.

ABSTRACT. Block codes have been shown to be a tool to thwart hardware trojan horses. The state of the electronic circuits is encoded thanks to a pair of complementary codes: one code prevents a purported hardware trojan horses from triggering, while the other one detects any kind of payload.

The feasibility and the actual implementation of such defense has be presented thanks to LCD (Linear Complementary Dual) codes and to LCP (Linear Complementary Pair) of codes. In this paper, we optimize the representation of such codes in order to reduce the hardware overhead of the countermeasure.

ABSTRACT. Nowadays, Hardware Trojans (HTs) become a real threat because of IC design and fabrication outsourcing trend. In the state of the art, many efforts were devoted to counter this threat, especially at netlist level. However, some clever HTs are actually a combination between a hardware and a software vulnerability, which, together, allow an exploitation. In this paper, we intend to detect such advanced HT, by resorting to a run-time detection. This method consists in identifying some high-level and critical behavioral invariants, and by checking them during the circuit operation. The assertion and Property Specification Language (PSL) is used to describe the properties to be checked. Then, a Hardware Property Checker (HPC) is created and integrated in the IC in order to verify these properties in run-time. We discuss how to define the critical properties for HPC. We also explain how this method is complementary with others, especially how the Hardware Checker can itself be protected against a tampering attempt.

ABSTRACT. Joint measurement of stochastic parameters of a low noise amplifier (LNA), based on output power measurement for input termination impedances is considered. As an advantage of this method the noise parameters can be determined in a quick way for narrow and broad band applications without special equipment. Knowing the noise parameters helps the user designing both matching networks for given low noise amplifiers and optimizing amplifiers. Four real parameters characterize the amplifier with the noise figure as function of the matching network. About ten different values for input termination impedances also provide an estimation of sensitivity and accuracy of this new method.

ABSTRACT. This paper discusses different approaches to improve the settling behavior of phase lock loops (PLL). Starting with a state-of-the-art PLL, a structure with an additional dynamic changing Loop-Filter and another structure with feed forward control are proposed. The main point of this paper is the adaption of modern control theory in the design of PLL systems to improve the behavior in case of a changing dividing factor and thereby the output frequency. For both structures, advantages and disadvantages are discussed and then the block diagram of the two approaches are presented. Both methods are compared to the state-of-the-art by simulations in MatLab Simulink. Therefore a massive changing output frequency of the PLL and the corresponding time for locking to the new output frequency is analyzed. All in all both novel PLL concepts offer a reduced settling time with respect to a specified change of the PLL output frequency.

ABSTRACT. An efficient algorithm is proposed for finding all DC solutions of nonlinear circuits using linear programming. This algorithm is based on a simple test (termed the LP test) for nonexistence of a solution to a system of nonlinear equations in a given region. In the conventional LP test, the system of nonlinear equations is transformed into a linear programming problem by surrounding component nonlinear functions by rectangles. Then, the emptiness or nonemptiness of the feasible region is checked by the dual simplex method. In this paper, we propose a new LP test algorithm using both rectangles and parallelograms, and shows that the proposed algorithm is more efficient than the conventional algorithms using rectangles only or parallelograms only.

ABSTRACT. Abstract—The paper proposes a new approach to improve the performance of multiphase switched capacitor converters (SCC). It is based on the use of redundant SCC topologies, which are switched forward and backward. The performance is improved by increasing the efficiency and simultaneous reducing the output current ripple. The SCC is considered as an analog computer that solves the system of linear equations by an iterative method. The SCC output voltage is assumed to be constant. This means that the corresponding system has no solution. It is shown that under this condition, the SCC operating in the no-charge mode solves the system by a least-squares method. This allows finding the average current in each SCC topology and consequently, an analytical expression for the equivalent resistance. The obtained theoretical results agree well with the results of simulations.

ABSTRACT. Capacitive body coupled communication (BCC) channel has been modeled as a two-port complex path impedance matrix [Z] which varies as a function of ten different body positions over the frequency range of 1 MHz to 60 MHz. A systematic numerical simulation methodology has been used to estimate [Z] parameters. The estimated complex path impedance [Z] is a symmetric matrix showing BCC channel is a reciprocal network of passive components for given coupler configuration, body positions and frequency range. The estimated complex path impedance has been utilized to determine either input impedance Zin or output impedance Zout to conjugately match to Zs at transmitter or ZL at receiver, respectively for maximum power transfer. It has been found that the resistive matching below 1000 Ω and inductive matching between 0.5 μH to 5 μH on any side of the two ports can meet the conjugate matching requirements for maximum power transfer for the given body positions and frequency range.

ABSTRACT. Memristor as an emerging history dependent nanometer scaled element will play an important role in future nanoelectronic computing technologies. Some pure and hybrid memristor-based implementation techniques have been proposed in recent years. Material implication logic is one of the significant areas for memristor-based logic implementation. In this paper a memristor-based linear feedback shift register is implemented based on material implication logic. It is implemented by 8 memristors which is considerably used less area in comparison with conventional CMOS-based peers. Also the proposed memristor-based LFSR circuit needs 55 computational steps for generating a 4-bits number.

ABSTRACT. One of the most promising emerging technologies is based on the use of memristive devices. Although capable of implementing certain type of logic circuits, they are being extensively used for memory applications. Beside memristor advantages such as high scalability, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. In this work we propose an implementation of a proactive reconfiguration strategy alongside a testing procedure to detect the weakest memory cells inside the crossbar. Such a realization can extend the crossbar lifetime with spare components and avoid memory cell failures.

ABSTRACT. This paper presents a procedure for the determination of the dimensionality of the state space of a memristive device. The state space dimensionality of a device corresponds to the minimum number of time delayed values/derivatives of the voltage and current required to represent the device dynamics for a specified set of inputs. The algorithm is based on the observed time domain voltage-current (i.e. input-output) data which is obtained by measurement. The determination of the state space dimensionality is important to achieve a single-valued input-output multivariate mapping between the device outputs as a function of the state variables. In this paper, this will be accomplished using an embedding technique, based on the false nearest neighbor principle.

ABSTRACT. This paper proposes the usage harmonic balance method to find the steady state solution on memristive devices and circuits. Harmonic balance is a well-established simulation tool often used to find the periodic steady state solution of circuits involving non-linear elements. It is a particularly efficient method when the focus is on the characterization of the frequency-domain behavior of some quantity in the circuit. This important characteristic arises due to the nature of the mathematical procedures involved, which operate directly on the frequency domain. One such example, is the problem of simulating the frequency behavior of the hysteresis loop area of a memristive device. In this paper, we describe the preliminary analysis involved in harmonic balance simulation and how it applies to the characterization of a memristive device. Simulation results at the end of the paper disclose important considerations on the accuracy of the method and its efficiency when compared to standard time domain methods.

ABSTRACT. Neurosurgery relies strongly on medical imaging techniques. However, many state-of-the-art diagnostic tools such as computer tomography (CT) and magneto-resonance imaging(MRI) cannot be applied during ongoing surgery in general. Our aim is to realize a multi-purpose imaging platform capable of real-time assistance to the surgeon. Therefore, we apply thermography: a non-invasive, contactless, marker-free technique that has been used in various medical applications, albeit some challenges remain. In this paper, we propose a Cellular Nonlinear Network -based image pre-processing for feature enhancing and extraction followed by a cepstrum-based motion correction algorithm allowing a real-time removal of breathing artifacts from thermographic images

ABSTRACT. This work presents techniques for an accurate numerical simulation of memristor models. In physics-based models of extended memristors under indirect excitation, the solution of the state equations is constrained to lie on specific manifolds at all times. A possible algorithm for the determination of numerical solutions to the algebraic differential equation set typical of these systems consists of augmenting the state vector with a novel variable which is invariant on the manifold. Solving the resulting ordinary differential equation problem simplifies the simulation since the algebraic constraint is embedded into the state equations. Regarding mathematical descriptions of generic memristors, where the state may only lie within a closed set, a procedure identifying each undesired event where the state either exceeds the upper bound or goes below the lower one, stopping the current simulation, starting a new one with initial condition set to the violated limit, and finally concatenating the time series of the various simulation sections, ensures a wellbehaved simulation run, and, consequently, a reliable numerical solution. Examples from a number of case studies demonstrate that the adoption of the proposed techniques prevents possible issues emerging in classical numerical integration methodologies, resulting in well-behaved state solutions, thus allowing a meaningful exploration of the full potential of memristors in electronic circuit design.

ABSTRACT. Piezoelectrical material with heterogeneities of nano-inclusions is considered in the case when it is subjected to time harmonic electro-mechanical load. The model is defined by the system of two partial differential equations and the boundary conditions for the generalized stress. On the exterior boundary, boundary conditions prescribe traction on the part of the boundary and prescribe displacement on the complemented part. We construct Cellular Nonlinear/Nanoscale Network (CNN) architecture for the boundary value problem. The dynamics of the obtained CNN model is studied via harmonic balance method. Traveling wave solutions are obtained numerically. The simulations are provided which illustrate the theoretical results. The obtained results are applicable in the field of non-destructive testing and fracture mechanics of multi-functional materials and structural elements based on them.

ABSTRACT. he current strategy to incorporate Graphical Pro- cessing Units (GPU) in the LHCb trigger system, with a view on the upgrade of the detector, is presented. Two main aspects are described: the strategy to fit GPUs in the current software framework and the performance of a particular algorithm.

ABSTRACT. In this paper we consider consecutive systems as a good match for certain nano-architectures, as nanoscale communications need schemes allowing for lower transmission bit error rates. In fact, nano-technologies like, e.g., molecular, nano-fluidic, nano-magnetic (even FinFET), can be mapped onto consecutive systems. We shall start by mentioning previous results for 1D (one dimensional) linear consecutive-k-out-of-n:F systems, before focusing on 2D ones. After introducing the 2D consecutive systems and some variations, the paper will present bounds for estimating their reliability. Simulation results for particular 2D cases will show that some of the bounds are in fact exact (for the particular cases considered). Conclusions and future directions of research will end the paper.

ABSTRACT. In this paper, we present a very low jitter reconfigurable shunt capacitor Vernier delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52pS/step, 17.5pS/step and 4.5pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600MHz. Incremental control steps can be configured in less than 1nS. Long time additive jitter is measured as 2.3pS.

ABSTRACT. This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

ABSTRACT. In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that Cholesky or LDL$^\intercal$ decomposition combined with equation system solving are the most promising algorithms for fixed point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.

ABSTRACT. Three-dimensional integration is a promising technology that can mitigate the deleterious effects of the increased interconnect length in modern ICs by vertically stacking dies. Through silicon vias (TSVs) and AC coupling have been proposed as communication interfaces between multiple stacked dies. This paper investigates these two communication schemes for 3-D systems where the link bandwidth is treated as a constraint rather than an objective. A frequency dependent RC model for the TSV and the redistribution layer is employed. A first order delay analysis between the two schemes shows comparable performance, but a better area efficiency for the TSV. Considering, however, a multiplexing scheme shows that TSVs with a pitch lower than 20 μm exhibit better bandwidth-to-area efficiency without multiplexing, while the inductive link demonstrates higher bandwidth-to-area efficiency ratio in comparison to TSVs with a pitch larger than 20 μm for a 12 : 1 multiplexing scheme.

ABSTRACT. To reduce layout design time, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Therefore, this paper presents the first knowledge-based layout synthesis methodology to generate new layouts by integrating existent design expertise contained in the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology with knowledge mining can achieve high layout reusage rate and hence the designers' layout preference can be successfully reserved.

ABSTRACT. This paper presents preliminary results of a statistical analysis of the SNM of an inverter (the basic element of any SRAM bit cell). These are statistical meaningful, and will be compared with results obtained using Monte Carlo, and should lead to more accurate, faster, and better yield estimates.

ABSTRACT. Realistic estimation of path loss is vital for designing an effective capacitive body-coupled communication system. The estimation based on simplified analytical models, however, results in errors of several orders of magnitude. The proposed efficient full-wave electromagnetic (EM) model takes into account the effect of capacitive coupler, electro-physiological properties of tissues in human body and environment all together to realistically predict the path loss. A comparison of both approaches is made in this paper, showing the superior performance of the proposed model.

ABSTRACT. The paper deals with a method for determining confidence intervals of stochastic responses at multiconductor transmission line (MTL) models with stochastic excitations. It is based on the theory of stochastic differential equations (SDE), namely a linear SDE with the additive noise is formulated to describe the system responses. In place of previous approach in which the moments of stochastic processes were calculated via sample statistics of the sets of individual stochastic trajectories, herein, respective variances are calculated leading to substantial acceleration of the solution. To enable it, differential equations for obtaining first two moments of the stochastic responses are formulated and solved. The verification is done by comparing with the above stated approach, while the Student’s t-distribution is utilized for calculating confidence intervals due to the additive noise considered. The simulation results have been obtained by means of the Matlab language.

ABSTRACT. In this paper an algorithm for distant aircraft detection for visual sense-and-avoid for UAV is presented. The algorithm uses local edge density to partition the frame into two types of regions. The first type is the unstructured or homogeneous part like sky region and the second part where there is a structured background, like high contrast clouds or terrain regions. The airplanes are detected on the two types of regions with different strategies. The algorithm was planned to run in an embedded environment with low power consumption, thus it can be run onboard of a small or mid-size UAV. First steps towards the GPU implementation on the nVidia Jeston TK1 development board are done and also presented in the paper.

ABSTRACT. In this study, a low-voltage design of a new general floating element simulator circuit for realizing floating frequency dependent negative resistor (FDNR), floating inductor (FI), floating capacitor (FC), and floating resistor (FR) simulator, depending on the selection of passive circuit elements, is described. The circuit employs two voltage differencing current conveyors (VDCCs) at low voltage levels (±0.45 V) and three passive components. It does not require any passive element matching. Moreover, the new general floating element simulator can be electronically controllable by changing the bias currents of the VDCCs or can be controlled through the grounded resistor or capacitors. Finally, using one of the described floating element simulator, i.e. FDNR, a fourth-order Butterworth characteristic band-pass filter is simulated via PSPICE using 90 nm, level 7 PTM CMOS technology parameters. The simulations agree with the theoretical analysis.

ABSTRACT. The most challenging step of implementing particle filtering is the resampling step which replicates particles with large weights and discards those with small weights. In this paper, we propose a generic architecture for resampling which uses double multipliers to avoid normalization divisions and make the architecture equally efficient for non-powers-of-two number of particles. Furthermore, the complexity of resampling is greatly affected by the size of memories used to store weights. We illustrate that by online storing the original weights instead of their cumulative sum and calculating them online reduces the total complexity, in terms of area, ranging from 0.56% to 37%, while giving up to 50% reduction in memory usage.

ABSTRACT. Four different flip-flops dimensioned for subthreshold operation has been designed and implemented in layouts. The four full custom, race-free, D-flip-flop were implemented in a standard 65 nm CMOS process and verified by measurements, when used in 2 divide-by-3 circuits. The first frequency divider, using standard topologies, demonstrated functionality down to a supply voltage of 132 mV, while the second variant, based on a recently proposed ”‘slice-based”’ approach, was functional for a supply voltage down to 137 mV. Frequency dividers using traditional 4-transistor NAND and NOR topologies, had lower energy per operation than the alternative 8-transistor NAND and NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V, a static flip-flop using 8-transistor NOR- gates plus one inverter, had the lowest static power consumption among the 4 flip-flops.

ABSTRACT. In this paper, a fundamentally new approach to computer-aided design and simulation of electrical circuits based on a use of λ-calculus for circuit device model representation and dynamic sizeable containers for sparse matrix simulation indexation indices is presented. This approach differs from traditional procedure where the entire simulation was performed over the matrix or matrix system assembled by modified nodal analysis (MNA). Turning device model definitions using λ-calculus to functionals allowed to reduce an effort required for their specification and opened new possibilities for simulation evaluation. Considering MNA matrix as second-order tensor system holding the functional definition of original sparse matrix entries allows to imagine these dependencies as chains with respect to a model definition and global dependencies between their defining inner functions. In this particular case, standard indexing methods would be a waste of memory during a computation, this problem occurs when huge sparse matrices enter the simulation. Therefore, new optimized indexing technique for non-zero matrix entries and variable size container types for those indexation vectors is proposed.

ABSTRACT. An all-digital delay locked loop (DLL) for use in an analog video front end (AFE) is presented. The DLL is designed for a wide input frequency range of 40-300 MHz to cater to a range of different video standards currently in use. The proposed DLL has a closed loop architecture that tracks PVT variations and locks to the input signal in a maximum of nine clock cycles. At its output, the DLL generates 32 uniformly distributed phases of the input clock to provide an optimal sampling point for the analog to digital conversion of the input signal in the AFE.

ABSTRACT. A Global Sensitivity Analysis (GSA) procedure is presented to efficiently determine which parameters of a computer model influence functional responses the least, and which the most. The procedure samples box-like area of parameter variation using modified Morris algorithm. Parameter samples are mapped into samples of response functions using simulation. Discrete representations of responses are processed concurrently to get discrete representation of extended Morris and an alternative global sensitivity index functions. Subsequently worst-case sensitivity measures are formed, to enable detection of the least and most influential model parameters. Procedure operation is illustrated with with GSA of a photo-detector front end time-domain step response.

ABSTRACT. The design and proof of concept implementation of a biomedical measurement device specifically targeting human wrist movements is presented. The key aspects of development are the integrated measurement of wrist kinematics and lower arm muscle activities, wireless operation and the possibility of real-time data streaming. The designed system addresses these requirements using single chip 9 degrees-of-freedom inertial sensors for kinematic measurements, an active myoelectric electrode frontend design to record muscle activities and a Bluetooth communication interface for device control and data streaming. In addition to design considerations and proof of concept implementation, test measurement data is presented to validate system usability in a future wrist movement classification task.

ABSTRACT. This work describes new methods of handling exceedings of the supply range in analog computation stages. These are handled as pseudo-digital and analog carry signals and used to regulate the gain of the stage where they occur as well as all computation stages that follow. A complete example for such an analog computation is simulated and presented and critical parts of the architectures are addressed. In addition, more sophisticated extensions are proposed and the ”right” way of carry handling is explained for a specific algorithm, together with a discussion of the advantages of different methods for each application.

ABSTRACT. In this work we study the quantization of audio signal for a zero-crossing method recently used to detect intruders in wildlife areas. This method implements two descriptors: D and S. These descriptors represent the number of samples between two real zeros and the number of points of local minima/maxima between two consecutive real zeros, respectively. We show using experimental results that in the proposed audio based wildlife intruder detection framework, the number of D/S pairs are almost constant till the number of bits is less than six.

ABSTRACT. Even though the importance of the lymphatic System in the active regulation of body fluid balance, in the immune system and in cancer dissemination is well known, large scale models of its behaviour are still lacking. Specifically, while several distributed and lumped models of single elements of the lymphatic system have been proposed, models that can be used as subsystems to describe behaviour of large lymphatic networks using general purpose simulators are not yet available. In this paper we propose a lumped model, based on data available in current literature, that is implemented using standard mixed mode circuit representation syntax. This allows to build large and complex lymphatic networks and simulate their transient and steady state behaviour. The model presented in this paper is limited to the element known as lymphangion that is one of the main components in lymph transport. Since we do not have yet data regarding larger networks, we will limit for the time being our discussion to a short chain of lymphangions.

ABSTRACT. Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

ABSTRACT. The linear drift memristor model, suggested by HP Labs, is used in this work together with two non-linear window functions. From the equations describing the memristor model, a state transfer function is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with its parameters. The design space is elaborated upon and it is shown that the state speed is inversely proportional to the physical length, and depth of the device. The state transfer function is simulated for Joglekar-Wolf, and Biolek window functions and the result are analyzed. The Joglekar-Wolf window function causes a complex fold of the state transfer function at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also show how the memristor can be used as an amplitude modulator and corresponding design constraints derived from the state transfer function.