DSD 2024: 2024 EUROMICRO DIGITAL SYSTEM DESIGN CONFERENCE

A
Abella, Jaume	Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+ Event Monitor Validation in High-Integrity Systems TAP: Task-Aware Profiling on Integrated Systems
Absmann, Markus	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
Acosta, Antonio	Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
Agosta, Giovanni	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Aknesil, Can	Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
Aktouf, Chouki	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
Aktouf, Chouki	How to track and predict design resources for complex chip design projects by including jointly cost and sustainability criteria
Aldinucci, Marco	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Ali, Nermine	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
Aliagha, Ensieh	DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
Alibeigi, Mina	PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Alvarez-Male, Maria Luisa	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Amar, Michael	Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels
Ammendola, Roberto	APEnetX: a custom NIC for cluster interconnects
Amonarriz, Aitor	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Anagnostopoulos, Georgios	Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations
Anagnostopoulos, Nikolaos Athanasios	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Andjelkovic, Marko	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Andronikou, Dimitrios	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Arul, Tolga	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Asavoae, Mihail	INVITED PAPER - Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers -- A Case Study
Athanasiadis, Angelos	An Open-source Fully Parameterizable Fully Synthesizable Matrix Multiplication Library for modern AMD FPGAs - WiP
Azumi, Takuya	AUTOSAR AP and ROS 2 Collaboration Framework
B
Baeyens, Jean-Pierre	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Baeyens, Rens	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Bantouna, Aimilia	Security Assessments for Networks and Services in 5G Networks
Baradie, Shaden	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Barros, António	Multiprotocol Middleware Translator for IoT
Basu Roy, Debapriya	Automatic Generation of modular multipliers upon pseudo Mersenne primes using DSP blocks on FPGAs
Baunach, Marcel	opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP
Beamer, Scott	Teaching Agile Hardware Design with Chisel
Becker, Juergen	Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs
Benea, Licinius	COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP
Bernaschi, Massimo	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Bernasconi, Anna	Exploiting PSOP Decomposition for Quantum Synthesis – WiP
Beroulle, Vincent	Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats
Biagioni, Andrea	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Biersack, Franz	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
Biglari-Abhari, Morteza	Hardware Acceleration of Capsule Networks for Real-time Applications
Bilavarn, Sébastien	Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18
Blond, Estelle	Embedded systems development, an example of implementation in a medical environment
Bogaraju, Sharatchandra Varma	An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
Brandner, Florian	INVITED PAPER - Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers -- A Case Study
Breitbach, Markus	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Bringmann, Oliver	Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
Brokalakis, Andreas	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Buchholz, Jan	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Burström, Gustav	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Butkowski, Lukasz	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
C
Cabral, Bernardo	Multiprotocol Middleware Translator for IoT
Caiza, Gustavo	Immersive Environments with Haptic Technology for the Control of an Industrial Robotic Arm - WIP
Calderón, Alejandro J.	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Callico, Gustavo Marrero	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
Calvo, Belen	Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
Carle, Thomas	Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs
Carmona, Mikael	COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP
Castelino, Cornell	An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
Cattaneo, Daniele	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Cazorla, Francisco J	Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+ Event Monitor Validation in High-Integrity Systems TAP: Task-Aware Profiling on Integrated Systems
Celestini, Alessandro	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Celino, Massimo	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Cervero, Teresa	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Charaf, Najdet	DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
Chaves, Ricardo	External Memory Protection on FPGA-Based Embedded Systems
Chen, Yan	High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs
Chiarini, Carlotta	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Chossat, Jérôme	Streamlined Models of CMOS Image Sensors Carbon Impacts
Chrysos, Grigorios	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Ciriani, Valentina	Exploiting PSOP Decomposition for Quantum Synthesis – WiP
Clavo, Bernardino	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Clijsen, Ron	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Consortium, Stratum	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Cornilly, Max	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Costa, Pedro	Multiprotocol Middleware Translator for IoT
Costella Vicenzi, Julio	Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification
Coussy, Philippe	SMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs
Cretaro, Paolo	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Crouzet, Noïc	Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs
Cuciniello, Gianmarco	Exploiting PSOP Decomposition for Quantum Synthesis – WiP
D
D'Ambra, Pasqua	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Daems, Walter	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Dafali, Rachid	Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow
Damsgaard, Hans Jakob	Hardware Generators with Chisel
Danek, Lukas	How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller
Danese, Giovanni	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Danese, Giovanni	HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images
Das, Debesh Kumar	Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
Das, Satyajit	SMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs
Das, Subrata	Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
de Haro Ruiz, Juan Miguel	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Deb, Arighna	Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
Delalot, Virginie	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
Delavari, Arvin	A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
Devi, Dantu Nandini	HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework
Di Benedetto, Luigi	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Drechsler, Rolf	SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Duan, Jinxue	Integrated Mapping and Scheduling Optimization with Genetic Algorithms
Dubrova, Elena	Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
Dyka, Zoya	Resistance of Radiation Tolerant TMR Shift Registers to Optical Fault Injections - WiP
E
Ecker, Wolfgang	Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models
Eklund, David	PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Eneriz, Daniel	Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
F
Fabelo, Himar	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
Falevoz, Yann	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Fanucci, Luca	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
Fehrenz, Markus	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Fernández, Yaime	A hardware accelerator for quantile estimation of network packet attributes
Fernández Solórzano, Víctor	CNN-LSTM implementation methodology on SoC FPGA for Human Action Recognition based on Video
Ferreira, Luis Lino	Multiprotocol Middleware Translator for IoT
Fey, Dietmar	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Fey, Goerschwin	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Figueroa, Miguel	A hardware accelerator for quantile estimation of network packet attributes
Filgueras, Antonio	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Fišer, Petr	Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
Fleck, Tobias	Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
Fonseca, Tiago	Multiprotocol Middleware Translator for IoT
Fornaciari, William	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Frank, Florian	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Freitas, Ricardo	Multiprotocol Middleware Translator for IoT
Frezza, Ottorino	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Fritz, Gilles	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
G
Gajawada, Saketh	HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework
Gala, Neel	Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP
Galannomatis, Yannis	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Gallardo-Pavesi, Carolina	A hardware accelerator for quantile estimation of network packet attributes
Gazzoni, Marco	HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
George, Aleena Elsa	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Georgopoulos, Kostas	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Ghoreishy, Faraz	A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
Giacomini, Francesco	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Giesen León, Jeremy Jens	TAP: Task-Aware Profiling on Integrated Systems
Goehringer, Diana	Hardware-level Access Control and Scheduling of Shared Hardware Accelerators DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
Gogniat, Guy	Scripting the Unpredictable: Automate Fault Injection in CABA Simulation for Vulnerability Assessment
Gomony, Manil Dev	Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers
Gorgon, Marek	PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data
Gratréaux, Bastien	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
Gupta, Siddharth	LeQC-AT: Learning Quantization Configurations during Adversarial Training for Robust Deep Neural Networks
H
Hannig, Frank	DSL-based SNN Accelerator Design using Chisel
Hanyu, Hiroyuki	AUTOSAR AP and ROS 2 Collaboration Framework
Hartetos, Konstantinos	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Hassan, Mohamed	HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost Event Monitor Validation in High-Integrity Systems
Hayes, Michael	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Heemstra, Sonia	Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers
Heiskanen, Mikko	Digital twins benefits and challenges from intelligent motion control point of view
Hemani, Ahmed	Exploration of Custom Floating-Point Formats: A Systematic Approach
Hemmati, Maryam	Hardware Acceleration of Capsule Networks for Real-time Applications
Hennebert, Christine	Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats
Herkersdorf, Andreas	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
Herkersdorf, Andreas	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
Hernández, Cecilia	A hardware accelerator for quantile estimation of network packet attributes
Hernández, Mar	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Hosseinzadeh, Shima	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
I
Iannone, Francesco	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Ilic, Aleksandar	External Memory Protection on FPGA-Based Embedded Systems
Ioannidis, Sotiris	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Ishigooka, Tasuku	AUTOSAR AP and ROS 2 Collaboration Framework
Iwakami, Ryudai	AUTOSAR AP and ROS 2 Collaboration Framework
J
Jaschke, Daniel	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Jayet, Quentin	Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats
Jellum, Erling	Hardware Generators with Chisel
Jiang, Junqiang	Integrated Mapping and Scheduling Optimization with Genetic Algorithms
Jiménez-González, Daniel	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Jin, Shengjie	Integrated Mapping and Scheduling Optimization with Genetic Algorithms
Joannou, Alexandre	A Suite of Processors to Explore CHERI-RISC-V Microarchitecture
Jordan, Michael Guilherme	Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification
Juarez, Eduardo	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
K
Kanics, Kristóf	opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP
Katzenbeisser, Stefan	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Keszöcze, Oliver	Hardware Generators with Chisel DSL-based SNN Accelerator Design using Chisel
Khandelwal, Shashwat	An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
Kieffer, Yann	Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats
Kilic, Alp	NanoXplore : European Leader in FPGA and SoC FPGA
Kissich, Meinhard	opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP
Kitsos, Paris	Security Assessments for Networks and Services in 5G Networks
Kodýtek, Filip	Counter power leakage for frequency extraction of ring oscillators in ROPUF
Koeck, Enrico	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Kohútka, Lukáš	Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches
Korol, Guilherme	Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification
Kosmidis, Leonidas	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Kral, Jiri	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Krishna Venkatesan, Nitin	DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
Krstic, Milos	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Kryjak, Tomasz	Event-based vision on FPGA - a survey PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data
Kulczewski, Michal	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Kumar, Akash	LeQC-AT: Learning Quantization Configurations during Adversarial Training for Robust Deep Neural Networks
Kuppens, Hans	Digital twins benefits and challenges from intelligent motion control point of view
L
Lagares, Alfonso	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Lampropoulos, Kostas	Security Assessments for Networks and Services in 5G Networks
Lancaster, Suzanne	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Langendoerfer, Peter	Resistance of Radiation Tolerant TMR Shift Registers to Optical Fault Injections - WiP
Lanzieri, Leandro	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Lapotre, Vianney	Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow Scripting the Unpredictable: Automate Fault Injection in CABA Simulation for Vulnerability Assessment
Laurijssen, Dennis	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Le Lann, Jean-Christophe	An HLS algorithm for the direct synthesis of complex control flow graphs into finite state machines with implicit datapath
Leon, Raquel	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Leporati, Francesco	HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Leva, Alberto	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Li, Zhuoer	Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18
Licciardo, Gian Domenico	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Liess, Marco	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
Liess, Marco	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
Liguori, Rosalba	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Lisboa Malaquias, Felipe	INVITED PAPER - Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers -- A Case Study
Lo Cicero, Francesca	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Lojda, Jakub	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Lonardo, Alessandro	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Lotter, Fabiana	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
López Ruiz, Nuria	Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications
Lórencz, Róbert	Counter power leakage for frequency extraction of ring oscillators in ROPUF
M
Mach, Ján	Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches
Malakonakis, Pavlos	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Maletic, Nebojsa	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Manni, Francesca	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Marco, Santiago	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Marenzi, Elisa	HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
Marquez-Suarez, Nerea	Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology
Martin, Kevin	SMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs
Martinelli, Michele	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Martorell, Xavier	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Marty, Thibaut	Streamlined Models of CMOS Image Sensors Carbon Impacts
Martínez Olmos, Antonio	Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications
Mavroidis, Iakovos	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Medrano, Nicolas	Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
Menkovski, Vlado	Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers
Mesa Simón, Miguel Ángel	Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications
Mexis, Nico	A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules
Mezzetti, Enrico	Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+ Event Monitor Validation in High-Integrity Systems TAP: Task-Aware Profiling on Integrated Systems
Miglioranza, Nicola	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Mikolajick, Thomas	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Mirzakuchaki, Sattar	A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
Miškovský, Vojtěch	Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash algorithm
Mohamed, Sajid	Digital twins benefits and challenges from intelligent motion control point of view
Mohammadi, Mohammadreza	PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Monopoli, Matteo	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
Monorchio, Andrea	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems
Montangero, Simone	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Moore, Simon W.	A Suite of Processors to Explore CHERI-RISC-V Microarchitecture
Morais, Lucas	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Morera, Jesus	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Moreto, Miquel	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Mueller, Luca	SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Mueller-Gritschneder, Daniel	Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization
Mystkowska, Gabriela	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
N
Nannipieri, Pietro	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
Navanesan, Lojenaa	Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels
Ney, Jonas	Achieving High-Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA
Niar, Smail	Hardware Acceleration of Capsule Networks for Real-time Applications
Novotny, Martin	How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller
O
Oleksiak, Ariel	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Olekšák, Matúš	Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash algorithm
Onaindia, Peio	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Oren, Yossi	Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels
Ortega, Samuel	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems
P
P S, Babu	Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP
Palazzari, Paolo	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Palma López, Alberto José	Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications
Paolucci, Pier Stanislao	APEnetX: a custom NIC for cluster interconnects
Papaefstathiou, Ioannis	An Open-source Fully Parameterizable Fully Synthesizable Matrix Multiplication Library for modern AMD FPGAs - WiP REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Parvaresh, Amirhossein	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Pastorelli, Elena	APEnetX: a custom NIC for cluster interconnects
Pau, Danilo	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Pavlitska, Svetlana	Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
Pebay-Peyroula, Florian	COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP
Peccia, Federico Nicolás	Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
Pelcat, Maxime	Streamlined Models of CMOS Image Sensors Carbon Impacts
Peng, Bo	AUTOSAR AP and ROS 2 Collaboration Framework
Peng, Zebo	Integrated Mapping and Scheduling Optimization with Genetic Algorithms
Pensec, William	Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow Scripting the Unpredictable: Automate Fault Injection in CABA Simulation for Vulnerability Assessment
Pertuz, Sergio	Hardware-level Access Control and Scheduling of Shared Hardware Accelerators
Peter, Astile	Exploration of Custom Floating-Point Formats: A Systematic Approach
Petryk, Dmytro	Resistance of Radiation Tolerant TMR Shift Registers to Optical Fault Injections - WiP
Pezzarossa, Luca	Hardware Generators with Chisel
Plagwitz, Patrick	DSL-based SNN Accelerator Design using Chisel
Pomante, Luigi	Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project
Pontisso, Luca	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Popp, Ralf	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Posadas Cobo, Héctor	CNN-LSTM implementation methodology on SoC FPGA for Human Action Recognition based on Video
Potestad Ordóñez, Francisco Eugenio	Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
Poulios, Kostas	Security Assessments for Networks and Services in 5G Networks
Przewłocka-Rus, Dominika	PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data
Prévotet, Jean-Christophe	Streamlined Models of CMOS Image Sensors Carbon Impacts
Pujol, Roger	Event Monitor Validation in High-Integrity Systems
Pérez Ávila, Antonio Javier	Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications
Q
Qaise, Omar	Security Assessments for Networks and Services in 5G Networks
Queneherve, Kévin	Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow
Quintana Quintana, Laura	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems
R
R, Kanish	Precision and Power Efficient Piece-wise-Linear Implementation of Transcendental Functions
Ragusa, Domenico	FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
Ramallo-Fariña, Yolanda	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Rao, Madhav	Precision and Power Efficient Piece-wise-Linear Implementation of Transcendental Functions HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework
Raptis, Lampros	Security Assessments for Networks and Services in 5G Networks
Ratnaparkhi, Omkar	Precision and Power Efficient Piece-wise-Linear Implementation of Transcendental Functions
Reghenzani, Federico	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Resende, João Carlos	External Memory Protection on FPGA-Based Embedded Systems
Rial, Claudio	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Rochange, Christine	Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs
Rodriguez-Almeida, Antonio J.	FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
Rossi, Cristian	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Rubino, Alfredo	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Rugg, Peter	A Suite of Processors to Explore CHERI-RISC-V Microarchitecture
Rutzig, Mateus	Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification
S
S, Shree Harish	Automatic Generation of modular multipliers upon pseudo Mersenne primes using DSP blocks on FPGAs
Sajan, Christie Sajitha	SMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs
Salmen, Mathis	Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization
Saponara, Sergio	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Sarkar, Souradip	Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers
Saverio Lodi, Carlo	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Savvakos, Charalampos	REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI
Sayakkara, Asanka	Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels
Schade, Florian	Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs
Scheipel, Tobias	opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP
Schlarb, Holger	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Schlichtmann, Ulf	Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization
Schmidt, Thomas C.	Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Schneider Beck Filho, Antonio Carlos	Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification
Schoeberl, Martin	Hardware Generators with Chisel
Segura, Mikel	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Sepúlveda, Johanna	Quantum-Secure Identity-based Encryption for Automotive Systems
Serrano-Cases, Alejandro	Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+
Severino, Ricardo	Multiprotocol Middleware Translator for IoT
Shahhoseini, Hadi Shahriar	A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
Shan, Julia	Hardware Acceleration of Capsule Networks for Real-time Applications
Shanker, Shreejith	An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
Shrestha, Rakesh	PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Silva, Cláudia	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Simek, Vaclav	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Simula, Francesco	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Sinaei, Sima	PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Slesazeck, Stefan	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
Smrz, Pavel	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Socorro-Marrero, Guillermo V.	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems
Solé Bonet, Marc	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Soto, Javier E.	A hardware accelerator for quantile estimation of network packet attributes
Stammler, Matthias	Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs
Stamoulis, Andreas	Security Assessments for Networks and Services in 5G Networks
Staníček, Ondřej	Counter power leakage for frequency extraction of ring oscillators in ROPUF
Starling Babette, Earlene	Hardware Acceleration of Capsule Networks for Real-time Applications
Stathis, Dimitrios	Exploration of Custom Floating-Point Formats: A Systematic Approach
Steckel, Jan	Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
Strnadel, Josef	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
Sukumaran, Simi	Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP
Sun, Bailian	HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost
Sun, Zhifang	Integrated Mapping and Scheduling Optimization with Genetic Algorithms
Suárez Plata, Daniel	CNN-LSTM implementation methodology on SoC FPGA for Human Action Recognition based on Video
T
Tadikken, Maike	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Taheri Monfared, Asma	Exploiting PSOP Decomposition for Quantum Synthesis – WiP
Tampouratzis, Nikolaos	An Open-source Fully Parameterizable Fully Synthesizable Matrix Multiplication Library for modern AMD FPGAs - WiP
Tanaka, Kiyofumi	High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs
Tanguy, Philippe	Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow
Tedeschi, Riccardo	Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor - WIP
Teich, Jürgen	DSL-based SNN Accelerator Design using Chisel
Tena-Sánchez, Erica	Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
Terraneo, Federico	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Torti, Emanule	HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
Tranoris, Christos	Security Assessments for Networks and Services in 5G Networks
Trompouki, Matina M.	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
U
Ullah, Salim	LeQC-AT: Learning Quantization Configurations during Adversarial Training for Robust Deep Neural Networks
V
Vaddeboina, Mounika	Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models
van Bolderik, Bram	Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers
van Kempen, Philipp	Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization
Vega, Carlos	Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology
Verbers, Max	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Verchyk, Dariia	Quantum-Secure Identity-based Encryption for Automotive Systems
Vicini, Piero	The TEXTAROSSA Project: Cool All the Way Down to the Hardware APEnetX: a custom NIC for cluster interconnects
Vidal, Miquel	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Vierimaa, Matias	Digital twins benefits and challenges from intelligent motion control point of view
Vilardell, Sergi	Event Monitor Validation in High-Integrity Systems
Vitolo, Paola	In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
W
Wacquez, Romain	COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP
Wagner, Ana	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Warrier, Tripti	Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP
Wehn, Norbert	Achieving High-Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA
Weis, Christian	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Weppe, Olivier	Streamlined Models of CMOS Image Sensors Carbon Impacts
Wild, Thomas	ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic
Wild, Thomas	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
Wirrer, Gerhard	opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP
Wolf, Jannis	The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Woodruff, Jonathan	A Suite of Processors to Explore CHERI-RISC-V Microarchitecture
Wulf, Cornelia	Hardware-level Access Control and Scheduling of Shared Hardware Accelerators
Wüben, Dirk	6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
X
Xydis, Sotirios	Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations
Y
Yang, Yu	Exploration of Custom Floating-Point Formats: A Systematic Approach
Yilmazer, Alper	Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models
Yousefzadeh, Saba	Exploration of Custom Floating-Point Formats: A Systematic Approach
Z
Zaourar, Lilia	Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP
Zinger, Sveta	3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Zompakis, Nikolaos	Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations
Zulberti, Luca	SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
Zummo, Giuseppe	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Zuñiga-González, Virginia	Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
Zyla, Klajd	FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
Á
Álvarez, Carlos	The TEXTAROSSA Project: Cool All the Way Down to the Hardware
Č
Čičák, Pavel	Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches

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