Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory (abstract)

Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation (abstract)

Exploiting PSOP Decomposition for Quantum Synthesis – WiP (abstract)

Hardware Acceleration of Capsule Networks for Real-time Applications (abstract)

Counter power leakage for frequency extraction of ring oscillators in ROPUF (abstract)

A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules (abstract)

COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP (abstract)

Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow (abstract)

Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash algorithm (abstract)

SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth (abstract)

Studying the Degradation of Propagation Delay on FPGAs at the European XFEL (abstract)

Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches (abstract)

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications (abstract)

APEnetX: a custom NIC for cluster interconnects (abstract)

FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar (abstract)

Achieving High-Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA (abstract)

A hardware accelerator for quantile estimation of network packet attributes (abstract)

Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers (abstract)

How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller (abstract)

Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats (abstract)

Automatic Generation of modular multipliers upon pseudo Mersenne primes using DSP blocks on FPGAs (abstract)

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher (abstract)

Teaching Agile Hardware Design with Chisel (abstract)

Hardware Generators with Chisel (abstract)

DSL-based SNN Accelerator Design using Chisel (abstract)

An Open-source Fully Parameterizable Fully Synthesizable Matrix Multiplication Library for modern AMD FPGAs - WiP (abstract)

Immersive Environments with Haptic Technology for the Control of an Industrial Robotic Arm - WIP (abstract)

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor - WIP (abstract)

ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic (abstract)

Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification (abstract)

CNN-LSTM implementation methodology on SoC FPGA for Human Action Recognition based on Video (abstract)

PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data (abstract)

Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels (abstract)

Resistance of Radiation Tolerant TMR Shift Registers to Optical Fault Injections - WiP (abstract)

An HLS algorithm for the direct synthesis of complex control flow graphs into finite state machines with implicit datapath (abstract)

Integrated Mapping and Scheduling Optimization with Genetic Algorithms (abstract)

SplitMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs (abstract)

Streamlined Models of CMOS Image Sensors Carbon Impacts (abstract)

HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework (abstract)

Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP (abstract)

opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP (abstract)

Exploration of Custom Floating-Point Formats: A Systematic Approach (abstract)

Hardware-level Access Control and Scheduling of Shared Hardware Accelerators (abstract)

Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+ (abstract)

Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18 (abstract)

INVITED PAPER - Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers -- A Case Study (abstract)

SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems (abstract)

Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine (abstract)

AUTOSAR AP and ROS 2 Collaboration Framework (abstract)

Multiprotocol Middleware Translator for IoT (abstract)

Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization (abstract)

Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs (abstract)

A Suite of Processors to Explore CHERI-RISC-V Microarchitecture (abstract)

Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP (abstract)

Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure (abstract)

Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment (abstract)

Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations (abstract)

External Memory Protection on FPGA-Based Embedded Systems (abstract)

Event Monitor Validation in High-Integrity Systems (abstract)

Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs (abstract)

DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge (abstract)

Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator (abstract)

PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection (abstract)

6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications (abstract)

3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project (abstract)

REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI (abstract)

NanoXplore : European Leader in FPGA and SoC FPGA (abstract)

Embedded systems development, an example of implementation in a medical environment (abstract)

How to track and predict design resources for complex chip design projects by including jointly cost and sustainability criteria (abstract)

Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications (abstract)

Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems (abstract)

Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology (abstract)

HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images (abstract)

Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models (abstract)

LeQC-AT: Learning Quantization Configurations during Adversarial Training for Robust Deep Neural Networks (abstract)

High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs (abstract)

HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost (abstract)

Digital twins benefits and challenges from intelligent motion control point of view (abstract)

The TEXTAROSSA Project: Cool All the Way Down to the Hardware (abstract)

Security Assessments for Networks and Services in 5G Networks (abstract)

Event-based vision on FPGA - a survey (abstract)

An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery (abstract)

TAP: Task-Aware Profiling on Integrated Systems (abstract)

Precision and Power Efficient Piece-wise-Linear Implementation of Transcendental Functions (abstract)

Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists (abstract)

In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization (abstract)

FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing (abstract)

Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA (abstract)

The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things (abstract)

The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators (abstract)

Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project (abstract)