PROGRAM
Days: Wednesday, August 28th Thursday, August 29th Friday, August 30th
Wednesday, August 28th
View this program: with abstractssession overviewtalk overview
10:45-12:15 Session 1A: Emerging Technologies and AI
Chair:
Location: Room 102
10:45 | Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory (abstract) |
11:15 | Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation (abstract) |
11:30 | Exploiting PSOP Decomposition for Quantum Synthesis – WiP (abstract) |
11:45 | Hardware Acceleration of Capsule Networks for Real-time Applications (abstract) |
10:45-12:15 Session 1B: Architectures and Hardware for Security Applications - 1
Chair:
Location: Room 106
10:45 | Counter power leakage for frequency extraction of ring oscillators in ROPUF (abstract) |
11:15 | A Runtime-Accessible True Random Number Generator Based on Commercial Off-The-Shelf Resistive Random Access Memory Modules (abstract) |
11:30 | COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology - WiP (abstract) |
11:45 | Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow (abstract) |
12:00 | Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash algorithm (abstract) |
10:45-12:15 Session 1C: Dependability, Testing and Fault Tolerance in Digital Systems
Chair:
Location: Room 109
10:45 | SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth (abstract) ![]() |
11:15 | Studying the Degradation of Propagation Delay on FPGAs at the European XFEL (abstract) |
11:45 | Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches (abstract) |
12:00 | A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications (abstract) |
14:45-16:15 Session 2A: Networking
Chair:
Location: Room 102
14:45 | APEnetX: a custom NIC for cluster interconnects (abstract) |
15:15 | FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar (abstract) |
15:30 | Achieving High-Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA (abstract) |
15:45 | A hardware accelerator for quantile estimation of network packet attributes (abstract) |
16:00 | Agile Design-Space Exploration of Dynamic Layer-skipping in Neural Receivers (abstract) |
14:45-16:15 Session 2B: Architectures and Hardware for Security Applications - 2
Chair:
Location: Room 106
14:45 | How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller (abstract) |
15:15 | Securing Elapsed Time for Blockchain: Proof of Hardware Time and some of its Physical Threats (abstract) |
15:45 | Automatic Generation of modular multipliers upon pseudo Mersenne primes using DSP blocks on FPGAs (abstract) |
16:00 | Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher (abstract) |
14:45-16:15 Session 2C: Digital Design and Verification with Chisel
Chair:
Location: Room 109
14:45 | Teaching Agile Hardware Design with Chisel (abstract) |
15:15 | Hardware Generators with Chisel (abstract) |
15:45 | DSL-based SNN Accelerator Design using Chisel (abstract) |
16:15-17:00 Session 3: Coffee Break + Poster Session – Auditorium Hall
An Open-source Fully Parameterizable Fully Synthesizable Matrix Multiplication Library for modern AMD FPGAs - WiP (abstract) |
Immersive Environments with Haptic Technology for the Control of an Industrial Robotic Arm - WIP (abstract) |
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor - WIP (abstract) |
17:00-18:30 Session 4A: Networking and Application of AI
Chair:
Location: Room 102
17:00 | ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic (abstract) |
17:30 | Exploiting Virtual Layers and Pruning for FPGA-based Adaptive Traffic Classification (abstract) |
18:00 | CNN-LSTM implementation methodology on SoC FPGA for Human Action Recognition based on Video (abstract) |
18:15 | PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data (abstract) |
17:00-18:30 Session 4B: Architectures and Hardware for Security Applications & Computer-Aided-Design of circuits and systems
Chair:
Location: Room 106
17:00 | Two's Complement: Monitoring Control Flow using Both Power and Electromagnetic Side Channels (abstract) |
17:30 | Resistance of Radiation Tolerant TMR Shift Registers to Optical Fault Injections - WiP (abstract) |
17:45 | An HLS algorithm for the direct synthesis of complex control flow graphs into finite state machines with implicit datapath (abstract) |
18:00 | Integrated Mapping and Scheduling Optimization with Genetic Algorithms (abstract) |
18:15 | SMS: Split Modulo-Scheduling for Accelerating Loops onto CGRAs (abstract) |
17:00-18:30 Session 4C: Sustainable Digital System Design
Chairs:
Location: Room 109
17:00 | Streamlined Models of CMOS Image Sensors Carbon Impacts (abstract) |
17:30 | HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework (abstract) |
18:00 | Towards Sustainable Electronic Design Automation Flows: A Joint Approach Based on Complexity Metrics - WiP (abstract) |
18:15 | opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs - WiP (abstract) |
Thursday, August 29th
View this program: with abstractssession overviewtalk overview
09:40-11:10 Session 5A: Hardware Acceleration Analysis and Scheduling
Chair:
Location: Room 102
09:40 | Exploration of Custom Floating-Point Formats: A Systematic Approach (abstract) |
10:10 | Hardware-level Access Control and Scheduling of Shared Hardware Accelerators (abstract) |
10:40 | Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+ (abstract) |
10:55 | Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18 (abstract) |
09:40-11:10 Session 5B: Hardware, Software, and Tools for the IoT-to-Edge-to-Cloud Continuum
Chairs:
Location: Room 106
09:40 | INVITED PAPER - Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers -- A Case Study (abstract) |
10:02 | SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems (abstract) |
10:24 | Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine (abstract) |
10:39 | AUTOSAR AP and ROS 2 Collaboration Framework (abstract) |
10:54 | Multiprotocol Middleware Translator for IoT (abstract) |
09:40-11:10 Session 5C: Opensource Methods, architectures, tools and technologies for RISC-V
Chair:
Location: Room 109
09:40 | Seal5: Semi-automated LLVM Support for RISC-V ISA Extensions Including Autovectorization (abstract) |
10:10 | Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs (abstract) |
10:40 | A Suite of Processors to Explore CHERI-RISC-V Microarchitecture (abstract) |
10:55 | Accelerating Galois Field Arithmetic based Cryptographic Algorithms on RISC-V cores using Carryless Multiplication - WiP (abstract) |
11:25-12:55 Session 6A: Security and monitoring of hardware devices
Chair:
Location: Room 102
11:25 | Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure (abstract) |
11:55 | Scripting the Unpredictable: Automate Fault Injection in CABA Simulation for Vulnerability Assessment (abstract) |
12:10 | Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations (abstract) |
12:25 | External Memory Protection on FPGA-Based Embedded Systems (abstract) |
12:40 | Event Monitor Validation in High-Integrity Systems (abstract) |
11:25-12:55 Session 6B: Safety, Security and Privacy of Cyber-Physical Systems, and Computations at the Edge
Chair:
Location: Room 106
11:25 | Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs (abstract) |
11:55 | DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge (abstract) |
12:10 | Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator (abstract) |
12:25 | PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection (abstract) |
12:40 | Quantum-Secure Identity-based Encryption for Automotive Systems (abstract) |
11:25-12:55 Session 6C: European Projects in Digital Systems Design – 1
Chair:
Location: Room 109
11:25 | 6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications (abstract) |
11:55 | 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project (abstract) |
12:25 | REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI (abstract) |
15:00-16:30 Session 7: Industrial Session - Auditorium
Chairs:
15:00 | NanoXplore : European Leader in FPGA and SoC FPGA (abstract) |
15:30 | Embedded systems development, an example of implementation in a medical environment (abstract) |
16:00 | How to track and predict design resources for complex chip design projects by including jointly cost and sustainability criteria (abstract) |
Friday, August 30th
View this program: with abstractssession overviewtalk overview
09:40-11:10 Session 8A: Hyperspectral Imaging Applications, Algorithms and Architectures
Chair:
Location: Room 102
09:40 | Assessment of the performance of a commercial spectral sensor for portable and cost-effective multispectral applications (abstract) |
10:02 | Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems (abstract) |
10:24 | Inter-band Movement Compensation Method for Hyperspectral Images based on Spectral Scanning Technology (abstract) |
10:46 | HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images (abstract) |
09:40-11:10 Session 8B: Hardware and Resource Aware Digital AI
Chair:
Location: Room 106
09:40 | Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models (abstract) |
10:10 | LeQC-AT: Learning Quantization Configurations during Adversarial Training for Robust Deep Neural Networks (abstract) |
10:40 | High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs (abstract) |
10:55 | HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost (abstract) |
09:40-11:10 Session 8C: European Projects in Digital Systems Design – 2
Chair:
Location: Room 109
09:40 | Digital twins benefits and challenges from intelligent motion control point of view (abstract) |
10:10 | The TEXTAROSSA Project: Cool All the Way Down to the Hardware (abstract) |
10:40 | Security Assessments for Networks and Services in 5G Networks (abstract) |
14:00-15:30 Session 9A: Vision, Image, Numbers and Functions
Chair:
Location: Room 102
14:00 | Event-based vision on FPGA - a survey (abstract) |
14:30 | An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery (abstract) |
14:45 | TAP: Task-Aware Profiling on Integrated Systems (abstract) |
15:15 | Precision and Power Efficient Piece-wise-Linear Implementation of Transcendental Functions (abstract) |
14:00-15:30 Session 9B: Advanced Systems for Health Wellness and Personal Monitoring
Chairs:
Location: Room 106
14:00 | Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists (abstract) |
14:22 | In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization (abstract) |
14:44 | FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing (abstract) |
15:06 | Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA (abstract) |
14:00-15:30 Session 9C: European Projects in Digital Systems Design – 3
Chair:
Location: Room 109
14:00 | The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things (abstract) |
14:30 | The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators (abstract) |
15:00 | Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project (abstract) |