DSD2021: EUROMICRO CONFERENCE ON DIGITAL SYSTEMS DESIGN 2021

This page contains an index consisting of author-provided keywords.

4
4K	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream
5
5G Security	5G Security: FPGA Implementation of SNOW-V Stream Cipher
A
Acceleration	An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
ADAS/AD	Measuring trust in automated driving using amulti-level approach to human factors
Aging modeling	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
AIOPS	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
anomaly detection	Towards Machine Learning Support for Embedded System Tests Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
Apollo	Enabling Unit Testing of Already-Integrated AI-based Software Systems: The Case of Apollo for Autonomous Driving
Applet	Towards a More Flexible IoT SAFE Implementation
Application characterization	NMPO: Near-Memory Computing Profiling and Offloading
Application Deployment	A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments
Approximate Circuits	Metrics for the Evaluation of Approximate Sequential Streaming Circuits
Approximate Computing	A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA Metrics for the Evaluation of Approximate Sequential Streaming Circuits
Artificial Intelligence	Going to the Edge - Bringing Internet of Things and Artificial Intelligence Together AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
artificial intelligence of things	Going to the Edge - Bringing Internet of Things and Artificial Intelligence Together
ASIC	A Power-Efficient Parameter Quantization Technique for CNN Accelerators
ASIL	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
asynchronous	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
asynchronous circuits	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits
attacks	MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
Automata	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
Automotive domain	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Autonomous driving	Enabling Unit Testing of Already-Integrated AI-based Software Systems: The Case of Apollo for Autonomous Driving
AUTOSAR	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
avalanche properties	Novel non-cryptographic hash functions for networking and security applications on FPGA
B
Battery discharge simulation	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
Battery state-of-charge	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
Binary neural networks	Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge
Binary nonlinear codes	Search Strategy of Large Nonlinear Block Codes
Biochemical analysis	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
Biological system modeling	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
BIST	Search Strategy of Large Nonlinear Block Codes
brake-by-wire controllers	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
BRIEF	An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents
Building HVAC system	Co-designing Intelligent Control of Building HVACs and Microgrids
C
Cache Metrics	Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
Cache Simulator	Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
CAN	FPGA-based real-time monitoring support for CANOpen applications
CANOpen	FPGA-based real-time monitoring support for CANOpen applications
Cartesian Genetic Programming	Resynthesis of logic circuits using machine learning and reconvergent paths
CGRA	Scheduling Persistent and Fully Cooperative Instructions
CGRAs	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Characterization	Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller
Checkpointing	Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications
Circuit models	Gain and Pain of a Reliable Delay Model
Clang	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
Clifford+T circuits	Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
clique cover number	Search Strategy of Large Nonlinear Block Codes
clustering	Improving the Efficiency of Transformers for Resource-Constrained Devices
Co-processor	Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing
Coarse-grained reconfigurable architectures	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Coarse-grained reconfigurable arrays	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
coded modulation	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
Combinational logic	Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge
comfort	Measuring trust in automated driving using amulti-level approach to human factors
Communication Abstraction	Heterogeneous Communication Virtualisation for Distributed Embedded Applications
comparative analysis	Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
Computing	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Confidentiality	Protecting IoT Devices through a Hardware-driven Memory Verification Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
connected component labelling (CCL)	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream
Connectivity	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Constraint programming	Scheduling Persistent and Fully Cooperative Instructions
Continuous System Engineering	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
controlled collisions	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
Convolutional Neural Networks	POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators
cooperative driving/braking	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
CPS4EU Project	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Cryptographic Extension	Protected Extension of Cryptographic Algorithms on RISC-V
Cryptography	Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
Cyber security	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Cyber-Physical Systems	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
D
data compression	An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR
Data driven models	The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0)
data processing	An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR
Data-driven method	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
Debugging	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
decomposition	Decomposition of transition systems into sets of synchronizing state machines
deep learning	A Power-Efficient Parameter Quantization Technique for CNN Accelerators
Deep Neural Networks	TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Map
Deep optical flow	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Deep Reinforcement Learning	Co-designing Intelligent Control of Building HVACs and Microgrids
Deformable shape tracking	High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
dependability	Secure and dependable: Area-efficient masked and fault-tolerant architectures
depth estimation	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
Design and synthesis of systems	Decomposition of transition systems into sets of synchronizing state machines
design automation	Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
Design for testability	Search Strategy of Large Nonlinear Block Codes
design space exploration	Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA
detection	MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
DevOps	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
dilution	Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
Disjoint Sum-of-Products	A Boolean Heuristic for Disjoint SOP Synthesis
Distributed Embedded Applications	Heterogeneous Communication Virtualisation for Distributed Embedded Applications
Distributed System	Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications
DPR Schedulability Analysis	An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems
Driver state	Measuring trust in automated driving using amulti-level approach to human factors
Drone/UAV	Builing Blocks and Interaction Patterns of Unmanned Aerial Systems
DTLS	Towards a More Flexible IoT SAFE Implementation
dynamic delay models	Gain and Pain of a Reliable Delay Model
Dynamic Partial Reconfiguration	An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems
E
ECS	The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0)
Edge processing	Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge
Eigen	High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
Electronic Design Automation	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
embedded software	Towards Machine Learning Support for Embedded System Tests
embedded systems	Towards Machine Learning Support for Embedded System Tests A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Emergency braking	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
Energy Distribution	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
energy efficiency	Improving the Efficiency of Transformers for Resource-Constrained Devices
Ensemble machine learning	NMPO: Near-Memory Computing Profiling and Offloading
eSIM	Towards a More Flexible IoT SAFE Implementation
eUICC	Towards a More Flexible IoT SAFE Implementation
Evolutionary Resynthesis	Resynthesis of logic circuits using machine learning and reconvergent paths
evolutionary-techniques	Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques
external memory protection	Protecting IoT Devices through a Hardware-driven Memory Verification
F
Face alignment	High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
Fail-Operational	Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3
faithful digital timing simulation	Gain and Pain of a Reliable Delay Model
Farrow structure	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
FAST	An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents
Fault Attacks	Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities
fault injection	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits
Fault maps	TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Map
Fault models	Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller
Fault Tolerance	Reliability Analysis of the FPGA Control System with Reconfiguration Hardening
Fault Tolerance Property Estimation	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
fault-tolerance assessment	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits
Fault-Tolerant System Design	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
field-programmable gate array	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
fog computing	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
Formal Methods in System Design	Decomposition of transition systems into sets of synchronizing state machines
Formal Verification	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
FPGA	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents FPGA-based real-time monitoring support for CANOpen applications Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher 5G Security: FPGA Implementation of SNOW-V Stream Cipher Novel non-cryptographic hash functions for networking and security applications on FPGA Reliability Analysis of the FPGA Control System with Reconfiguration Hardening Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
FPGA overlay	A RISC-V-based FPGA Overlay to SimplifyEmbedded Accelerator Deployment
fractional delay filters	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
Framework	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
Functional Blocks	Builing Blocks and Interaction Patterns of Unmanned Aerial Systems
FUSION	Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3
G
Generic Framework	A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments
glitch propagation	Gain and Pain of a Reliable Delay Model
Graph theory	Search Strategy of Large Nonlinear Block Codes
H
Hardware accelerators	TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
hardware implementation	A Power-Efficient Parameter Quantization Technique for CNN Accelerators
hardware performance counters	MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
hardware security	Protecting IoT Devices through a Hardware-driven Memory Verification Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
hardware software co-design	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
heart-rate	Measuring trust in automated driving using amulti-level approach to human factors
Heterogeneous	Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
Heterogeneous Computing	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
Heterogenous Communication	Heterogeneous Communication Virtualisation for Distributed Embedded Applications
high-level functional fault model	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules
High-level synthesis	A RISC-V-based FPGA Overlay to SimplifyEmbedded Accelerator Deployment
HMI	Measuring trust in automated driving using amulti-level approach to human factors
Hybrid Communication	Heterogeneous Communication Virtualisation for Distributed Embedded Applications
Hyperspectral imaging	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
I
Identity-based Encryption	Towards Post-Quantum Enhanced Identity-based Encryption
Image Processing	A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA
implementation-independent test generation	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules
In cabin measurement	Measuring trust in automated driving using amulti-level approach to human factors
In-vehicle networks	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Industry Automation	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Infrared imaging	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
Instruction scheduling	Scheduling Persistent and Fully Cooperative Instructions
integrity	Protecting IoT Devices through a Hardware-driven Memory Verification Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
intelligent transport systems	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
Intelligent Transportation Systems	MPC-Based Speed Tracking for Automated Urban Buses Performing V2I Communications with Traffic Lights
Interaction Patters	Builing Blocks and Interaction Patterns of Unmanned Aerial Systems
Interface Design	Towards a More Flexible IoT SAFE Implementation
internet of things	Going to the Edge - Bringing Internet of Things and Artificial Intelligence Together
Internet of Things (IoT)	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Internet of Things security	5G Security: FPGA Implementation of SNOW-V Stream Cipher
Inverse NTT	Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
IoT	Protecting IoT Devices through a Hardware-driven Memory Verification Towards a More Flexible IoT SAFE Implementation
Izikevich neuron	Revealing the secrets of Spiking Neural Networks: the case of Izhikevich neuron
J
Java Card	Towards a More Flexible IoT SAFE Implementation
JICG	Optical Fault Injection Attacks against Radiation-Hard Registers
L
lab-on-a-chip	Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
Lagrange interpolation	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
laser	Optical Fault Injection Attacks against Radiation-Hard Registers
Laser fault injection	Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller
LiDAR	An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR
Lightweight Cryptography	Protected Extension of Cryptographic Algorithms on RISC-V
Logic optimization	Resynthesis of logic circuits using machine learning and reconvergent paths
Logic synthesis	A Boolean Heuristic for Disjoint SOP Synthesis
low-power	A Power-Efficient Parameter Quantization Technique for CNN Accelerators
M
machine learning	Towards Machine Learning Support for Embedded System Tests
Machine Learning Acceleration	POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators
Machine learning on edge	Evaluation of Time Series Clustering in Embedded Sensor Platform
machine learning performance prediction	Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors
malware	MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
Mandatory access control	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Mapping	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
masking	Secure and dependable: Area-efficient masked and fault-tolerant architectures
maximization	Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques
metastability analysis	Gain and Pain of a Reliable Delay Model
microarchitecture	MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
Microcontroller	Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller
microfluidics	Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
microgrid	Co-designing Intelligent Control of Building HVACs and Microgrids
MIKEY-SAKKE	Towards Post-Quantum Enhanced Identity-based Encryption
Minimum clique cover problem	Search Strategy of Large Nonlinear Block Codes
mixed precision	TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
Model Predictive Control	MPC-Based Speed Tracking for Automated Urban Buses Performing V2I Communications with Traffic Lights Co-designing Intelligent Control of Building HVACs and Microgrids
Model-based Design	Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
modular redundancy	Secure and dependable: Area-efficient masked and fault-tolerant architectures
multi-level approach	Measuring trust in automated driving using amulti-level approach to human factors
Multilevel security	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Multimedia tampering	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Multiple-choice Knapsack Problem	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
MultiProcessor	Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems
Multiprocessor system-on-chip	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Myriad	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
N
Near-memory computing	NMPO: Near-Memory Computing Profiling and Offloading
Network-on-chip	Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
Networked control systems	Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
NIST lightweight standardization competition	Novel non-cryptographic hash functions for networking and security applications on FPGA
no back-pressure	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
NoC simulation	Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration
non-cryptographic hash functions	Novel non-cryptographic hash functions for networking and security applications on FPGA
Nondeterministic execution	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
novelty detection	Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
NTT	Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
O
OpenCL	Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
operating system	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
optical Fault Injection attack	Optical Fault Injection Attacks against Radiation-Hard Registers
Optical flow	An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents
optimization	Improving the Efficiency of Transformers for Resource-Constrained Devices
Ordering	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
outlier detection	Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
Oxygen saturation	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
Oxygenation Maps	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
P
Parallel computing	Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge
Parallel execution	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
Parallel Programming	Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
Parallel simulation	Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration
PARSEC	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
Partial Dynamic Reconfiguration Controller	Reliability Analysis of the FPGA Control System with Reconfiguration Hardening
partial reconfiguration	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
perception	Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3
Performance	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Performance prediction	NMPO: Near-Memory Computing Profiling and Offloading
Petri net	Decomposition of transition systems into sets of synchronizing state machines
Physical attacks	Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities
Physics of failure	The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0)
Pinning	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
pixel accumulation	An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR
platoons	Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
Post-Quantum Cryptography	Towards Post-Quantum Enhanced Identity-based Encryption
power and thermal management	TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
Power Modelling	POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators
Prefetchers	Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
Probabilistic timing analysis	Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems
Processing-in-Memory	Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design
processing-near-memory	Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors
processor architecture	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Prognostic health monitoring	The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0)
Programmable logic	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Protected Communication	Towards a More Flexible IoT SAFE Implementation
Protection against side-channel attacks	Protected Extension of Cryptographic Algorithms on RISC-V
pseudo-Boolean optimization	Decomposition of transition systems into sets of synchronizing state machines
Pseudo-exhaustive testing	Search Strategy of Large Nonlinear Block Codes
psychophysiology	Measuring trust in automated driving using amulti-level approach to human factors
pulse degradation	Gain and Pain of a Reliable Delay Model
Q
QEMU	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
Quality Metrics	Metrics for the Evaluation of Approximate Sequential Streaming Circuits
Quality-Sensitive Applications	A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments
quantization	A Power-Efficient Parameter Quantization Technique for CNN Accelerators
quantum circuit transformation	Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
quantum computation	Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
R
radiation hardness	Optical Fault Injection Attacks against Radiation-Hard Registers
Raspberry Pi	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Real-time	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
real-time video processing	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream
Reconfigurable hardware	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
reconfigurable logic	A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Reconfiguration	Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
Redundancy Allocation	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
Redundancy Insertion	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
reference architecture	Going to the Edge - Bringing Internet of Things and Artificial Intelligence Together
reflectance	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
Reliability	TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Map Optical Fault Injection Attacks against Radiation-Hard Registers The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0)
Reliability Analysis	Reliability Analysis of the FPGA Control System with Reconfiguration Hardening
ReRAM	Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design
resource management	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
Resource-Constrained Platforms	A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments
Reverse Engineering	Revealing the secrets of Spiking Neural Networks: the case of Izhikevich neuron
Reversible logic circuits	A Boolean Heuristic for Disjoint SOP Synthesis
RISC processors	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules
RISC-V	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing Protected Extension of Cryptographic Algorithms on RISC-V
S
Safety-critical	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
sample preparation	Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
sample rate converter	Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
SAT	Decomposition of transition systems into sets of synchronizing state machines
Scalability	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
Scheduling	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
Scientific computing	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
Scratchpad Memory Management	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
security	Optical Fault Injection Attacks against Radiation-Hard Registers Secure and dependable: Area-efficient masked and fault-tolerant architectures MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
Self-Organizing Map	Evaluation of Time Series Clustering in Embedded Sensor Platform
semi-supervised	Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
Sensors	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Sequential Streaming Circuits	Metrics for the Evaluation of Approximate Sequential Streaming Circuits
Services	Towards a More Flexible IoT SAFE Implementation
Ship detection	Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge
Side Channel Attacks	Revealing the secrets of Spiking Neural Networks: the case of Izhikevich neuron
side-channel analysis	Secure and dependable: Area-efficient masked and fault-tolerant architectures
SIMD	Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing
Simulation	To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
Simulation acceleration	Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration
Simulation and Modelling Tools	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
Simulation-based performance estimation	Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems
single-frame	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
SLAM	Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications
Smart connected glasses	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
SNOW-V stream cipher	5G Security: FPGA Implementation of SNOW-V Stream Cipher
SoC	An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents
SoC prediction	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
Software engineering	AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems
Spiking Neural Networks	Revealing the secrets of Spiking Neural Networks: the case of Izhikevich neuron
state machine	Decomposition of transition systems into sets of synchronizing state machines
switching-activity	Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques
Synchronous	Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
Synthesis	Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
System Architecture	Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
System Development	Builing Blocks and Interaction Patterns of Unmanned Aerial Systems
system level testing	Towards Machine Learning Support for Embedded System Tests
System on Chip	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
System-level design methodology	A RISC-V-based FPGA Overlay to SimplifyEmbedded Accelerator Deployment
System-level modeling	Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
System-on-Chip	Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
System-on-Chip (SoC)	Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing
SystemC HLS	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
T
task allocation strategy	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
task-based programming model	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
Test vector compression technique	Search Strategy of Large Nonlinear Block Codes
test-bed	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
theory of regions	Decomposition of transition systems into sets of synchronizing state machines
Thermal imaging	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
Time series analysis	Evaluation of Time Series Clustering in Embedded Sensor Platform
Time-of-Flight	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
Tissue Oxygenation	Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
TLS	Towards a More Flexible IoT SAFE Implementation
ToF	Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
Transformers	Improving the Efficiency of Transformers for Resource-Constrained Devices
Transition system	Decomposition of transition systems into sets of synchronizing state machines
Transmission Optimisation	Heterogeneous Communication Virtualisation for Distributed Embedded Applications
trust	Measuring trust in automated driving using amulti-level approach to human factors
Two-level control	Scheduling Persistent and Fully Cooperative Instructions
two-phase cooling	TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
U
UHD	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream
Unit testing	Enabling Unit Testing of Already-Integrated AI-based Software Systems: The Case of Apollo for Autonomous Driving
Unmanned Aerial System (UAS)	Builing Blocks and Interaction Patterns of Unmanned Aerial Systems
use-case	BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario
V
V2I Communications	MPC-Based Speed Tracking for Automated Urban Buses Performing V2I Communications with Traffic Lights
Vector processing	Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing
Verification	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
VHDL	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
Video forgery detection	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Video integrity	Digital Forensics, Video Forgery Recognition, for Cyber Security Systems
Vision Processing Unit	ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
Visualization	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
Z
Zynq UltraScale+ MPSoC	A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream

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