DSD2021: EUROMICRO CONFERENCE ON DIGITAL SYSTEMS DESIGN 2021
PROGRAM

Days: Wednesday, September 1st Thursday, September 2nd Friday, September 3rd

Wednesday, September 1st

View this program: with abstractssession overviewtalk overview

09:00-10:00 Session 1: KEYNOTE 1 DSD

Keynote 1Prof. Dr. Mehrdad Dianati - University of Warwick (England) - Enabling and harvesting the benefits of cooperation among connected automated vehicles

10:00-11:30 Session 2A: ACCELERATORS

FPGA ACCELERATORS

10:00
A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA (abstract)
10:30
A RISC-V-based FPGA Overlay to SimplifyEmbedded Accelerator Deployment (abstract)
11:00
A Power-Efficient Parameter Quantization Technique for CNN Accelerators (abstract)
10:00-11:30 Session 2B: VIDEO PROCESSING

VIDEO PROCESSING

10:00
A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream (abstract)
10:30
An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR (abstract)
11:00
BarMan: Managing the Resource Continuum in a Real Video Surveillance Scenario (abstract)
11:30-13:00 Session 3A: COPROCESSORS

COPROCESSORS

11:30
An efficient FPGA-based co-processor for sparse optical flow calculation in drone agents (abstract)
12:00
Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing (abstract)
12:20
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems (abstract)
11:30-13:00 Session 3B: SYNTHESYS

SYNTHESYS

11:30
A Boolean Heuristic for Disjoint SOP Synthesis (abstract)
12:00
Resynthesis of logic circuits using machine learning and reconvergent paths (abstract)
12:30
Decomposition of transition systems into sets of synchronizing state machines (abstract)
12:50
Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns (abstract)
14:30-15:30 Session 4: KEYNOTE 2 SEAA

Keynote 2 - Dott. Marco D’Ambros - CodeLounge (Switzerland) Research + Industry = R&D - Reflections from a research-industry roundtrip

15:30-16:30 Session 5A: EUROPEAN PROJECTS IN DIGITAL SYSTEMS DESIGN 1
15:30
Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3 (abstract)
16:00
Builing Blocks and Interaction Patterns of Unmanned Aerial Systems (abstract)
15:30-16:30 Session 5B: Architecture and Hardware for Security Applications (AHSA) 1
15:30
Protected Extension of Cryptographic Algorithms on RISC-V (abstract)
16:00
Secure and dependable: Area-efficient masked and fault-tolerant architectures (abstract)
16:30-17:30 Session 6B: Architecture and Hardware for Security Applications (AHSA) 2
16:30
Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms (abstract)
17:00
Novel non-cryptographic hash functions for networking and security applications on FPGA (abstract)
17:30-19:00 Session 7A: EUROPEAN PROJECTS IN DIGITAL SYSTEMS DESIGN 3
17:30
AIDOaRt: AI-augmented automation for DevOps, a model-based framework for continuous development At RunTime in cyber-physical systems (abstract)
18:00
The H2020-ECSEL Project ”iRel40” (Intelligent Reliability 4.0) (abstract)
18:30
Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems (abstract)
17:30-18:30 Session 7B: Architecture and Hardware for Security Applications (AHSA) 3
17:30
MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities (abstract)
18:00
Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller (abstract)
Thursday, September 2nd

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09:00-10:00 Session 8: KEYNOTE 3 SEAA

Keynote 3 - Prof. Genoveffa Tortora - University of Salerno (Italy) - Are developers and software engineers simple gear of the wheel?

10:00-11:30 Session 9A: FPGA APPLICATIONS

FPGA 2

10:00
Massively parallel binary neural network inference for detecting ships in FPGA systems on the edge (abstract)
10:30
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher (abstract)
10:50
FPGA-based real-time monitoring support for CANOpen applications (abstract)
10:00-11:30 Session 9B: NETWORK ON CHIP

NETWORK ON CHIP

10:00
Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration (abstract)
10:30
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications (abstract)
10:50
Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design (abstract)
11:30-13:00 Session 10A: ANOMALIES, SECURITY AND PROTECTION
11:30
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks (abstract)
12:00
Protecting IoT Devices through a Hardware-driven Memory Verification (abstract)
12:30
Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems (abstract)
11:30-13:00 Session 10B: MODELING AND SIMULATION

MODELING AND SIMULATION

11:30
Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems (abstract)
12:00
Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors (abstract)
12:30
Towards Machine Learning Support for Embedded System Tests (abstract)
14:30-15:30 Session 11: KEYNOTE 4 DSD

KEYNOTE 4 - Prof. Dr. Marko Bertogna - University of Modena-ReggioEmilia (Italy) - Next-Generation Embedded Platforms for Robotics

15:30-16:30 Session 12A: Intelligent Transportation Systems (ITS) 1
15:30
Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications (abstract)
16:00
MPC-Based Speed Tracking for Automated Urban Buses Performing V2I Communications with Traffic Lights (abstract)
15:30-16:30 Session 12B: Applications, Architectures, Methods and Tools for Machine - and Deep Learning (AAMTM) 1
15:30
TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Map (abstract)
16:00
POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators (abstract)
16:30-17:30 Session 13A: Intelligent Transportation Systems (ITS) 2
16:30
Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements (abstract)
17:00
Measuring trust in automated driving using amulti-level approach to human factors (abstract)
16:30-17:30 Session 13B: Applications, Architectures, Methods and Tools for Machine - and Deep Learning (AAMTM) 2
16:30
Improving the Efficiency of Transformers for Resource-Constrained Devices (abstract)
17:00
Co-designing Intelligent Control of Building HVACs and Microgrids (abstract)
17:30-18:30 Session 14A: Architecture and Hardware for Security Applications (AHSA) 3
17:30
Optical Fault Injection Attacks against Radiation-Hard Registers (abstract)
17:50
Towards a More Flexible IoT SAFE Implementation (abstract)
18:10
5G Security: FPGA Implementation of SNOW-V Stream Cipher (abstract)
18:30
Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities (abstract)
17:30-19:00 Session 14B: Advanced Systems in Healthcare, Wellness and Personal Assistance (ASHWPA)
17:30
Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices (abstract)
18:00
Modeling Battery SoC Predictions for Smart Connected Glasses Simulations (abstract)
18:30
Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring (abstract)
Friday, September 3rd

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09:00-10:00 Session 15: KEYNOTE 5 DSD

Keynote 5 - Dr. Danilo Pietro Pau - Technical director, IEEE and ST Fellow, System Research and Applications, STMicroelectronics (Italy) - Characterizing deeply quantized neural networks for in-sensor computing

10:00-11:30 Session 16A: APPLICATIONS
10:00
High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm (abstract)
10:20
Highly Parallel Sample Rate Converter for Space Telemetry Transmitters (abstract)
10:40
Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras (abstract)
11:00
Evaluation of Time Series Clustering in Embedded Sensor Platform (abstract)
10:00-11:30 Session 16B: FRAMEWORKS
10:00
A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments (abstract)
10:30
ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs (abstract)
11:00
Scheduling Persistent and Fully Cooperative Instructions (abstract)
11:30-13:00 Session 17A: HW-SW CODESIGN AND RECONFIGURABILITY
11:30
An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems (abstract)
12:00
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime (abstract)
12:30
Metrics for the Evaluation of Approximate Sequential Streaming Circuits (abstract)
11:30-13:00 Session 17B: MODELING AND SIMULATION 2
11:30
To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation (abstract)
12:00
Gain and Pain of a Reliable Delay Model (abstract)
12:20
Heterogeneous Communication Virtualisation for Distributed Embedded Applications (abstract)
12:50
NMPO: Near-Memory Computing Profiling and Offloading (abstract)
15:30-16:30 Session 19A: Dependability, Testing and Fault Tolerance in Digital Systems 1
15:30
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs (abstract)
16:00
Search Strategy of Large Nonlinear Block Codes (abstract)
15:30-16:30 Session 19B: Future Trends in Emerging Technologies (FTET)
15:30
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip (abstract)
16:00
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation (abstract)
16:30-17:30 Session 20A: Dependability, Testing and Fault Tolerance in Digital Systems 2
16:30
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques (abstract)
17:00
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits (abstract)
16:30-17:30 Session 20B: Security and Privacy of Cyber-Physical Systems (SPCPS) 1
16:30
Towards Post-Quantum Enhanced Identity-based Encryption (abstract)
17:00
Digital Forensics, Video Forgery Recognition, for Cyber Security Systems (abstract)
17:20
Revealing the secrets of Spiking Neural Networks: the case of Izhikevich neuron (abstract)
17:30-18:30 Session 21A: Intelligent Transportation Systems (ITS) 3 AND Mixed-Criticality System Design (MCSDIA)
17:30
Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism (abstract)
18:00
Enabling Unit Testing of Already-Integrated AI-based Software Systems: The Case of Apollo for Autonomous Driving (abstract)
17:30-18:30 Session 21B: Dependability, Testing and Fault Tolerance in Digital Systems 3
17:30
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs (abstract)
17:50
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening (abstract)
18:10
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules (abstract)