ABSTRACT. This paper presents the evaluation of an image restoration approach based on a bilateral Gaussian filter (BGF) to address signal identification for spectrum sensing. The proposed methodology uses synthetic Long-Term Evolution (LTE) and 5G New Radio (NR) signals generated in MATLAB to build two spectrogram datasets. A Resnet-18 model has been trained with and without enhanced spectrograms to show the benefits of spectrogram preprocessing. Several case studies are considered using noisy and restored spectrograms. A noise recognition of 84.81% is obtained, showing the benefits of the proposed approach for spectrum sensing.

ABSTRACT. This study focuses on optimizing Multi-Layer Per- ceptron (MLP) neural networks for deployment in resource- constrained edge computing environments like smartphones and Internet of Things (IoT) devices. The proposed method involves using auxiliary dense Morphological Neural Networks (MNN) to generate pruning masks for each hidden layer in the MLP. These MNN have shown high efficiency in the pruning process, leading to a significant reduction in the total number of parameters. The effectiveness of our proposal is explained and validated using the Fashion-MNIST dataset. Furthermore, the performance of the optimized MLP is evaluated on an IoT platform, and compared with other state-of-the-art pruning techniques. The experimental results show the effectiveness of the proposed technique in reducing model complexity, improving power efficiency, and decreasing inference response time, while maintaining minimal impact on overall MLP accuracy. These findings have important implications for the development of efficient and scalable deep learning models tailored for edge computing applications.

ABSTRACT. This paper describes a low power integrated circuit that can communicate using commodity equipment. It operates without the need for an external crystal because it fully integrates oscillators. The operation of the chip is enabled by an energy harvesting unit that, in combination with a capacitor, collects energy from 2.45 GHz RF signals. The communication between transceivers and the integrated circuit is done by using backscattering technology being the distance limited by the energy harvester to 1 m for an input power of -12 dBm. The chip has been designed using a 65 nm process and achieves a power consumption of only 10 uW in the wake-up mode and 47$\,\mu\text{W}$ in the backscatter mode. The receiver has a sensitivity of -30 dBm, enabling it to receive weak signals. This makes the integrated circuit ideal for use in low-power, energy-efficient devices that need to operate without a battery, the potential applications of this technology are significant.

ABSTRACT. This paper proposes a design for Physical Unclonable Functions (PUFs) that exploit reconfigurable sense amplifiers for strengthening security in cryptographic applications. This reconfigurability allows for a significant increase in the number of challenge-response pairs (CRPs), paving the way for the design of stronger PUFs. The proposed design presents security metrics very close to the ideal values, comparable to those of other PUFs designed in the same technological node and with a high reliability to variations in operating conditions. The results underline the potential of reconfigurable sense amplifiers in the development of high-performance PUFs for secure and resilient hardware security solutions.

ABSTRACT. The design and implementation of lightweight-oriented ciphers on hardware is an ever more important topic in Internet of Things (IoT) given the increasing abundance of devices needing secure communication in our modern society. ASCON was selected in 2023 as the new standard algorithm with authenticated encryption with associated data (AEAD) for lightweight applications by the National Institute of Standards and Technology (NIST). This paper offers a full bibliographic recollection of hardware implementations, attacks and countermeasures published about ASCON. From which ASCON has proven its simplicity allows many implementation design approaches to achieve great performance while staying lightweight. However, its unprotected implementations are not safe from hardware attacks, some of the published attacks even being able to dodge countermeasures. ASCON is expected to thrive as the new standard in its field, although further work is required in the development of secure implementations before it does so.

ABSTRACT. Implementation attacks are a serious threat in the field of cryptography and the IoT. One particular type of implementation attack is Fault Injection attacks (FIA). These attacks aim to modify the functionality of a certain cryptographic scheme by altering the value of certain bits or bytes inside the electronic circuit. Differential Fault Analysis (DFA) is a technique that exploits these introduced faults to retrieve sensible information about the cryptographic algorithm, like the secret key. There are several ways to perform an FIA, one of them is the electromagnetic FIA, which aims to insert faults in a circuit by generating an electromagnetic pulse (EMP) to induce Foucault currents inside the chip that affect the components inside. In this paper, a methodology to find the optimal locations to perform an electromagnetic FIA and test it in two circuits is presented: The first one is an implementation of a single S-Box of the Advanced Encryption Standard (AES) algorithm and the second one is a full implementation of the AES, both on an Artix-7 FPGA. Both examples show that inserting several types of faults that the DFA literature uses to break the cipher is possible.

ABSTRACT. Transceivers built to modern communication standards tend to be as digital as possible, including the radio frequency stages. This forces the transmitter's digital-to-analog converters (DACs) to have high bandwidth. DACs based on sigma-delta (SD) modulation represent a good choice in modern digital technologies, as they have a simple analog circuit with limited precision requirements. However, the oversampling and technology's speed limitations impose serious limitations on digital SDM design. In this sense, Time-Interleaving (TI) allows the designer to balance complexity and speed by replacing the original SDM architecture with M parallel paths clocked at a frequency M times lower. The M outputs of the TI architecture are then multiplexed into a single high-speed stream and converted to analog using a single DAC. This article explores the possibility of using low-speed M DACs by means of analog multiplexing. The experimental results provided show that this is a good solution that achieves better performances than using a dedicated high-speed DAC.

ABSTRACT. Radio Frequency Identification (RFID) tags face inherent limitations in power delivery and communication range. Ultrahigh Frequency (UHF) offers extensive reach but microwatt power transmission, while High Frequency (HF) boasts better power delivery but suffers from restricted range. EPC UHF air protocol is very suitable for semi-passive RFID used as a sensor node in Internet of things (IoT) applications thanks to its backscattering ability reducing power consumption and allowing to achieve a high transmission range. But the low power delivery inherent in UHF often requires another power source. EPC standards also provide a HF protocol which can be used for better power delivery. This paper will investigate the potential gains of a dual frequency implementation through both EPC HF and UHF protocols and includes an FPGA implementation to demonstrate performance.

ABSTRACT. In this work, the novel Intelligent Engines of the Versal Adaptive Compute Acceleration Platform (ACAP) from AMD (formerly Xilinx) are evaluated for Digital Signal Processing (DSP) applications. Different configurations of Finite Impulse Response (FIR) filters and Fast Fourier Transforms (FFTs) have been used as benchmarks. The Intelligent Engines comprise the new DSP blocks generation (DSP58) and the Adaptative Intelligent Engines (AIEs). As FIR filters and FFTs are core units in almost all DSP algorithms, this benchmark is of great value in understanding the best way to implement DSP algorithms on the new devices family. A comparison of several implementations using the Programmable Logic (PL) and DSP blocks of Zynq Ultrascale+ and Versal families, as well as the scalar and vector units of the Versal’s AIEs, is provided. Throughput, latency, power consumption and hardware cost are measured as key performance indicators for the algorithms under test. Results highlight the Versal architectural advantages in optimizing compute-intensive applications and its potential in terms of throughput, power and resources efficiency. The outcomes also provide valuable insights into the optimal configurations for DSP algorithms, depending on the used data types, filter taps, FFT length, as well as the latency, throughput, power and resources constraints of the target application.

ABSTRACT. In this study, cutting-edge FPGA-based Physical Unclonable Functions (PUFs) are analyzed and compared. We present measurements results on some of the most popular FPGA-oriented weak PUF architectures taken from the litera- ture, in order to compare them in terms of statistical perfor- mance, resources usage, and the different tradeoffs achieved. Six PUF primitives, namely the DD-PUF, the NAND-PUF, the XOR-PUF, the PICO-PUF, the TERO-PUF, and the SS-RO-PUF have been implemented on the same AMD-Xilinx Artix-7 FPGA device, and measurements on 16 FPGA boards are provided for the comparisons. An evaluation of performance variations under different supply voltage and temperature conditions is presented. The statistical performance of the different PUFs is assessed by using the National Institute of Standards and Technology (NIST) tests to quantify the achieved randomness. The comparison is based also on a Figure of Merit which accounts for the tradeoff between statistical performance and resources usage.

ABSTRACT. This paper introduces a novel subthreshold voltage reference circuit designed for low-power applications that require high stability and reliability. Unlike traditional designs, this circuit operates in weak inversion, significantly reducing power consumption while ensuring robust performance through a unique Proportional To Absolute Temperature (PTAT) current generation mechanism complemented by a negative feedback loop. Thorough theoretical analysis and simulation validate the design’s ability to maintain ultra-low power consumption without compromising output stability under varying environmental conditions.

ABSTRACT. A fully-differential single-stage class AB operational transconductance amplifier (OTA) is presented. The OTA features improved large-signal and small-signal performance due to the combined use of a non-linear current mirror and partial positive feedback at the active load. The amplifier operates in weak inversion, leading to reduced power consumption. Measurement results of a test chip prototype fabricated in a 180-nm CMOS process are presented, showing a GBW of 45 kHz and a SR of 0.23 V/µs for a load of 160 pF and a supply current of 1µA drawn from ±0.45 V power sources. The silicon area employed is just 1500 µm2.

ABSTRACT. Current references constitute fundamental building blocks in many analog and mixed-signal circuits. Their primary purpose is to provide a precise and accurate current, which in turn establishes the operating point for other circuit components. In this work, we delve into the essential concepts behind designing CMOS integrated current references, specifically focusing on the conventional β-multiplier reference topology. Key aspects, including VDD sensitivity, temperature coefficient, and start-up considerations, are thoroughly discussed.

ABSTRACT. Very Long Baseline Interferometry (VLBI) techniques have become crucial in radio astronomy and geodesy due to the major improvements that they provide to the observations’ outcomes, at the expense of requiring a significant computational load to implement the corresponding processing in real time. The devices responsible for these digital signal processing tasks in the application field, mainly based on Field-Programmable Gate Arrays (FPGAs), are known as Digital Backends. Currently, the costs coming from the state-of-the-art digital backends are high and their FPGA designs either require expensive software licenses to be involved, or they are released as proprietary solutions. This work proposes a novel SoC (System-on-Chip) architecture, based on a Xilinx Zynq device, for a digital backend focused on VLBI applications. The architecture is capable of managing the acquisition stage at the required data rates, and packing data in the well-known VDIF format to upload them. By offering a low-cost open-source architecture, it becomes a suitable solution for dissemination purposes, as well as for specific research fields. Furthermore, the system has been successfully validated with its implementation and test in some preliminary experimental setups.

ABSTRACT. High-Performance Computing (HPC) scientific applications require linear and eigensolvers, and the growth in the size of linear systems has led to the broad use of iterative projection methods, which have lower memory occupancy than direct methods, but suffer from roundoff errors. Augmenting the precision speeds up convergence, but currently only software libraries support variable and extended precision Floating Point (FP) computation beyond 80 bits. We present the VaRiable and extended Precision Accelerator (VRP), a RISC-V accelerator, implemented on a System-on-Chip (SoC) using GF22FDX technology. It supports FP computations with a number of significand bits ranging from 2 to 512. The VRP provides an average 19.25x application speedup compared to the well-known MPFR software library running on a 2400 MHz Intel Xeon processor. Furthermore, extended precision enables the convergence of linear solvers for problems that would not otherwise converge.

ABSTRACT. Recent space missions increasingly use video sensors for enhanced observation, real-time monitoring and decision making. Video cameras generate large data volumes that are challenging due to the limited transmission bandwidths, hardware and power available on space systems. On-board video compression is essential to reduce data size while limiting quality losses, thus enabling efficient transmission and storage. This works presents a low-complexity H.264 compliant output subsystem. This system is able to autonomously generate a correct compressed bitstream. An area-optimized CAVLC entropy coding stage is included in the proposed architecture. Results demonstrate that the entropy coder is able to manage throughputs of up to 0.78 Macroblocks/s while keeping resource utilization at minimal levels (0.63% LUTs, 0.28% FFs, no BRAMs) on a Xilinx Kintex UltraScale XCKU040 FPGA.

ABSTRACT. Digital logic is typically tested by means of the scan chain methodology. Scan test procedures often need to be applied with different configurations (e.g., selectively activating certain clock domains or bypassing memory cores), which usually are dynamically set by means of functional or dedicated interfaces (e.g., IEEE 1149.1 JTAG). In addition, it may be useful to read some functional device data during the scan operation. This paper describes a novel approach for accessing in write or read mode some specific signals during the scan test procedure, employing the same protocol used for controlling scan chains and thus easing test generation and application.

ABSTRACT. MEMS microphones for human-to-machine interface applications require small, low-power readout circuits. One approach to enhance scalability is to eliminate the microphone biasing circuit. The feasibility of this approach has been demonstrated by employing a switched-capacitor-based feedback to a voltage-controlled oscillator. The resulting capacitance-to-digital converter offers a wide input dynamic range, exceeding the microphone requirements. This manuscript proposes a further improvement: the oscillation frequency changes in accordance with the difference between a sensing and a reference capacitance. This approach provides two main advantages. Firstly, it compensates for the parasitic capacitance, which reduces conversion sensitivity. Secondly, it allows trading surplus dynamic range for an increase in signal-to-noise ratio at the same power consumption.

ABSTRACT. This paper presents the design of a bottom-sampling 762ksps 13.92-ENOB capacitive SAR Analog-to-Digital Converter with embedded autocalibration tailored for medical applications. The IP has been developed using a HCMOS9A 130nm technology from STMicroelectronics, but has been designed using the HCMOS9A GO2 option which only includes 500nm minimum length MOS and require a 1.8V supply. The proposed Converter achieves high resolution and speed, fulfilling the stringent demands of the PPG (photoplethysmogram) channel which requires at least 14-bit resolution and power-saving features such as the ability to turn OFF during inactive periods. The IP exhibits an average power dissipation of 4.86mW per conversion from 1.8V supply and an area employment of 0.806mm2. Simulation results have shown linearity and noise performances of a 14-bit converter, proving the goodness of the design. An auto-calibration technique improves the ADC’s linearity up to 16 bits, ensuring that INL does not degrade the ENOB.

ABSTRACT. The recording of extracellular field potentials from cardiac tissues or cardiomyocytes can provide relevant information for the study of cardiovascular diseases and the effects of drugs. Cardiac field potentials are commonly acquired using commercial systems based on microelectrode arrays, which are expensive and lack flexibility, thus precluding a more extensive use in cardiac research. In this work, an easily configurable, open-source system is presented, which is based on a modular and flexible architecture. The proposed system offers a customizable and low-cost solution that could enable greater accessibility to electrophysiological studies of cardiac cells and tissues.

ABSTRACT. Fast Fourier Transform (FFT) is a necessary and widely used algorithm in frequency-domain image processing, and the iterative calculation of 2D FFTs and iFFTs (inverse Fast Fourier Transform) is commonly applied. The general sequence of the global calculations often implies reiterative processes of data loading and storing. On the other hand, the detection-in-frequency split-radix 2-4 FFT has advantages in terms of resources and latency, compared to the radix-2 or the radix-4 schemes. In this way, a hardware architecture for frequency-domain image processing is proposed here, where a split-radix 2-4 multi-path delay commutation architecture (MDC) FFT structure with four parallel inputs and outputs is designed to achieve 100% resource utilization. In addition, a dynamic ping-pong switching between the FFT and the iFFT is designed to implement a non-stalled stream on calculation by means of a feedback path without reloading data. Furthermore, as for the conjugate symmetry of the transfer function, the processing order of the image is designed to reduce the number of calculations or data loading. Comparing with other architectures, the proposed one requires less buffers, complex multiplications and complex additions, whereas it also provides a low latency and a wide range of sequence lengths. In this way, in a frequency-time domain processing for an image, only 2 loads and 2 stores are required per iteration because of the dynamic ping-pong switching.

ABSTRACT. Analog-to-Digital converters (ADCs) are a crucial part of many electronic systems, such as communications transceivers or smart sensors for computing-on-the-edge IoT. The design of these converters is strongly constricted by the final application, producing different structures and configurations. ADCs based on VCOs (Voltage-Controlled Oscillators) are being increasingly used due to their simplicity and all-digital structure. VCO-ADCs are conformed by an Analog-to-Frequency converter (i.e., the VCO) and a Frequency-to-Digital converter (FDC) which usually consists of a digital circuit. There is a wide range of possible implementations for FDCs, always focused on improving power consumption, area and noise effects. In this work, an analysis on three different FDCs in 40nm technology standard cells is presented, aiming towards the comparison of their performance. The first design is based on a FDC previously designed by the authors. The second design is based on a circuit found in the literature. Finally, the third design is based on the second but with some new changes. Comparing these designs can give an idea of the application they are best suited.

ABSTRACT. This paper proposes an innovative device-level solution for Single-Event Latch-up (SEL) protection. It introduces a programmable, adaptive, and integrated protection mechanism that offers more targeted and higher protection compared to system-level solutions. The proposed monolithic mixed-signal integrated circuit continuously monitors the current demanded by the Device Under Protection (DUP). If the current exceeds a specific threshold, the circuit disconnects the DUP from the power supply. The circuit's dynamic threshold determination adapts to variations caused by radiation and aging, ensuring the threshold is high enough to prevent unnecessary shutdowns and low enough to protect the DUP's integrity. This approach allows the use of Commercial Off-The-Shelf (COTS) components in space electronics, reducing costs while providing protection against critical SEL effects without special radiation hardening techniques.