ABSTRACT. A critical challenge in IC design is ensuring the seamless integration of hardware and software components. Traditional HDL simulators, which are often slow and provide low-level analysis tools, are not always effective for simulating the software component of processor-based systems. To address this, we focus on using higher levels of abstraction to improve practicality in educational settings. This work presents an Interactive Co-Simulation framework that enhances students' understanding of computer architecture concepts typically obscured by hardware intricacies. Our framework facilitates a unified environment for iterative design, enabling detailed analysis and generation of reports and traces to identify system performance and bottlenecks. By prioritizing analysis features over performance, our framework serves as a valuable tool for educational purposes and comprehensive examination of system interactions.

ABSTRACT. Performing AI inference ubiquitously requires energy-efficient, small footprint and highly reliable processing devices. Heterogeneous processing architectures combining customized CPUs with domain specific coprocessors can provide a good trade-off between computational efficiency and application flexibility for edge AI deployments while shortening development times compared to full custom application-specific processor designs. Following the impulse for the European sovereignty in the microelectronics field, in this work we propose the use of a RISC-V based open-source hardware platform and Free/Libre and/or Open Source (FLOS) Electronic Design Automation (EDA) tools to evaluate the performance of different coprocessor integration options in a System-on-Chip (SoC) prototyped on FPGA. We tested four integration options (XBUS, Stream, CFS and CFU) to obtain precise data that will allow making the correct design decisions for the future development of integrated devices for high-performance AI at the edge.

ABSTRACT. This work shows the results of an implementation of an AI application on a RISC-V processor with a Vector Processor Unit (VPU) using TensorFlow as a common tool. We used two commercial SoCs that uses RISC-V cores that implement the RISC-V vector extension (RVV) with a width of 128 and 256 bits and they are able to run a standard Linux distribution. The developed work application classifies clouds on satellite image and is designed to be deployed aboard satellites to improve their performance and yield. In this work we adapt TensorFlow to take advantage of the vector instructions present in the system and improve computing times. First, the performance of the vector unit with different data-types, word widths and length of the vectors has been outlined and characterized to be able to optimize TensorFlow with said parameters and later the entire framework is vectorized to take advantages of this processor units.

ABSTRACT. In Embedded and Cyber-Physical Systems (E&CPS) the functional and temporal interactions between the digital and physical parts are crucial. In these systems, most of the functionality is implemented by software deployed on heterogeneous, distributed platforms so its performance largely affects the whole E&CPS behavior. Their HW/SW co-design requires fast and accurate simulation tools capable of evaluating the performance of each platform configuration for the applications selected while minimizing software porting needs. Host-compiled simulation avoids porting, but has limitations for practical industrial application due to the difficulty of extracting and modeling the microarchitectural details of the target platforms. To solve that, this work proposes replacing the traditional approach of generating ad-hoc code annotations with all processor internal details by the use of neural networks. Training the neural network for a specific processor enables considering its internal details when estimating the cost of executing each basic block of the software in the target processor.

ABSTRACT. Advancements in printing technologies now enable the embedding of sensors within composite parts for aeronautical applications. The sensor characteristics have been meticulously analyzed to align with the requirements of the targeted phenomena, particularly springback. In this study, a Design of Experiments was conducted to generate significant data for training a surrogate model capable of predicting distortions in L-shaped structures, eliminating the need for dependence on Finite Element Method (FEM) software. Utilizing the acquired insights, the paper further investigates the experimental study on sensor requirements encompassing location, operational temperature range, sensing capabilities, and signal acquisition during curing processes. The equipment and experimental setup are introduced to elucidate additional requirements for future research endeavors. This paper successfully presents a methodological approach for the development and characterization of sensors tailored for the curing of composite parts.

ABSTRACT. RRAMs operate based on resistive switching phenomena within several structuring technologies, enabling reversible switching between high and low resistance states with electrical stimuli. UGR-VCMTCF model developed at Granada University, which is based on the Stanford-PKU model, extends its flexibility. In this paper, we improve this model to adjust the switching behavior to a real TiN/Ti/HfO2/W RRAM device from IMB CNM. Our improvements fit the nominal characteristics of the device, introduced more flexibility in some parameters and modified the variability scheme. The comparison between the empirical and the simulation outcomes demonstrate a better match.

ABSTRACT. This document proposes the novel application of a nanoelectromechanical system (NEMS) comb drive in the use of analog computations, specifically multiplication. Through the use of simulations, we demonstrate the feasibility of performing simple, scalar multiplications of analog values using a single NEMS comb drive. Using state-of-the-art NEMS technology, we find that a single NEMS comb drive can reach a theoretical computational efficiency of over 4,000 TOPS/W, with a throughput of over 600,000 multiplications per second. This is ten times higher than the previous maximum efficiency demonstrated by analog multipliers in the literature.

ABSTRACT. A common approach when designing a memristor-based Physical Unclonable Function (PUF) is to quantize directly observable electrical quantities. While this is a straightforward approach, it suffers from a problem: It remains unclear which effects underly the extracted entropy. As a consequence, it is hard to counteract detrimental effects, e.g. bias and correlation, due to their unknown causes, and to optimize measurement and quantization techniques. This work provides the foundation to base a PUF on physical model parameters extracted from I–V curve measurements, using the reading branch of a BiFeO3 (BFO) memristor as an example. The work outlines possible avenues for deriving reliable and high-entropy PUF responses from such parameters in general and concretely for BFO memristors using experimental data from a laboratory sample with 129 memristive cells.

ABSTRACT. Bifacial panel strings generate energy from both the incident and albedo radiation. The variability in albedo radiation on each module, based on its position, emerges as a primary source of mismatch, alongside factors such as partial shading, orientation, and dust accumulation. To optimize power extraction despite these mismatches, DC-DC converters have proven more effective than bypass diodes. This paper introduces a buck-boost DC-DC converter topology, implemented with GaN transistors and operating at a switching frequency of 1 MHz, that execute differential power processing (DPP). GaN switches allow to achieve converters with high compactness and efficiency thanks to their characteristics such as the channel high electron mobility, the wide bandgap and the bidirectionality. The converter has been designed and simulated to maximize power extraction in a bifacial solar panel comprising three series-connected bifacial modules, mitigating the different effects of albedo radiation and mismatches on each module.

ABSTRACT. Gallium Nitride (GaN) semiconductor technology is currently undergoing continuous development due to its promising electrical and physical characteristics, mainly for high power switching applications. As a result, there is a growing demand for circuits implemented in this technology, necessitating monolithic implementation to leverage integration advantages. The production of integrated devices in GaN technology requires the development of auxiliary circuits, both digital and analog, to accompany the power circuits. One limitation of this technology is the unavailability of the P-type transistor adopted in traditional analog and digital design. In this paper basic digital circuits have been designed with the aim to realize digital memory circuits for storing data. The main objective is to limit the whole power consumption with ad-hoc solutions. Digital and analog basic circuits have been examined and optimized with regard to power consumption-efficiency and robustness to power supply and temperature variations. A new shift register topology designed in GaN monolithic technology of STMicroelectronics has been designed and simulated.

ABSTRACT. This paper presents a solution for the PWM generator of a current-mode control feedback for switching power converters. The circuit was designed in a 0.5-µm GaN technology and is suitable for fully integrated high-performance power converters. The switched-capacitor technique was extensively used to overcome GaN technology limitations and provide a robust implementation against process tolerances and temperature variations. System simulations of the current-mode control used in a flyback dc-dc converter are provided, which show the effectiveness of the proposed solution. The circuit exhibits an overall current consumption as low as 2 mA while operating with a 6-V power supply.

ABSTRACT. This paper aims to validate a GaN HEMTs-based three-phase and three-level ANPC inverter, evaluating the performances of the GaN devices employed in the designed prototype. Critical issues of the design stage are presented and the GaN HEMTs’ driving is analysed and discussed in detail. Thermal analysis is reported together with the preliminary tests conducted on the single-phase ANPC power cell.

ABSTRACT. In this work we present the design, additive manufacturing (AM) using 3D printing, and characterization of very compact 2-way Wilkinson power dividers/combiners for application in the sub-GHz RF band. We employ two helical-microstrip transmission line segments to implement the proposed Wilkinson devices. The fabricated components are then compared with a reference Wilkinson device implemented using standard PCB technology, working at the same central frequency. The results demonstrate that the proposed 3D-printed devices achieve similar performance in terms of port matching and bandwidth compared to the reference design, but with a significant reduced area.

ABSTRACT. A new topology for a three-stage Operational Transconductance Amplifier (OTA) in flexible-substrate process is presented. The amplifier is designed in the Cadence environment using thin-film transistors (TFTs) and is validated through post-layout simulations. When loaded with 50-pF capacitive load, the OTA exhibits 52-dB gain and 1.19-MHz gain-bandwidth product with 3-V power-supply voltage and 186-$\boldsymbol\upmu$W power dissipation. The OTA is compared to other flexible TFT amplifiers in terms of bandwidth, drive capability and power dissipation. It shows the best figure-of-merit with performance that ranges from 8.57X to 1750X compared to other state-of-the-art solutions.

ABSTRACT. In this work, the fabrication of a novel configuration for an ohmic contact on p-doped SiC substrate, employing laser treatment instead of the conventional oven treatment, is analyzed. Test patterns made by Ti rectangular contacts on p-SiC were fabricated. The overall structure is treated with an excimer laser, employing different energy densities and number of shots. In particular, the laser energy density ranges from 1.0 J/cm2 to 3.8 J/cm2 and the number of shots from 1 to 10. The analysis shows that the system begins to exhibit an ohmic behavior when exposed to laser energy densities of 3.6 J/cm2 and above. Also, the number of shots influences the electrical behavior, with higher values leading to losing the linearity in the I-V curves. The best performance, characterized by the lowest resistivity value, is observed with an energy density value of 3.8 J/cm2 and 1 laser shot applied. Under these conditions, the resistivity value is 1.4x10-2 Ωcm, or in terms of specific resistivity 7x10-5 Ωcm2, the contact resistance is 152 Ω and the sheet resistance is 656 Ω/sq. This work enables the achievement of an ohmic contact between Titanium and p-doped SiC, overcoming the challenge of using high temperature oven treatment.

ABSTRACT. The low and medium complexity SoCs used for sensing and networking in Critical Sectors, like Energy, Industry, Transportation, and A&D, are typically built using mature 65-22nm USDM technologies. The demand for more specialized, secure, and safe devices is growing due to the high specialization demanded by these strategic sectors. In this context, in the R&D project SoC4cris, we are working on a SoC subsystem based on a 32-bit RISC-V for 65-22nm USDM technologies that could be easily adapted to new SoCs oriented to these sectors.

The testing stage of the ASIC, once it is manufactured and in prototype stages, is very important. Thus, the main aim of the presented work is to automate this testing stage by developing a flexible and cost-effective scan chain Design-for-Test (DfT) verification method that looks for flexibility and facilitates the testing of the ASIC. Furthermore, this method will allow us to test communication standards typically used in the industry.

As the level of integration in digital ICs increases and transistor size decreases, the post-silicon verification of the chips becomes critical. However, the usage of complex Automatic Test Equipment (ATE) is highly expensive, and sometimes very inflexible for little production volumes or multi-project wafers, which complicates its verification. In this paper we propose a lowcost, highly flexible ATE, capable of testing DUTs that integrate Scan Chain as Design-for-Test (DfT) architecture.

Our ATE can be used for little production volumes and prototypes where the verification time is not critical, but a exhaustive testing is needed. Together with a SW library based on Python, it is fast and easy to deploy, maintain and modify. Furthermore, it targets a wide range of DUTs as its working frequency can be dynamically modified by user.

ABSTRACT. The effect of space radiation on deterministic electronic circuits is a well researched topic. However, the statistical quality of non-deterministic numbers generated by True Random Number Generator (TRNG) circuits, critical for secure communication in space applications, has not been extensively explored in literature. This paper presents implementation of a resource-optimized Mixed Mode Clock Manager (MMCM) based TRNG circuit on Xilinx Field Programmable Gate Arrays (FPGA), along with the results of statistical tests. The advantage of this study is the execution of Single Event Effects (SEE) tests, enabling a detailed examination of the TRNG circuit's performance under space radiation. Additionally, based on SEE test results, the TRNG circuit is redesigned using the fault tolerant design techniques. The performance of the applied fault tolerant design technique on the TRNG circuit is examined through a repetition of SEE tests.

ABSTRACT. This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.

ABSTRACT. This paper presents a fully-integrated CMOS contactless temperature sensor for low power applications. The sensing element is a TMOS thermal sensor, which is a micromachined suspended CMOS transistor made in a standard 130 nm CMOS-SOI process. The TMOS sensor produces a signal that is linearly related to the difference between the temperature of a non-contact object and the ambient temperature. The Readout interface circuit, realized in 130 nm CMOS process, supplies the bias current to the TMOS and amplifies its signal using a differential integrator, then a 12 bit SAR ADC converts the signal to digital domain. It has been designed to limit technology process dependency and mismatch variations. To obtain a measurement of the object temperature, the digitized TMOS signal is added to the digitized signal from a BJT based temperature sensor. The ASIC Readout circuit and the TMOS were mounted in the same package and measured, demonstrating an accuracy of ±0.2°C in detecting the object temperature from 35°C to 42°C considering the ambient temperature from 10°C to 40°C. A power consumption of 18 µW has been measured, making the circuit suitable for portable and wearable applications.

ABSTRACT. This paper is conceived as an update of integrated electrodebased systems involved on Stem Cells (SC) differentiation processes based on electric stimulation, actual and future progress. These techniques are applied in different biological and medical protocols with varied objectives: cell linage derivation, tissue engineering, cellular therapy, cancer research, cell motility, etc. The general procedure of SC electric stimulation tries to emulate the biological processes by applying an electrical signal to the cell culture, and to evaluate the cell response to it. Basically, cell metabolism is electrically sensitive, answering in some manner to the applied stimuli. What is really happening at the cell is not well known actually, but it is clear that the ion density changes, positive or negative, at the cell membrane neighbourhood must excite in some way the cell metabolism (receptors) activating its “differentiation” as response to the electrical stimulus. In this review, we will try to progress towards a compilation of the proposed system setups, and specifications required, to find and know the local conditions or variables at cell environment that activate differentiation processes. Two features of stimulation (STI) will be reviewed: the setup employed for STI; and the circuits for STI. The nexus between both are the electrodes, as required interfaces to apply electric signals to cell cultures; so we will focus our interest on integrated Micro-Electrode Arrays (MEAs) realizations mainly, and the problems and specifications imposed by its use. This approach will allow to centre this review on fully integrated realization of electrodes, at the same scale of cell sizes.

ABSTRACT. The design of wireless sensor systems requires low power consumption to ensure high autonomy and long lifetimes, especially when they are used in remote locations. This article analyzes the power consumption of a data processing system for a multi-sensory instrument designed to study meteorological conditions on planetary surfaces. Three system architectures have been developed, two of which are based on software-hardware co-design. These architectures aim to optimize performance, resource usage, and processing speed. The energy consumption of these architectures has been measured and compared in this work.Furthermore, low power consumption techniques have been implemented in these architectures, such as reducing the clock frequency where possible. The effect of these techniques on power consumption has been analysed.

ABSTRACT. This paper proposes switched-capacitor AC-DC converters driven by highly resistive energy transducers. Unlike a previously reported input-voltage-tracking method, the number of capacitors (N) and on-time (T1) are fixed at certain values in the proposed design, which can be determined using optimum design theory for the DC-DC switched-capacitor voltage-down converter driven by a highly resistive DC energy transducer with a DC voltage amplitude as high as the RMS value of the amplitude of the AC voltage. This fixed method is suitable for low-power applications aiming to maximize output power. To prevent reverse current with the fixed method, a suspending circuit or a Schottky barrier diode is employed. Model equations, including the loss due to the bottom plate parasitic capacitance, reveal that the fixed operation requires 66% fewer switches and 66% fewer control signals, while achieving 60% higher output power compared to the tracking method. SPICE simulations and measurements validate the effectiveness of the proposed fixed method on the entire power efficiency.

ABSTRACT. A novel scheme based on a modified Dickson charge pump topology (DCP), is presented as an effective solution to achieve optimized power conversion efficiency. In this solution, currents of the clock generator are directly conveyed to the DCP, with the result of reducing the power consumption of the drivers and the oscillator. A prototype of the design was implemented in a standard 130-nm CMOS process and its operation was tested and compared to the previous arts.

ABSTRACT. This paper presents model equations of a Cross-Coupled Charge Pump (CC-CP) operating in steady-state conditions, based on a Thevenin equivalent circuit. The model is derived under the assumption of zero net charge transfer of the circuit dynamics. Equations for the mean voltage values of each fly-capacitor are obtained. These equations are useful for the proper sizing of the switching and capacitive elements, avoiding unnecessary area overhead of transistors while guaranteeing functionality. The model also provides ripple equations for both the Fast and Slow Switching Limits. The models are validated against ideal Spectre simulations of a CC-CP and an implementation in 28~nm FDSOI technology.

ABSTRACT. Aging processes in batteries are receiving more and more attention due to the problems they generate in their performance and safety. In this context, mathematical models are especially useful in allowing predictions of the behavior of batteries in the medium and long term and being able to prevent unwanted situations from occurring. However, the accuracy of these predictions depends largely on the battery's usage history, so it would be desirable to have a specific model for each battery that takes that history into account. This could be achieved by building a digital twin for each battery, which would be subjected to the same operating conditions as the battery in real time. This digital twin would allow much more accurate predictions of the battery's status, optimizing its use and opening new possibilities for its reuse in other applications. This article proposes the hardware implementation of a battery model as a first step to obtain digital twins capable of operating in real time, in low-cost and low-consumption reconfigurable devices.

ABSTRACT. Modern power conversion applications require increased computation power. Recently, an optimal fault-tolerant control technique for cascaded H-bridge power converters, utilizing a compute-intensive algorithm, was presented. However, limitations of conventional computation platforms impose serial constraints on the real time operation of such algorithms. Novel artificial intelligence (AI) engines emerge as excellent candidates for these compute-intensive applications. This article evaluates the novel AI engines of the Versal Adaptive Compute Acceleration Platform (ACAP) from AMD (formerly Xilinx) for accelerating the aforementioned compute-intensive algorithm for the real-time control of the power converter. The algorithm is implemented in the Adaptative Intelligent Engines (AI Engines) of Versal ACAP family with several heterogeneous configurations. Performance is compared with implementations in the Processing System (PS) and the Programmable Logic (PL) of a Zynq-7000 family device, considering throughput, latency, power consumption and resources utilization. The obtained result highlight the superiority of the Versal architectural for this application and demonstrate the potential of AI engines in power converter control.

ABSTRACT. In this paper, an advanced framework for the optimizer of DC-DC buck converters, which utilizes Python for algorithm implementation and SIMETRIX/SIMPLIS for accurate DC-DC converter simulation for automatic parameter sizing. The analysis focuses on achieving an exceptional 86% peak efficiency under a typical condition of 1A load current, achieved by determining optimal inductance and capacitance values ranging from 1μH to 6.6μH and from 10μF to 200μF respectively, through an automatic parametric sweep is presented. The automation for the benchmark of DC-DC converters is more efficient and valuable for high-efficiency electric vehicles and renewable energy systems, decreases the optimization time, and increases overall system performance.

ABSTRACT. The Alpha Mission, led by a consortium of Andalusian aerospace entities and universities, aims to advance technological development and innovation in the space sector by designing, manufacturing, launching, and operating the CubeSat "Alpha3." This mission seeks to analyze and mitigate the effects of space radiation on electronic systems in low Earth orbits. The paper presents the design and implementation of the Alpha3 satellite’s payload, which includes instruments to measure radiation levels and their impact on electronic components. This data will aid in developing protective measures, enhancing the reliability and longevity of future space missions. Experimental results from validation tests, including preliminary radiation testing, confirm the payload's capability to monitor and transmit critical radiation data, contributing valuable insights for the aerospace sector.

ABSTRACT. Most readout systems for integrated sensor arrays rely on time-division multiplexing of analog frontends and analog-to-digital converters (ADCs) that have sample rates much faster than the one needed for acquiring the signal bandwidth of a single sensor. This complicates the system design if the sensor array is large, as switching the active sensor at high frequencies may degrade simultaneously the overall signal integrity and power integrity. Also, if the noise bandwidth is limited by a low-pass filter, the latter may require a fast-settling mechanism to be included. Additionally, in case of a large sensor impedance, buffers need to be employed in order to cope with the significant parasitics of long interconnecting. This paper proposes an architecture of a quasi-passive Σ∆ modulator that fits in a very small area, partially because it employs only metal-oxide-semiconductor capacitors (MOSCAPs), which are known to provide the highest capacitance density inside CMOS chips. This enables the usage of one modulator per sensor while simultaneously allowing the digitized sample to be sent over a single-wire digital signal, which conclusively eases the noise margin requirements for the sensor array. Taking a pass on employing an operational amplifier, as done in conventional Σ∆ modulators, reduces the design complexity while maintaining the inherent noise shaping property of the Σ∆ ADC. The proposed ADC is implemented and simulated in a 0.13 μm technology, fits in an area of under 20 × 20 μm2 and consumes 11.8 μW at 100 MSps while providing an ENOB of 7.19 bits at an oversampling ratio of 128.

ABSTRACT. Radio Frequency Identification (RFID) technology can be used for many purposes. Here, we propose its use to enhance the capabilities of conventional sensors, allowing them to be easily identified and read without contact. In addition, the RFID system may be used to power the sensor, eliminating the need for a battery or power supply. The proposed frontend is fully analog and includes as key elements a rectifier, a regulator, a VCO and a modulator. The designed frontend has been fabricated with a 65 nm commercial technology, occupies 0.0157 mm^2 and consumes only 22.4 nW.