AVM25: 17TH ALPINE VERIFICATION MEETING

A
Alexaj, Ondrej	Complementing Emerson-Lei Elevator Automata
B
Bjorner, Nikolaj	Arithmetic Solving in Z3
Bozga, Marius	On the Verification of Structured Parameterized Networks
Britikov, Konstantin	CHCs for every occasion
C
Chatterjee, Krishnendu	Hardware-Optimal Quantum Algorithms
D
Dacík, Tomáš	RacerF: Lightweight Static Data Race Detection for C Code
Dold, Simon	Pseudo-Boolean Proof Logging for Optimal Classical Planning
E
Eigner, Dennis	A Novel Symbolic Execution Framework for Symbolic Timing Analysis of Digital Integrated Circuits
F
Ferdowsi, Arman	A Novel Symbolic Execution Framework for Symbolic Timing Analysis of Digital Integrated Circuits
Funk, Lena	Towards Minimizing Phase Event Automata
H
Helmert, Malte	Pseudo-Boolean Proof Logging for Optimal Classical Planning
Henzinger, Thomas A.	Neural Certificates Hardware-Optimal Quantum Algorithms
I
Iosif, Radu	On the Verification of Structured Parameterized Networks
J
Jobranová, Sára	Accelerating Decision-diagram-based Quantum Circuit Simulation With Symbolic Execution
K
Kaufmann, Daniela	Verifying Arithmetic Circuits with Polynomials
Kolarik, Tomas	On User-defined Decision Guidance in SMT Solvers
L
Labbaf, Faezeh	Proof-based Space Explanation of Classifying Neural Networks
Lingsch-Rosenfeld, Marian	Software Verification Witnesses
M
Maderbacher, Benedikt	Parameterized Infinite-State Reactive Synthesis
Muroya, Stefanie	Hardware-Optimal Quantum Algorithms
N
Nordström, Jakob	Pseudo-Boolean Proof Logging for Optimal Classical Planning
O
Onderka, Jan	Computing abstract model-checking transitions using abstract interpretation
R
Rebola Pardo, Adrian	Proofs (that contain programs that contain proofs)*
Röger, Gabriele	Pseudo-Boolean Proof Logging for Optimal Classical Planning
S
Sangnier, Arnaud	On the Verification of Structured Parameterized Networks
Schindler, Tanja	Pseudo-Boolean Proof Logging for Optimal Classical Planning
Schmid, Ulrich	A Novel Symbolic Execution Framework for Symbolic Timing Analysis of Digital Integrated Circuits
Schwabe, Wolffhardt	Leveraging Partial Redundancy in Active Automata Learning
Schüssele, Frank	Witness-guided verification in trace abstraction
Síč, Juraj	Current State of String Solver Z3-Noodler
T
Thaqi, Era	A Novel Symbolic Execution Framework for Symbolic Timing Analysis of Digital Integrated Circuits
V
Vašák, Jan	Regexes with Back-References using Register Set Automata
Villani, Neven	On the Verification of Structured Parameterized Networks
Voronkov, Andrei	First-Order Proof Checking
W
Wallner, Felix	Robust by Design: SAT-based Automata Learning in the Presence of Noise
Winkler, Lorenz	Bounding Probabilistic Loop Variables using Martingales and the Optional Stopping Theorem
Z
Zavada, Ármin	Formal Verification with Configurable Execution Semantics
Zumkeller, Matthias	From Interleavings to Owicki–Gries via Empires: Certificates for Concurrent Program Verification

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