The Minimizating of Hardware for Implementation of Pseudo-LRU Algorithm for Cache Memory

EasyChair Preprint 2989

Abstract

Synthesis of logic LRU of the internal  cache memory of the central processing unit is fulfilled in case of hit, miss and filling in the lines for unit of data of the internal  cache memory. The logic models are analyzed by selecting the lines including unreliable multitude for filling and controlling logic for substitution of the lines while it was true the selected multitude by unit of data. The minimizing functions that are simple completely defined and composite not completely defined is carried out. They are switched as: L=f(B) by selecting multiple among reliable values and B⁺=f(L,B) forming the values of bits for unit LRU considering the previous state. As a result the minimum discrete realization has been obtained by suggested hardware solutions substitution policy for the algorithm of pseudo-LRU of internal associative cache memory and associative translation look –a – side buffer.

Keyphrases: LRU unit, algorithm pseudo-LRU, controlling logic, internal memory cache, translation look–a-side buffer

@booklet{EasyChair:2989,
  author    = {Vadym Puydenko and Vyacheslav Kharchenko},
  title     = {The Minimizating of Hardware for Implementation of Pseudo-LRU Algorithm for Cache Memory},
  howpublished = {EasyChair Preprint 2989},
  year      = {EasyChair, 2020}}