Download PDFOpen PDF in browserRewriting Environment for Arithmetic Circuit VerificationEasyChair Preprint no. 6629 pages•Published: December 3, 2018AbstractThe paper describes a practical, commercialstrength software tool for the verification of integer arithmetic circuits. It covers different types of adders, multipliers, fused addmultiply circuits, and some dividers  the circuits whose computation can be represented as a polynomial. The verification uses an algebraic model of the circuit and is accomplished by rewriting the polynomial of the binary encoding of the primary outputs (output signature), using the polynomial models of the logic gates, into a polynomial over the primary inputs (input signature). The resulting polynomial provides the arithmetic function of the circuit and hence can be used to extract its functional specification from the gatelevel implementation. The rewriting uses an efficient \textit{AndInverter Graph} (AIG) representation to enable extraction of the essential arithmetic components of the circuit. The tool is integrated with the popular ABC system. Its efficiency is illustrated with impressive results for large integer multipliers, fusemultiply circuits, and divide by constant circuits. The entire verification system is offered in an open source ABC environment together with an extensive set of benchmarks. Keyphrases: Arithmetic Circuits, computer algebra, formal verification
