Download PDFOpen PDF in browserExhaustive DFM Evaluation of Logic Cell Libraries via Virtual CharacterizationEasyChair Preprint 5442 pages•Date: September 29, 2018AbstractLocal layout effects create pattern dependencies at the 14nm node and below that make prediction of functional and parametric yield challenging. Because of exponential complexity of cell neighboring scenarios, pre-characterization of all patterns is impractical and silicon characterization is practically impossible. In this paper we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all unique layout patterns as a function of a specified radius of influence. By exhaustively searching for patterns, these VCVs compile pattern frequency and expose hotspot patterns for all possible cell combinations. VCV results can guide the design and selection of logic cells in a library based on their impact on DFM metrics. Most importantly, these results can be used in silicon characterization vehicles to cover all possible layout patterns. Our VCV results show how DFM quality improves at a minimal performance cost. Keyphrases: Design for Manufacturability, Layout patterns, Standard Cell Library, Virtual characterization
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