Time-Sensitive Shared Caches interferences Analysis in Multi-Core Architectures for WCET

EasyChair Preprint no. 13958, version 2

Abstract

Shared last-level caches in multicore architectures cause memory accesses to interfere with others, resulting in additional access latency. So computing the worst-case execution time (WCET) of a program necessitates an analysis of the inter-core interference, which requires determining when the accesses occur. Current approaches directly use the execution time of a program as the life cycle of its internal accesses for scalability, which can lead to a significant overestimation of the interferences. In this paper, we propose a time-sensitive shared cache interference analysis method. It estimates the execution time of a basic block relative to the start of the program based on the execution path of the program and combines it with an approximation model as the life cycle of the accesses within the block, which can effectively exclude impossible interferences and improve the tightness of WCET analysis.

Keyphrases: Mulit Core, shared cache, WCET analysis

@Booklet{EasyChair:13958,
  author = {Yixuan Zhu and Wenqi Lou and Xianglan Chen and Chao Wang and Xi Li},
  title = {Time-Sensitive Shared Caches interferences Analysis in Multi-Core Architectures for WCET},
  howpublished = {EasyChair Preprint no. 13958},

  year = {EasyChair, 2024}}