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Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology

EasyChair Preprint no. 289, version 2

Versions: 12history
6 pagesDate: June 22, 2018


This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most of the
IoT-oriented circuits and applications. The use of 3D CoolCubeTM technology enables the design of a stable 4T SRAM bitcell by using data-dependent back biasing. The proposed bitcell architecture provides a major reduction of the write operation energy consumption compared to a conventional 6T bitcell. A dedicated read port coupled to a virtual GND (VGND) ensures a full functionality at ULV of read operations. Simulation results show reliable operations down to 0.35 V close to six sigma (6 σ) without any assist techniques (e.g. negative bitlines), achieving in worst case corner 300 ns and 125 ns in write and read access time, respectively. A 6x energy consumption reduction compared to a ULV ultra-low-leakage (ULL) 6T bitcell is demonstrated.


Keyphrases: 4T bitcell, SRAM, ULV

BibTeX entry
BibTeX does not have the right entry for preprints. This is a hack for producing the correct reference:
  author = {Reda Boumchedda and Jean-Philippe Noel and Bastien Giraud and Adam Makosiej and Marco Antonio Rios and Eduardo Esmanhotto and Emilien Bourde-Cicé and Mathis Bellet and David Turgis and Edith Beigne},
  title = {Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology},
  howpublished = {EasyChair Preprint no. 289},
  doi = {10.29007/nc31},
  year = {EasyChair, 2018}}
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