Binary Multiplier Circuit Based on Vedic Mathematics

EasyChair Preprint 7455

Abstract

 In the literature, Vedic multipliers for 4-bit, 8-bit, 16-bit, and 32-bit are available, but their design involves a larger number of adders, which consumes a considerable portion of the FPGA and causes more delay during implementation. This paper presents a Vedic multiplier based on the Urdhva Tiryagbhyam sutra with certain adjustments in the technique of partial product addition to solve this problem. Xilinx Vivado tool is used to simulate the proposed design, which is written in Verilog HDL. For 4-bit, 8-bit, 16-bit, and 32-bit input, the proposed Vedic multiplier design is simulated. The proposed design's performance is compared to that of existing designs in terms of speed and LUTs. In terms of time and the number of LUTs, this Vedic multiplier has improved.

Keyphrases: Carry Save Adder, Ripple Carry Adder., Vedic Multiplier

@booklet{EasyChair:7455,
  author    = {Jerubandi Ravi Teja},
  title     = {Binary Multiplier Circuit Based on Vedic Mathematics},
  howpublished = {EasyChair Preprint 7455},
  year      = {EasyChair, 2022}}