Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate

EasyChair Preprint 2561

Abstract

The fundamental operation in most digital circuits is binary addition. It is very important in VLSI designs to minimize the area, delay and power. In carry skip adder, data to be added is divided into blocks and the carry is skipped though these blocks thereby reducing the time to propagate carry.

Basic operation in every digital computers is addition and subtraction, multiplication is implemented using repeated adding and division by repeated subtraction which can be programmed. Adders are not only used in ALUs(arithmetic logic units), but also in many circuits used in of the processors including digital signal processors and general purpose processors. So improving speed, area and energy parameters of adders will improve the performance of whole ALU. Different types of adders are available in the market such as ripple carry adder, carry look ahead adder, carry select adder, carry skip adder etc.  In this paper,  two different Carry skip adders are compared and slightly modified version of both architecture is proposed that can increase the speed. It incorporates a carry feed forward block to the existing structures so that the delay can be reduced. The proposed architecture can be used for high speed application by the cost of area. The adders compared in this paper are CSKA (conventional carry skip adder) and CI- CSKA (Concatenation Incrementation Carry skip adder), and the proposed models are CFF-CSKA (Carry Feed Forward CSKA) and CFF-CI-CSKA.

Keyphrases: CSK, MUX, Transmission gate

@booklet{EasyChair:2561,
  author    = {Ashutosh Pandey and Harshit Singh and Vivek Kumar Chaubey and Utkarsh Jaiswal},
  title     = {Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate},
  howpublished = {EasyChair Preprint 2561},
  year      = {EasyChair, 2020}}