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Implementation of Edge Detection Algorithm Using Nexys 4 FPGA

6 pagesPublished: August 5, 2017

Abstract

Image processing requires extensive computation and usually done on Personal Computer or CPU. Due to its sequential processing method of Image processing or CPU task takes long time to get desire output. However FPGAs can be one of the options to speed up image processing without increasing the clock speed. One of the main features of FPGA is allowing parallel processing which speed up the processing of Image and get desire output in limited time-bound. In this paper, Digilent Nexys 4 XC7A100T-1CSG324C FPGA is used to implement the edge detection operation on image. The Sobel algorithm is used to detect the edge in an image and is implemented on FPGA using Hardware Description Language (VHDL).

Keyphrases: edge detection, FPGA, image processing, Sobel, SoC

In: Ajitkumar Shukla, J. M. Patel, P. D. Solanki, K. B. Judal, R. K. Shukla, R. A. Thakkar, N. P. Gajjar, N. J. Kothari, Sukanta Saha, S. K. Joshi, Sanjay R. Joshi, Pranav Darji, Sanjay Dambhare, Bhupendra R. Parekh, P. M. George, Amit M. Trivedi, T. D. Pawar, Mehul B. Shah, Vinay J. Patel, Mehfuza S. Holia, Rashesh P. Mehta, Jagdish M. Rathod, Bhargav C. Goradiya and Dharita K. Patel (editors). ICRISET2017. International Conference on Research and Innovations in Science, Engineering and Technology. Selected Papers in Engineering, vol 1, pages 428--433

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BibTeX entry
@inproceedings{ICRISET2017:Implementation_of_Edge_Detection,
  author    = {Chintan Patel and Ronak Vashi and Anish Vahora},
  title     = {Implementation of Edge Detection Algorithm Using Nexys 4 FPGA},
  booktitle = {ICRISET2017. International Conference on Research and Innovations in  Science, Engineering and Technology. Selected Papers in Engineering},
  editor    = {Ajitkumar Shukla and J. M. Patel and P. D. Solanki and K. B. Judal and R. K. Shukla and R. A. Thakkar and N. P. Gajjar and N. J. Kothari and Sukanta Saha and S. K. Joshi and Sanjay R. Joshi and Pranav Darji and Sanjay Dambhare and Bhupendra R. Parekh and P. M. George and Amit M. Trivedi and T. D. Pawar and Mehul B. Shah and Vinay J. Patel and Mehfuza S. Holia and Rashesh P. Mehta and Jagdish M. Rathod and Bhargav C. Goradiya and Dharita K. Patel},
  series    = {Kalpa Publications in Engineering},
  volume    = {1},
  pages     = {428--433},
  year      = {2017},
  publisher = {EasyChair},
  bibsource = {EasyChair, http://www.easychair.org},
  issn      = {2515-1770},
  url       = {https://easychair.org/publications/paper/g7xM},
  doi       = {10.29007/rckt}}
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