Efficient Simulation for Hardware Model Checking

11 pages•Published: May 26, 2024

Abstract

Simulation is an important aspect of model checking, serving as an invaluable pre- processing step that can quickly generate a set of reachable states. This is evident in model checking tools at the Hardware Model Checking Competitions, where Btor2 is used to represent verification problems. Recently, Btor2MLIR was introduced as a novel format for representing safety and correctness constraints for hardware circuits. It provides an executable semantics for circuits represented in Btor2 by producing an equivalent program in LLVM-IR. One challenge in simulating Btor2 circuits is the use of persistent (i.e., immutable) arrays to represent memory. Persistent arrays work well for symbolic reasoning in Smt but they require copy-on-write semantics when being simulated natively. We provide an algorithm for converting persistent arrays to transient (i.e., mutable) arrays with efficient native execution. This approach is implemented in Btor2MLIR, which opens the door for rapid prototyping, dynamic verification techniques and random testing using established tool chains such as LibFuzzer and KLEE. Our evaluation shows that our approach, when compared with BtorSim, has a speedup of three orders of magnitude when safety properties are trivial, and at least one order of magnitude when constraints are disabled.

Keyphrases: btor2mlir, model checking, simulation, verification

In: Nikolaj Bjorner, Marijn Heule and Andrei Voronkov (editors). Proceedings of 25th Conference on Logic for Programming, Artificial Intelligence and Reasoning, vol 100, pages 136--146

Links:	https://easychair.org/publications/paper/FDRF
	https://doi.org/10.29007/rdbb