Days: Monday, October 30th Tuesday, October 31st Wednesday, November 1st Thursday, November 2nd
View this program: with abstractssession overviewtalk overview
Panel Organizers: Mark Tehranipoor (University of Florida) and Yervant Zorian (Synopsys)
Panel Moderator: Mark Tehranipoor (University of Florida)
Safety and security assurance of future smart vehicles have become ever more important and a pressing need. The complex ecosystem delivering components – both hardware and software – through a potentially untrusted supply chain and the sheer complexity of security design and validation of modern cars create host of new challenges with system security. Innovative features like driver assistance, infotainment via smartphone integration or over-the-air (OTA) updates keep increasing the potential attack surfaces and vulnerabilities for both remote and physical attacks. This panel will cover this important topic and point to the associated challenges as well as hopes in the horizon.
Panelists:
Yervant Zorian, Synopsys
Riccardo Mariani, Intel
Ken Modeste, Underwriters Laboratories
Swarup Bhunia, University of Florida
Yousef Iskandar, Cisco
View this program: with abstractssession overviewtalk overview
Presenter: Bob Klosterboer, EVP of the Analog Solutions Group, ON Semiconductor
Abstract: This presentation will highlight some of the challenges and opportunities that test developers and test operations managers face in a changing data climate. Measured data will drive decisions not only about the product under test but potentially on the entire design and manufacturing ecosystem. I will also explore some the value tradeoffs of increased data harvesting vs reduced test cost requirements of each component.
Bio: Robert Klosterboer joined ON Semiconductor in March 2008 and currently serves as Executive Vice President and General Manager of the Analog Solutions Group for ON Semiconductor and SCI LLC. From March 2008 to September 2012 he was Senior Vice President and General Manager of the business unit then known as the Automotive, industrial, Medical, & Mil/Aero Group. He has more than two decades of experience in the electronics industry. During his career, Mr. Klosterboer has held various engineering, marketing and product line management positions. Prior to joining ON Semiconductor in 2008, Mr. Klosterboer was Senior Vice President, Automotive & Industrial Group for AMI Semiconductor, Inc. Mr. Klosterboer joined AMIS in 1982 as a test engineer and during his tenure there he also was a design engineer, field applications engineer, design section manager, program development manager, and product marketing manager. Mr. Klosterboer holds a bachelor's degree in electrical engineering technology from Montana State University.
| 14:00 | Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs ( abstract ) |
| 14:30 | Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization ( abstract ) |
| 15:00 | An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme ( abstract ) |
| 15:30 | Built-in Self-Test for Stability Measurement of Low-Dropout Regulator ( abstract ) |
| 14:00 | Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set ( abstract ) |
| 14:30 | Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure ( abstract ) |
| 15:00 | Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective ( abstract ) |
| 15:30 | High-Throughput Multiple Device Diagnosis System ( abstract ) |
| 14:00 | Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time ( abstract ) |
| 14:30 | Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric ( abstract ) |
| 15:00 | On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops ( abstract ) |
| 15:30 | Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors ( abstract ) |
| 14:00 | Interstitial DFT in SpeedCore™ ( abstract ) |
| 14:04 | A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling ( abstract ) |
| 14:08 | Quo Vadis IJTAG.1? ( abstract ) |
| 14:12 | Scaling Interactive IJTAG Debug Beyond the Desktop to ATE ( abstract ) |
| 14:16 | Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG ( abstract ) |
| 14:20 | An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield ( abstract ) |
| 14:24 | Taming of the Shmoo ( abstract ) |
| 14:28 | Technique to Test Hierarchical Designs with Multiple Design Levels ( abstract ) |
| 14:32 | Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects ( abstract ) |
| 14:36 | BIST On-demand Using Distributed On-Chip Programmable Data Streams ( abstract ) |
| 14:40 | Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture ( abstract ) |
| 14:44 | Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature ( abstract ) |
| 14:48 | Testing TSVs for Micro-void and Pinhole Defects Using OTA ( abstract ) |
| 14:52 | Self-Test and Self-Repair Method for FPGAs ( abstract ) |
| 14:56 | A VMIN Temperature Shift Outlier Screen for Cold Test Elimination ( abstract ) |
| 15:00 | Hierarchical Hybrid EDT-LBIST System ( abstract ) |
| 15:04 | A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test ( abstract ) |
| 15:08 | Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing ( abstract ) |
| 15:12 | Transition Fault Testing for Offline Adaptive Voltage Scaling ( abstract ) |
| 15:16 | A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links ( abstract ) |
| 15:20 | A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode ( abstract ) |
| 15:24 | The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps ( abstract ) |
| 15:28 | Multicycle At-Speed Test ( abstract ) |
| 15:32 | Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study ( abstract ) |
| 15:36 | Delay Fault Testing Using Cloud Testing Service ( abstract ) |
| 15:40 | Multisite PMIC Fast Trimming with Pattern-based Search Function ( abstract ) |
Organizer: Jeff Rearick, AMD
For evaluating the performance and effectiveness of new test methods and algorithms, and for comparing new approaches with those previously published, benchmark circuits have proven to be highly useful. This session will explore two new sets of benchmarks, one for analog circuits and the other for 1687 networks. Both of these topics are quite active in the industry and the standards development community, which makes the release of these benchmarks timely and pertinent. To examine the importance of benchmarks in general, as well as to strike a cautionary note about the effects of over-reliance on the specific attributes of published benchmarks, the final presentation will review several other available test benchmarks and reflect on what we’ve learned in the past decades through using them.
| 16:30 | A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods ( abstract ) |
| 17:00 | Doing more with ITC'2016 IEEE 1687 Benchmarks: Ecosystem and PDLs ( abstract ) |
| 17:30 | A Third of a Century of ATPG Benchmarks ( abstract ) |
Description: Testing of analog circuits has been challenging since there is no uniformly accepted behavior of defects and no established relationship between defects and fault coverage therein. To ensure quality of the manufactured circuit, there is a tendency to test the circuit for all its operating performance parameters. However, this is becoming increasingly unaffordable and hence there is an increasing focus on testing for defects alone as against testing for specifications. This special session will have three experts present their views on what is required for designing to specifications and testing for defects alone in analog circuits, and what are the impediments to adopting this as a design and test methodology. These presentations will cover illustrations on where and how these methods have been successfully used on today’s circuits and what are the challenges preventing their wider adoption. Other aspects of evaluating these methods using silicon data from characterization and production, and how they scale for low DPPM requirements will also be covered. These will lead to a recipe for defect based testing for analog.
| 16:30 | Testing for Latent Defects in the Analog: Does the Spec. Matter? ( abstract ) |
| 17:00 | Functional vs. Defect-based Testing in Context of Analog Mixed-Signal Blocks ( abstract ) |
| 17:30 | Advanced Test Methods for Mixed-Signal Circuits: Specification vs. Defect-based Test ( abstract ) |
| 16:30 | Fault-tolerant Electronic System Design ( abstract ) |
| 17:00 | Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements ( abstract ) |
| 17:30 | Design-for-Test and Test Optimisation for 3D SOCs ( abstract ) |
Post Silicon diagnosis drives the isolation of manufacturing defects and provides feedbacks for process improvement and is critical for enabling Moore’s law and semiconductor technology scaling. Due to the increasing complexity of nano-scale manufacturing fabrication, the need for faster root-cause of issues is essential for volume production ramp to meet the product time to market demand. Over the last several years, many innovations have been made and novel solutions are emerging for better and faster defect isolation. With the advent of new transistor devices, lithography, and fabrication processes, the demand for improving the defect isolation and faster yield learning will continue to grow in coming years.
In this tutorial, we will review the basics of diagnosis approaches, and advancements in post silicon diagnosis field. In addition to diagnosis quality improvement, increased focus has been made to volume processing of diagnosis results for yield learning. This has resulted in introduction of new DFT technologies to obtain and process massive amount of fail data, and to provide better controllability and observability of failures to narrow down the defect suspects. Diagnosis algorithms are optimized to provide speed-ups in analysis time. Advancements are made in fault modeling to abstract the complex defect behavior and logical analysis of failures are being incorporated with layout analysis for finer pruning of diagnosis candidates. We will review emerging techniques of learning based diagnosis approach which combining with process sensitivity, DFM constraints, and lithography simulation will be the key for driving the innovations for future technology generations.
| 16:30 | Diagnosis Part 1 ( abstract ) |
| 17:00 | Diagnosis Part 2 ( abstract ) |
| 17:30 | Diagnosis Part 3 ( abstract ) |
View this program: with abstractssession overviewtalk overview
| 08:30 | Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation ( abstract ) |
| 09:00 | Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter ( abstract ) |
| 09:30 | A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions ( abstract ) |
| 08:30 | DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects ( abstract ) |
| 09:00 | Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation ( abstract ) |
| 09:30 | Selecting Target Bridging Faults for Uniform Circuit Coverage ( abstract ) |
| 08:30 | Hardware Trojan Detection Through Information Flow Security Verification ( abstract ) |
| 09:00 | Run-Time Hardware Trojan Detection Using Performance Counters ( abstract ) |
| 09:30 | Thwarting Analog IC Piracy via Combinational Locking ( abstract ) |
| 08:30 | Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study ( abstract ) |
| 09:00 | Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics ( abstract ) |
| 09:30 | Analytical Test of 3D Integrated Circuits ( abstract ) |
| 10:30 | Use Models for Extending IEEE 1687 to Analog Test ( abstract ) |
| 11:00 | Single-Pin Test Control for Big A, little d Devices ( abstract ) |
| 11:30 | Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus ( abstract ) |
| 10:30 | Kernel-based Clustering for Quality Improvement and Excursion Detection ( abstract ) |
| 11:00 | Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects ( abstract ) |
| 11:30 | POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits ( abstract ) |
| 10:30 | Test Opportunities to Reduce Time and Expertise Required to Assess (TERA) for Trust ( abstract ) |
| 11:00 | Fault Injection Attacks and their Mitigation in Embedded Processors ( abstract ) |
| 11:30 | Opportunities in Emerging Technologies for Hardware Security ( abstract ) |
Organizer: Peilin Song, IBM Research
Peilin Song (IBM, United States)
| 10:30 | The Emerging Applications of Machine Learning in Testing ( abstract ) |
| 11:00 | Enhanced Lithographic Hotspot Detection Through Design of Experiments ( abstract ) |
| 11:30 | Opportunities in Machine Learning and Test ( abstract ) |
| 14:00 | Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs ( abstract ) |
| 14:30 | Advancing Test Compression to the Physical Dimension ( abstract ) |
| 15:00 | Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points ( abstract ) |
| 14:00 | Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems ( abstract ) |
| 14:30 | A Run-Pause-Resume Silicon Debug Technique with Cycle Granularity for Multiple Clock Domain Systems ( abstract ) |
| 15:00 | GPU-Accelerated Fault Dictionary Generation for the TRAX Fault Model ( abstract ) |
| 14:00 | Upgrade/Downgrade: A Perspective on Challenges and Opportunities in Overcoming the Legacy System Issue ( abstract ) |
| 14:30 | Supply-Chain Risks in Additive Manufacturing ( abstract ) |
| 15:00 | Securing Chip-Scale Microbiology and Biochemistry: Attacks and Countermeasures for Microfluidic Biochips ( abstract ) |
| 14:00 | Part 1: Demystifying Automotive Safety and Security for Semiconductor Developer ( abstract ) |
| 14:45 | Part 2: An Effective Functional Safety Solution for Automotive Systems-on-Chip ( abstract ) |
Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication and data security in IoT platforms. This talk describes the design of security circuit primitives that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99 min-entropy with 3pJ/bit energy-efficiency. The talk will also discuss design issues related to side-channel leakage of key information, and how they may be addressed during design of encryption circuits. Finally, the talk will touch upon existing challenges of maintaining the integrity of security circuits, while still enabling testability and post-silicon validation.
Bio:
Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he leads research & development of energy-efficient hardware accelerators for encryption & security. Sanu obtained his Ph.D. degree in Electrical and Computer Engineering from State University of New York at Buffalo in 1999. He holds 41 issued patents, with another 63 patents pending and has published over 77 conference/journal papers. He has been with Intel for the past 18 years.
View this program: with abstractssession overviewtalk overview
| 09:00 | Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking ( abstract ) |
| 09:30 | RTL Functional Test Generation Using Factored Concolic Execution ( abstract ) |
| 10:00 | Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems ( abstract ) |
| 09:00 | Automated Die Inking: A Pattern Recognition-based Approach ( abstract ) |
| 09:30 | Front-End Layout Reflection for Test Chip Design ( abstract ) |
| 10:00 | ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation ( abstract ) |
| 09:00 | A Cloud-based Methodology for Online PVTA Monitoring ( abstract ) |
| 09:30 | Changepoint-based Anomaly Detection in a Core Router System ( abstract ) |
| 10:00 | Symbol-based Health-Status Analysis in a Core Router System ( abstract ) |
| 09:00 | Safety Analysis for Integrated Circuits in the Context of Hybrid Systems ( abstract ) |
| 09:30 | Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs ( abstract ) |
| 10:00 | Some Considerations on Choosing an Outlier Method for Automotive Product Lines ( abstract ) |
Presenter: Joachim Kunkel, General Manager, Synopsys, Inc., Corporate Staff
Title: Look mom! No hands!
Abstract: After many years of relying on established processes technology geometries, advanced automotive semiconductors, driven by assisted and autonomous driving systems, have recently joined the race to ever smaller semiconductor process technologies. If the massive functionality enabled by 16-nm and below FinFET semiconductor processes, combined with the new fault mechanisms they bring along, weren’t enough of a test and repair challenge, the automotive functional safety requirements add a whole other dimension to the problem. This talk discusses automotive test and repair requirements and solutions in the context of automotive functional safety from the perspective of a test automation tool and IP provider.
Bio: Joachim joined Synopsys in 1994 and serves as general manager of the Solutions Group. In this capacity, he oversees the business unit responsible for Synopsys DesignWare intellectual property (IP). Before joining Synopsys, Joachim was co-founder of CADIS GmbH in Aachen, Germany. There, he served as managing director and performed myriad duties in engineering, sales, and marketing. Before co-founding CADIS he was a research assistant at the Aachen University of Technology, where he conducted research in system-level simulation techniques for digital signal processing, with special emphasis on parallel computing. Joachim holds an M.S.E.E. degree, the Dipl.-Ing. der Nachrichtentechnik, from the Aachen University of Technology.
System Level Test is becoming a bit of a hot button topic at times. The general sentiment with some is, "hate to have to implement System-Leve Test, but cannot live without it". In this "virtual panel" everyone can weigh in during this interactive session and share their opinion through the audience poll. We will see what the Test community sees as the issues and challenges going forward. We will raise the questions one by one providing some time for the everyone to answer in an online poll and then show the results real-time.
Organizers: Enamul Amyeen, Shawn Blanton
Moderator: Enamul Amyeen
Panelists:
Rob Aitken, ARM
Shawn Blanton. CMU
Rao Desineni, Global Foundries
Doug Gerwitz, Intel
Bruce Cory, NViDIA
Mike Bourland, Qualcomm
Current approaches for test chip design does not fully reflect all the complexities of actual customer product ICs, therefore yield learning is becoming more dependent on product fails as opposed to test chips. The capability of a test chip to capture real product issues may be diminishing as we move further and further into advanced process nodes. Are test chips missing the mark, or is the fabrication process simply different when customer ICs are manufactured?
Panel: Automotive Test & Reliability: Challenges or Opportunities
Moderator: LeRoy Winemberg, NXP (US)
Organizer: Yervant Zorian, Synopsys (US)
While ensuring automotive test quality needs (DPPB) and meeting reliability levels and functional safety standards are major challenges today, could our embedded test & repair infrastructure become the new opportunity to address the multipurpose needs of automotive SoCs?
Panelists:
O. Ballan, Xilinx (USA)
Gabriele Boschi, Intel (Italy)
Marco Casarsa, ST (Italy)
Christophe Eyschenne, Bosch (France)
Rubin Parekhji, Texas Instruments (India)
Leroy Winemberg, NXP Semiconductors (USA)
Organizer: Jeff Rearick, AMD
The IEEE Test Technology Standards Committee oversees the entire lifecycle of the development of new standards in our field. This session features three standards in three different stages of that lifecycle: one just completed and published, one in active development by a working group, and one just starting as a study group. Respectively, the freshly-minted IEEE 1149.10 standard addresses the use of high-speed serial I/O interfaces to access scan and JTAG registers, the IEEE P1687.1 working group is defining how to connect 1687 networks to non-TAP device interfaces, and the study group is tackling analog test access and coverage issues. The audience will receive an overview of the first standard and learn about the in-flight development details for the other two efforts.
| 14:00 | IEEE 1149.10-2017: Mapping JTAG and Scan onto Serial I/O Such As SERDES and SPI ( abstract ) |
| 14:30 | IEEE P1687.1: Accessing 1687 Networks via Non-TAP Interfaces ( abstract ) |
| 15:00 | IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems ( abstract ) |