ITC 2017: INTERNATIONAL TEST CONFERENCE 2017
PROGRAM FOR THURSDAY, NOVEMBER 2ND
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09:00-10:30 Session 11: Functional and Software-based Test
Chair:
Sounil Biswas (Altera, United States)
Discussant:
Prab Varma (Veritable, United States)
09:00
Ying Zhang (The School of Software Engineering, Tongji University, China)
Krishnendu Chakrabarty (Duke University, United States)
Huawei Li (Institute of Computing Technology, Chinese Academy of Sciences, China)
Jianhui Jiang (The School of Software Engineering, Tongji University, China)
Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
SPEAKER: Ying Zhang

ABSTRACT. Online testing is critical to ensure reliable operation of NoC-based manycore systems. We present a software-based online NoC self-testing solution based on bounded model checking, and achieves high fault coverage in functional mode.

09:30
Sonal Pinto (Virginia Tech, United States)
Michael S. Hsiao (Virginia Tech, United States)
RTL Functional Test Generation Using Factored Concolic Execution

ABSTRACT. We present CORT (COncolic RTL Test generator), which rapidly builds functional tests with the aim of maximizing branch coverage. Path explosion and unrolling limitations are solved by stitching together factorized explorations.

10:00
Christopher Lukas (University of Virginia, United States)
Farah Yahya (University of Virginia, United States)
Ben Calhoun (University of Virginia, United States)
Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems

ABSTRACT. This paper models trans-threshold correlations to allow high voltage, high speed testing of subthreshold SoCs. This accurately predicts delay and power, resulting in 5.4X test time reduction in sequential logic, and >2X reduction in SRAMs.

09:00-10:30 Session 12: Die Inking, Test Chips and Aging
Chair:
Glenn Colon-Bonet (Intel, United States)
Discussant:
John Carulli (GLOBALFOUNDRIES, United States)
09:00
Constantinos Xanthopoulos (The University of Texas at Dallas, United States)
Peter Sarson (ams AG, Austria)
Heinz Reiter (ams AG, Austria)
Yiorgos Makris (The University of Texas at Dallas, United States)
Automated Die Inking: A Pattern Recognition-based Approach

ABSTRACT. Marking of failing die clusters is manually performed in order to exclude neighboring die that are likely to be defective. In this work, we propose a novel approach to automate this process.

09:30
Zeye Liu (Carnegie Mellon University, United States)
Phillip Fynan (Carnegie Mellon University, United States)
Ronald Blanton (Carnegie Mellon University, United States)
Front-End Layout Reflection for Test Chip Design
SPEAKER: Zeye Liu

ABSTRACT. This work describes a design flow that identifies and incorporates representative FEOL-layout geometries into an optimally-testable logic test chip.

10:00
Souhir Mhira (ST Microelectronics, France)
Vincent Huard (STMicroelectronics, France)
Ahmed Benhassain (STMicroelectronics, France)
Florian Cacho (STMicroelectronics, France)
David Meyer (STMicroelectronics, France)
Sylvie Naudet (STMicroelectronics, France)
Abhishek Jain (STMicroelectronics, India)
Chittoor Parthasarathy (STMicroelectronics, India)
Alain Bravaix (REER-ISEN, France)
ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
SPEAKER: Souhir Mhira
09:00-10:30 Session 13: Status Monitoring
Chair:
Samy Makar (Stanford, United States)
Discussant:
Yanjing Li (University of Chicago, United States)
09:00
Shi-Yu Huang (National Tsing Hua University, Taiwan)
A Cloud-based Methodology for Online PVTA Monitoring
SPEAKER: Shi-Yu Huang

ABSTRACT. This talk reviews a methodology for monitoring the PVTA conditions of a device (including Process, Voltage, Temperature, and Aging), even when it is operated in the field. For IoT devices, such a monitoring scheme can be even conducted from the cloud and anywhere in the world. With such a built-in scheme, not only the operating conditions of a device can be continually tracked, a potential PVTA-induced failure can be alarmed in advance before it actually strikes. A working prototype system will be demonstrated to show real data.

09:30
Shi Jin (Duke University, United States)
Zhaobo Zhang (Huawei Technologies Co. Ltd., United States)
Krishnendu Chakrabarty (Duke University, United States)
Xinli Gu (Huawei Technologies Co. Ltd., United States)
Changepoint-based Anomaly Detection in a Core Router System
SPEAKER: Shi Jin

ABSTRACT. A changepoint-based anomaly detector is designed and implemented that detects changepoints from collected time-series data and utilizes these changepoints to identify “outliers” when the application scenario of monitored core routers change significantly as time proceeds

10:00
Shi Jin (Duke University, United States)
Zhaobo Zhang (Huawei Technologies Co. Ltd., United States)
Krishnendu Chakrabarty (Duke University, United States)
Xinli Gu (Huawei Technologies Co. Ltd., United States)
Symbol-based Health-Status Analysis in a Core Router System
SPEAKER: Shi Jin

ABSTRACT. A symbol-based health status analyzer is implemented that encodes, as a symbol sequence, the long-term complex time series collected from a number of core routers, and utilizes the symbol sequence to do health analysis.

09:00-10:30 Session 14: Safety and Test for Automotive ICs
Chair:
Oscan Ballan (Xilinx, United States)
Discussant:
Paolo Bernardi (Politecnico di Torino, Italy)
09:00
V Prasanth (Texas Instruments, India)
Rubin Parekhji (Texas Instruments (Bangalore), India)
Bharadwaj Amrutur (Indian Institute of Science, India)
Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
SPEAKER: V Prasanth

ABSTRACT. Many real-life systems have integrated circuits interacting with physical systems in safety critical applications. We propose an improved safety analysis method cognizant of end application with interacting physical system to reduce hardware overhead for safety.

09:30
Tal Kogan (Intel, Israel)
Yehonatan Abotbol (Inomize, Israel)
Gabriele Boschi (Intel, Italy)
Gurgen Harutyunyan (Synopsys, Armenia)
Itay Kroul (Intel, Israel)
Hanna Shaheen (Intel, Israel)
Yervant Zorian (Synopsys, United States)
Advanced Functional Safety Mechanisms for Embedded Memories and IPs in Automotive SoCs
SPEAKER: Tal Kogan

ABSTRACT. Given the fast growing complexity and miniaturization of automotive SoCs, this paper presents functional safety challenges and related solutions for such SoCs. The paper is based on ISO 26262 standard and shows experimental results on a SoC example to demonstrate the advantages of the proposed solutions.

10:00
Li-C. Wang (UCSB, United States)
Sebastian Siatkowski (UCSB, United States)
Chuanhe Shan (UCSB, United States)
Matthew Nero (UCSB, United States)
Nikolas Sumikawa (NXP, United States)
Leroy Winemberg (NXP, United States)
Some Considerations on Choosing an Outlier Method for Automotive Product Lines
SPEAKER: Li-C. Wang

ABSTRACT. The concept of applicability of an outlier methods is proposed. Results of evaluating such applicability for five selected outlier methods across five automotive product lines are presented.

11:00-12:00 Session K3: Keynote - Automotive

Presenter: Joachim Kunkel, General Manager, Synopsys, Inc., Corporate Staff

Title: Look mom! No hands!

Abstract: After many years of relying on established processes technology geometries, advanced automotive semiconductors, driven by assisted and autonomous driving systems, have recently joined the race to ever smaller semiconductor process technologies. If the massive functionality enabled by 16-nm and below FinFET semiconductor processes, combined with the new fault mechanisms they bring along, weren’t enough of a test and repair challenge, the automotive functional safety requirements add a whole other dimension to the problem. This talk discusses automotive test and repair requirements and solutions in the context of automotive functional safety from the perspective of a test automation tool and IP provider.

Bio:  Joachim joined Synopsys in 1994 and serves as general manager of the Solutions Group. In this capacity, he oversees the business unit responsible for Synopsys DesignWare intellectual property (IP). Before joining Synopsys, Joachim was co-founder of CADIS GmbH in Aachen, Germany. There, he served as managing director and performed myriad duties in engineering, sales, and marketing. Before co-founding CADIS he was a research assistant at the Aachen University of Technology, where he conducted research in system-level simulation techniques for digital signal processing, with special emphasis on parallel computing. Joachim holds an M.S.E.E. degree, the Dipl.-Ing. der Nachrichtentechnik, from the Aachen University of Technology.

14:00-15:30 Session P2: Hot Topic Virtual Panel - What does the Test Community really think about System-Level Test?

System Level Test is becoming a bit of a hot button topic at times.  The general sentiment with some is, "hate to have to implement System-Leve Test, but cannot live without it". In this "virtual panel" everyone can weigh in during this interactive session and share their opinion through the audience poll.  We will see what the Test community sees as the issues and challenges going forward.   We will raise the questions one by one providing some time for the everyone to answer in an online poll and then show the results real-time.

Chair:
Paul Berndt (Test Consultant, United States)
14:00-15:30 Session P3: Yield Learning at the Crossroads – Test Chips to the Rescue?

Organizers: Enamul Amyeen, Shawn Blanton

Moderator: Enamul Amyeen

Panelists:  

                   Rob Aitken, ARM

                   Shawn Blanton. CMU

                   Rao Desineni, Global Foundries

                   Doug Gerwitz, Intel

                   Bruce Cory, NViDIA

                   Mike Bourland, Qualcomm

Current approaches for test chip design does not fully reflect all the complexities of actual customer product ICs, therefore yield learning is becoming more dependent on product fails as opposed to test chips.  The capability of a test chip to capture real product issues may be diminishing as we move further and further into advanced process nodes.  Are test chips missing the mark, or is the fabrication process simply different when customer ICs are manufactured?

Chair:
Enamul Amyeen (Intel, United States)
14:00-15:30 Session P4: Automotive Panel

Panel: Automotive Test & Reliability: Challenges or Opportunities 

Moderator: LeRoy Winemberg, NXP (US)

Organizer: Yervant Zorian, Synopsys (US)

While ensuring automotive test quality needs (DPPB) and meeting reliability levels and functional safety standards are major challenges today, could our embedded test & repair infrastructure become the new opportunity to address the multipurpose needs of automotive SoCs?  

Panelists:

O. Ballan, Xilinx (USA)

Gabriele Boschi, Intel (Italy)

Marco Casarsa, ST (Italy)

Christophe Eyschenne, Bosch (France)

Rubin Parekhji, Texas Instruments (India)

Leroy Winemberg, NXP Semiconductors (USA)

Chair:
Yervant Zorian (Synopsys, United States)
14:00-15:30 Session S6: Special Session: Emerging IEEE Test Standards

Organizer: Jeff Rearick, AMD

The IEEE Test Technology Standards Committee oversees the entire lifecycle of the development of new standards in our field.  This session features three standards in three different stages of that lifecycle: one just completed and published, one in active development by a working group, and one just starting as a study group.  Respectively, the freshly-minted IEEE 1149.10 standard addresses the use of high-speed serial I/O interfaces to access scan and JTAG registers, the IEEE P1687.1 working group is defining how to connect 1687 networks to non-TAP device interfaces, and the study group is tackling analog test access and coverage issues.  The audience will receive an overview of the first standard and learn about the in-flight development details for the other two efforts.

Chair:
Mike Ricchetti (Synopsys, United States)
14:00
Cj Clark (Intellitech, United States)
IEEE 1149.10-2017: Mapping JTAG and Scan onto Serial I/O Such As SERDES and SPI
SPEAKER: Cj Clark
14:30
Al Crouch (SiliconAid, United States)
IEEE P1687.1: Accessing 1687 Networks via Non-TAP Interfaces
SPEAKER: Al Crouch
15:00
Steve Sunter (Mentor Graphics, Canada)
IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems
SPEAKER: Steve Sunter