ABSTRACT. Metal Gate / High-k stacks are in CMOS manufacturing since the 45nm technology node. To meet technology performance and yield targets gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

ABSTRACT. With shrinking dimensions and increased number of on-chip transistors radiation can provoke faults in integrated circuits even at sea level. This paper presents a comparison of Fully Depleted SOI (FDSOI) and Bulk CMOS 6T SRAM Cells’ Resilience to Radiation Effects. Both cells were simulated using TCAD tools, considering heavy-ion impacts in different locations of the transistor as well as using different impact angles. Two types of radiation effects have been considered: Single-Event Transients (SETs) and Single-Event Upsets (SEUs). The minimum critical collected charge (CC) to flip a cell is almost the same in both technologies. However, it is shown that a FDSOI SRAM cell needs a heavy-ion impact with a Linear Energy Transfer (LET) around 10 times greater than a Bulk-CMOS SRAM cell, to generate a similar CC and to flip a cell.

ABSTRACT. This paper shows the advantages of using body bias. Experiments are performed in 14 nm and 28nm UTBB FDSOI transistors and ring oscillators (ROs). The impact of body bias on performance and reliability are highlighted. The body biasing offers significant advantages for adapting the tradeoff between reliability and performance in logic circuits without changing the design margins. With FDSOI technology, we have an additional degree of freedom of process variability compensation by using body bias voltage (Adaptive Body Bias, ABB) next to supply voltage compensation used before. We show that ABB compensation technique presents better results for a complete power optimization.

ABSTRACT. We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias VB sensing effects in forward (FBB) mode in 28nm FDSOI CMOS node. This is done for DC to AC operations from Input-Ouput device (EOT= 3.6nm) to core blocks (EOT= 1.35nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (IOn, VT) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case.

ABSTRACT. Under a research project of monolithic pixel detectors, a double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. It not merely integrates the sensor and readout circuit on the same processed wafer, but also increases radiation tolerance. Electromagnetic susceptibility (EMS) is also an important reliability issue in pixel detectors. The readout circuit should avoid false signal generation due to coupled noise from the substrate. This paper evaluates the performance of DSOI devices regarding total ionizing dose (TID) effect compensation in transistors by applying a negative bias to the middle silicon layer, and evaluates the electromagnetic susceptibility of the substrate by a ring oscillator. The experiment results show that the DSOI device is able to compensate for TID, and the threshold voltage and leakage current are recoverable. However, the reduction of TID effect on the DSOI device is at the expense of increasing susceptibility to electromagnetic interference (EMI) on the substrate.

ABSTRACT. Most studies on resistance switching have been carried out at the device level with the standard electrical characterization setup, which allows for effective automated reliability test and extensive characterization of the lifetime of an RRAM device. However, it is equally important to be able to probe the switching phenomenon at the nanoscale so as to improve insight on the bias-dependent kinetic behavior of the filament during multiple reversible breakdown and recovery cycles. This study aims to do just that by probing HfO2 blanket films (~4 nm) with a W bottom electrode using an ultra-sharp Ptwire conductive-AFM (CAFM) tip with an areal resolution of 10-20 nm at ambient conditions. The use of the CAFM allows for a more reliable assessment of single filament evolution behavior as possible multiple filamentation events (common at the device level) are rare for such small probing areas. The role of oxygen vacancy induced filaments is studied here by using low compliance setting and moderate voltage levels, ensuring operation in the sub-quantum conductance regime. Our results show good repeatable switching trends and also provide insight on the quantum conductance phenomenon in oxygen vacancy based filaments. The read disturb trends in switching are investigated for the high resistance state (HRS) and the impact of tip-induced mechanical stresses on forming lifetime is also presented, which could serve as a motivator for further studies on non-volatile memory (NVM) reliability for flexible electronics devices and system on chip (SoC) applications.

ABSTRACT. Plug connectors are one of the frequent failure causes when regarding at electronic systems. Since connectors had to keep pace with ongoing miniaturization on PCB level, current and voltage capabilities and specifications are frequently sportive or even overestimated. The tutorial focuses on the interfaces between connector and PCB as well as on connector-to cable and the connector contact itself, showing various failure mechanisms and precautions. Environmental conditions may also severely impact the connector reliability. The tutorial sensitizes the failure analyst to this underestimated topic and offers a deeper understanding and precaution measures against connector-related failures. Since many aspects considering plug connectors also apply for relays, the most important relay failure aspects are included in a small chapter of this tutorial.

ABSTRACT. As the first power GaN devices are entering the market, there is an increasing demand of thorough understanding of long term reliability mechanisms for this new technology. A potentially critical topic is the piezoelectric character of Gallium Nitride (GaN), where an applied electric voltage in the device will result in additional mechanical stresses, which makes a significant difference to traditional silicon based power devices. This physical effect can be studied by numerical FEM (Finite-Element Method) simulations covering the piezoelectric nature of GaN. This talk will give an insight on how temperature, stress and electric field interact – based on the Heckmann diagram – and how these effects can be calculated by numerical FEM simulations. A representative example of a Finite-Element model will be discussed in detail to show how the combined effect of an electric field and temperature rise is modelled.

ABSTRACT. Monolithic integration between AlGaN/GaN high electron mobility transistor (HEMT) and Si-based semiconductors is very attractive as this will open up many applications and allow cost-effective large scale fabrication. However, there are still many reliability problems to be solved for this technology. Our group is studying the reliability of AlGaN/GaN HEMT grown on Si substrate. The goal of the project is to come out with a reliability model to predict the lifetime of AlGaN/GaN HEMT on Si. The lattice mismatch between GaN and Si substrate higher than other substrates causing high threading dislocation density (TDD) about 109 cm-2. We found that degradation pits were formed at threading dislocation due to lower strain energy. This will affect the device performance significantly. Thus it is crucial to keep the TDD as low as possible during the AlGaN/GaN epitaxy growth on Si substrate.

ABSTRACT. Single photon avalanche diode (SPADs) is a photodiode that detects light very sensitively compared to the common photodiodes. SPADs with high accuracy in detecting light is being used in many fields already including autonomous car system, geographical measurement and biological measurement usage. However, for the high level application of SPADs such as autonomous car system which is directly related to the human safety, high level of SPADs reliability to the various environment including external thermal and electrical stress should be secured. In this presentation we will introduce SPADs, their basic operation principle and applications. Also, reliability issues in SPADs and ongoing research topics will be addressed.

ABSTRACT. The parasitic bipolar transistor (BJT) is a well known failure mechanism in integrated circuits, which is of particular interest for power applications and under leaky conditions. This work focuses on characterizing the behavior of parasitic BJT, in saturated as well as in active mode, whilst operating the MOS transistor. Electrical measurements and photon emission measurements of the two devices have been conducted. The results of the photon emission measurements show different spacial spreading for the two devices: while the Photon emission (PEM) signal of the MOS transistor in saturation is sharply focused, the signals of the parasitic BJT are spread wider, in BJT saturation mode even more than in active condition. Thus the PEM signals of the two devices, operated separately and in combination, are distinct and are therefore an interesting possibility for failure analysis and will be investigated further with spectroscopic implications.

ABSTRACT. Electro optical techniques are efficient backside contactless techniques usually used for design debug and defect location in modern VLSI. Unfortunately, the signal to noise ratio is quite low and depends on laser power with potential device stress due to long acquisition time or high laser power, especially in up to date technologies. Under these conditions, to maintain a good signal or image quality, specific signal or image processing techniques can be implemented. In this study, I proposed new post-processing approaches which allows the use of low laser power and short acquisition time in temporal and image mode

ABSTRACT. 3D integration technology is one of the promising solutions to overcome the bottleneck problems with classical transistor scaling by stacking Si wafers/dies on top of each other offering faster and more compact electronic circuits. The stacked wafers/dies are electrically interconnected using µ-bumps and Cu TSVs (Through Silicon Vias) which introduce new failure modes and require new failure analysis techniques. One of the problems associated with TSVs in 3D technology is the stress induced in the surrounding Si substrate.  Current TSV stress measurement techniques, such as µRaman spectroscopy, only provide local information and require long measurement time. Acoustic GHz-microscopy is another possible candidate not only for detecting TSV failures, but also for detecting TSV stresses by visualizing the Rayleigh waves fringe pattern around a TSV. The aim of this study is to evaluate the capability of the GHz SAM in detecting differences in Rayleigh wave velocities around the TSVs which might be interpreted in terms of stresses.

ABSTRACT. Recent trends in 3D integration and dimensional scaling technologies have attracted interest in micro-connects as a novel method for interconnection. Micro-connects, including small volume interconnects (or micro-bumps) and Solid-Liquid Interdiffusion (SLID) bonds for Micro- and Nanoelectromechanical Systems (MEMS and NEMS) are functionally far superior in comparison with traditional large volume interconnects and enable novel integration techniques for the miniaturisation and diversification of complex integrated systems. As micro-connects have smaller volumes than traditional forms of interconnects, they become more susceptible to microstructural defect failures. One problematic defect is Cu-Sn interfacial voiding, often referred to as Kirkendall voiding. This work examines the relationship between the embedded impurities occurring during Cu electroplating, the chemical composition of the electroplated Cu and the microstructure over the thermal-mechanical lifetime of micro-connects. This study is designed not only to understand the root-cause, but also the reliability impacts of interfacial void formation in Cu-Sn micro-connects.

ABSTRACT. The southeast United States continues to develop the fastest growing automotive industry in North America. Known for its world‐class automotive production and excellent business environment, the region’s supply‐base has grown while OEMs and major suppliers continue to invest. Georgia Tech as the number one ranked engineering university in southeast cooperates with many automotive companies in southeast. Georgia Tech automotive industry partners include BMW, GM and Ford, to date. Additional R&D collaborations are underway with Mercedes Benz, Ferrari, Honda, VW and Toyota in many areas that include hybrid vehicle R&D, internal component design, communication-vehicle interactions, automated driving, driver-assist, human-robot interactions and in environmental impacts.

ABSTRACT. ADAR technology as sensor for collision warning has been used in upper class vehicles for some years now. Assembling this electronic is highly sophisticated and therefore expensive. With new developments in SiGe-technology and semiconductor packaging RADAR technology is now available much smaller and cheaper. It is therefore affordable for mass-market in Advanced Driver Assistance Systems (ADAS) – which means “safety for everyone”. This paper emphasizes the evolution from a consumer electronic package to an automotive package enduring the requirements relating to quality and reliability in these applications. Using 2nd level interconnect reliability as an example, we show the systematic approach utilizing “Design for Reliability” to enhance system properties. Particularly, the package board interaction and the solder joint performance regarding temperature cycling is discussed in matters of board material and build-up.

ABSTRACT. In the last years, many new intelligent headlamp and rear lamp technologies based on semiconductor light sources (LEDs) were developt in order to reduce the traffic accident rates on different road topologies and situations, to improve night time driving comfort and to get better sight conditions. The resulting new intelligent automotive lighting technologies are able to adapt their lighting distributions and luminous intensity on and beside the road in dependence on the traffic density, weather or car speed.

The lecture therefore deals with system development  and system reliability of these innovative lighting systems in automotive lighting. First new lighting systems in LED technology are presented. The design of both the LEDs required for this purpose and the PCB technologies applied has a significant impact on  LED solder joint reliability,  on optimized low position tolerance of the LED component by, component self-alignment mechanism. It also has a key role to play in the system reliability of LED modules. In addition the latest miniaturized LED housing developments – featuring remodeled designs and new materials – are turning the focus toward the thermal management of LED modules, tolerance characteristics, and the entire LED-module production process.  This report concludes with an outlook for new  high resolution light sources systems for automotive lighting.

ABSTRACT. Human civilization revolves around artificial light. Since its earliest incarnation as firelight to its most recent as electric light, artificial light is at the core of our existence. It has freed us from the temporal and spatial constraints of daylight by allowing us to function equally well night and day, indoors and outdoors. It evolved from open fire, candles, carbon arc lamp, incandescent lamp, fluorescent lamp to what is now on our door step: solid state lighting (SSL). SSL refers to a type of lighting that uses semiconductor light-emitting diodes (LEDs), organic or polymer light-emitting diodes (OLED / PLED) as sources of illumination rather than electrical filaments, plasma (used in arc lamps such as fluorescent lamps), or gas. SSL applications are now at the doorstep of massive market entry into our offices and homes. This penetration is mainly due to the promise of an increased reliability with an energy saving opportunity: a low cost reliable solution. An SSL system is composed of a LED engine with a micro-electronics driver(s), integrated in a housing that also provides the optical, sensing and other functions. Knowledge of (system) reliability is crucial for not only the business success of the future SSL applications, but also solving many associated scientific challenges. In practice, a malfunction of the system might be induced by the failure and/or degradation of the subsystems/interfaces. This paper will address the items to ensure high reliability of SSL systems by describing LED degradation from a component and a system perspective.

ABSTRACT. Reliability of LED light sources is essential for many general and automotive lighting application where exchange of LED modules would be expensive. Reliability testing to predict the life-time of the devices is required. In this paper transient thermal testing is applied and further developed to monitor the structural integrity of the LED modules during accelerated stress testing. The temperature shock test is one important test because thermomechanical stress is a dominating root cause for structural failures as delamination in the package or cracking of solder joints between package and board. New flip chip LEDs (WLP-LEDs) are assembled directly on printed circuit boards (PCB). The initial assembly quality is tested using X-Ray, optical inspection and transient thermal analysis (TTA). In combination the methods deliver essential data to ensure initial assembly quality. Afterwards, the LED modules are exposed to temperature shock tests (-40°C to 125°C) and the TTA is performed repeatedly. By TTA the structural integrity is resolved and cracks or delamination can be identified. Failure modes can be separated and the root cause is investigated by support of transient finite element analysis. One test board is measured In-situ during temperature shock testing. Due to differences in thermo-mechanical stress under hot and cold conditions additional information can be obtained.

ABSTRACT. The European Union has identified Micro- and Nanoelectronics as one of the key enabling technology of our times. Specific program lines were initiated in order to support research and development activities throughout the entire value chain. “Pilot Line” projects are intended to close the gap between research and commercial availability of technologies for customers. Infineon Technologies with its core competencies in power and industry electronics, together with its partners in academia and industry uses these programmes actively to enable new technologies contributing to providing solutions to societal challenges such as energy efficiency, mobility and security. The presentation will give an overview on respective strategies and activities contributing to a strong knowledge-based Europe in the global competition

ABSTRACT. Reliability topics are getting ever more important, particularly for automotive or other European-relevant applications. The panel discussion will therefore be devoted to the resulting needs and consequences as well es new demands:

• on supply chain and ecosystem

• on governmental/European research strategies and public funding,

• on industry-academy cooperation,

• on scientific developments and on university education

Participants:

Berthold Hellenthal, AUDI AG (GER)

Sabine Herlitschka, Infineon Technologies Austria AG (AT) (requested)

Mervi Paulasto-Kröckel, Aalto University (FIN)

Michael Pecht, CALCE (USA) (requested)

Simona Rucareanu, ECSEL Joint Undertaking (requested)

ABSTRACT. BTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage Vth after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the BTI degradation itself. The variability of the Vth (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc [1]. The dependence on the transistor size is proven by several publications [e.g. 2,3]. The variability of the BTI parameter degradation itself and the convolution are not fully understood yet and need further investigation. The impact of the recovery behavior on the distribution of the Vth - values is, to our knowledge, not yet studied at all. In this paper we investigate the increase (degradation) of variability due to NBTI and the statistical behavior of Vth after end of stress (recovery). Furthermore we analyze the dependency of the additional variability of Vth on the transistor size and geometry. For the necessary statistical relevance we perform long term NBTI experiments with a special smart array test-structure at a large amount of pMOSFETs with various geometries. We prove our results for a second technology node with a different oxide thickness. We demonstrate for the first time that also the induced additional variability recovers. Furthermore we show that the variability of pMOSFETs after NBTI depends not only on the size of the active area (w×l) but also on its geometry (w/l).

ABSTRACT. With technologies scaling down to 28nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.

ABSTRACT. In this presentation, current trends and requirements for memories in different automotive applications will be discussed.  We see an increasing demand for high density and high performance memory subsystems. These requirements are driven from high-quality video demands within the infotainment segment but as well from an increasing number of sensors to support the ADAS applications leading into an autonomous driving car. More and more connected cars and related networking communication traffic further increases the performance requirements and additionally asks for a secure memory subsystem. However all those innovative systems and features have to meet the strict reliability requirements of the automotive industry. This requires an involvement and a close collaboration at a much earlier point in time within the supply chain. Based on a new level of cooperation we developed a concept that allows investigating the functionality and reliability of new memory subsystems and solutions on system level already during the product design stage. 

ABSTRACT. AVL has developed a comprehensive methodology for a smart reliability approach called “AVL Load Matrix” and is continuously working on extending this methodology for new technologies coming from the electrification area.

Key Benefits of Load Matrix at a glance:

•         Optimization of durability & reliability validation programs
•         Quantify improvement of reliability
•         Monitoring tool in order to quantify risks

The Load Matrix is a generic methodology and consists of four major steps allowing for the systematic analysis of the target system to derive a tailor-made validation program for potential reliability and durability issues. During the first step, the “System analysis”, the target system (e.g. the e-motor) is analyzed in order to identify potential component failure mode combinations. This is the basis for the later analysis of the validation program. The second step, called “Application and targets”, is aimed at describing the end-customer vehicle usage and its consequences on the system load with customer reference profiles. Additionally the set validation targets (e.g. failure rate targets to be demonstrated) are collected and prepared for the analysis. In the third step, “Test program and load analysis”, the coverage of potential component failure modes with the planned durability tests is studied. This can be achieved using basic considerations or detailed damage models describing the estimated damage induced by different tests. The fourth and last step, the “Evaluation and optimization”, combines all previously prepared information: The potential failure modes, the customer reference profiles and the coverage based on planned tests are used to evaluate the quality of the planned validation program. The evaluation allows the identification of potential weak points in the validation program and can be used to quantify the effect of changes in the program. The optimization step is performed by validation experts.

ABSTRACT. A general trend in automotive electronics is the development of customized products with the focus on system integration in combination with increased reliability and lower costs. For transmission control units (TCUs) of Continental this means: extended functionalities have to be integrated in a minimum of available space. At the same time, the TCU has to operate in an harsh environment with increasing temperature, high vibration loads and most aggressive transmission fluids. As a result of these extreme requirements, the development of new TCU solutions and high performance materials is necessary to guarantee a reliable operation over lifetime.

ABSTRACT. During the past decade Cu-wire bonding has been gradually industrialized. Meanwhile, it has become a mature technology in standard commercial electronics. This presentation explains what is needed for a flawless introduction into automotive electronics. First of all, a  comprehensive overview will be given on Cu-wire specific failure mechanisms including the current status on what is known on the Physics-of-Fail. Based on this fundamental knowledge, it will be shown that in-line wire bond responses, if correctly interpreted and used, can both safeguard against early life PPM fails as well as guarantee reliability robustness with respect to wear out failure mechanisms.

ABSTRACT. This paper reports the outcome of a series of reverse-bias experiments performed on commercial GaN-based green LEDs. The experimental results showed that green LEDs submitted to reverse bias i) show a time-dependent failure when they are submitted to constant (reverse) voltage stress, at a bias point smaller than the BDV; ii) experience an increase of the reverse-bias electro-luminescence signal, well-correlated with the increase of the reverse leakage current; iii) the TTF (Time-To-Failure) related to the time-dependent breakdown process has an exponential dependence on stress voltage; iv) the TTF is Weibull distributed. This work provides the first experimental demonstration of time-dependent failure of GaN LEDs.

ABSTRACT. The aim of this paper is to contribute to the understanding of the impact of charge/impurity instabilities on the optical degradation of InGaN LEDs. We demonstrate a correlation between the optical degradation and the accumulation of charge within the active region of the devices; more specifically, we provide experimental evidence that the increase in SRH recombination is strongly related to the diffusion/build-up of charged defects within the active region of the devices. The properties of the defects involved in the degradation are investigated by means of deep level transient spectroscopy DLTS. 

ABSTRACT. Forward and reverse HBM, MM, CDM ESD tests have been performed on 850-nm VCSELs, together with EOS and overpower test. The physical analysis of the tested devices showed a variety of damages not easily correlated to the measured electro-optical degradations. The solution requires the detailed interpretation of the observed physical mechanism, by means of electron microscopy and device modelling.

ABSTRACT. In this paper, we analyze the degradation of InGaN-based green laser diodes submitted to stress tests at different bias currents and junction temperatures. The variation of the threshold current suggests the presence of a diffusion process. The fitting of the degradation kinetics according to Fick’s second law allows for the extrapolation of the diffusion coefficient of the impurity/defect involved in the degradation process, and the related activation energy of 1.98 eV. The diffusion process is accelerated not only by the temperature but also by the flow of current. Taking into account the strong difference between experimental and theoretical diffusion coefficients of Mg and H in GaN, the physical model of the diffusion may need to be revised in order to take into account the role of electric field and carrier flow. The extrapolated values of the diffusion coefficient and of the related activation energy is consistent with the hypothesis that the degradation originates from the diffusion of hydrogen in the H+ species.

ABSTRACT. The defects generated by the catastrophic optical degradation (COD) of high power laser diodes have been examined using cathodoluminescence (CL). Discontinuous dark lines that correspond to different levels of damage have been observed along the ridge. Finite element methods have been applied to solve a physical model for the degradation of the diodes that explicitly considers the thermal and mechanical properties of the laser structure. According to this model, the COD is triggered by a local temperature enhancement that gives rise to thermal stresses leading to the generation of dislocations. Damage is initially localized in the QW, and when it propagates to the waveguide layers the laser ends its life.

ABSTRACT. Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.

ABSTRACT. Channel width dependence of AC stress was investigated. OFF-state stress generated negative interface traps, positive oxide charges, and neutral traps in the whole channel region. Comparison of drain currents of parasitic and main MOSFET during OFF-state indicates that more defects were generated on channel edge than near its center. During ON-state stress, electrons were dominantly trapped in the neutral traps near channel edge. These results cause degradation due to AC stress to become increasingly severe as W is scaled down. The operating voltage to guarantee 10-year lifetime decreased as width decreased. The above results show that electron trapping in neutral traps near the channel edge induce severe degradation on narrow nMOSFET during AC stress. Therefore, degradation of channel edge during AC stress is an importantly considered in narrow nMOSFET.

ABSTRACT. A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy. Post-processing of the data from the laser mapping facilitated the plotting of the cross-section versus laser energy curve. We found a clear shift in the crosssection curves after voltage stress of 130 hours. Comparisons of data revealed at least a doubled increase in sensitive areas after voltage stress. During the voltage stress, various electrical parameters were monitored and changes were observed. It was found that the increase in SEU sensitivity is related to electrical parameter changes and SPICE simulation results concur likewise.

ABSTRACT. Resistive switching in high-κ (HK) dielectric based metal-insulator-metal (MIM) devices occurs locally and is accompanied by dynamic changes in structural and electrical property of the HK dielectric. In polycrystalline HfO₂ HK dielectric based MIM devices, the presence of grain boundaries (GBs) play a significant role in the formation of a percolation path for the resistive switching as the GB regions contain large number of defects and favor the formation of conduction/low resistive paths. In this work, we present a multi-physics based combined Kinetic Monte Carlo- Finite element model (KMC-FEM) based 3D percolation framework to simulate the resistive switching (high resistive state (HRS) to low resistive state (LRS)) process in TiN/HfO₂ (~5nm)/Pt MIM stacks. The KMC-FEM model describes the effect of GBs on the nucleation of conduction path during the HRS to LRS resistive switching process. In addition, this model is used to find the statistical distribution of conductive path formation in amorphous and polycrystalline HfO₂ dielectrics. Conductive atomic force microscopy and transmission electron microscopy observations on the characteristics of the HfO₂ dielectrics at the nanometer scale complement the simulation results. The results clearly show that the resistive switching occurs preferably at the GB regions in polycrystalline HfO₂, whereas resistive switching in amorphous HfO₂ based MIM stacks occurs at random locations.

ABSTRACT. With deterioration of the electromagnetic environment, microcontroller unit (MCU) electromagnetic susceptibility (EMS) to transient burst interference has become a focus of academia and enterprise. Most electromagnetic compatibility (EMC) studies of MCUs have not taken the effects of aging into account. However, component aging can degrade the physical parameters of an MCU and change its immunity to EMI. This paper proposes a time-equivalent interval accelerated aging methodology combining DC electrical and high temperature stresses. The test results show variations in susceptibility to electrical fast transients (EFT) burst revealing increasing susceptibility. The reasons for MCU immunity drifts in the aging process are discussed.

ABSTRACT. Double side bonding technology has been applied in various electrified vehicles to realize higher power density by better cooling performance. This structure has an interface between power semiconductor device and solder on its top surface electrode. To enjoy the high power density potential of double side bonding structure, we have to care about new reliability aspect on it in terms of mechanical stress. In this talk, I will show new reliability demand on Si power semiconductor devices for electrified vehicles in case introducing new double side bonding structure.

ABSTRACT. Power electronics applications in electrified automotive powertrains demand for high robustness in technology selection and design for power modules. In drive inverters especially the active loading by currents, which heat up the chip and its surrounding, lead to significant temperature swings in the core of the module and initiates specific failure modes in the materials involved. Therefor the technology depended life-time curves exhibit a meaningful output parameter for the design of the entire powertrain.
New near chip technologies like Silver-sintering, diffusion soldering and Copper-bonding shift existing life-time curves to higher robustness. This means higher active power cycle numbers to failure at given temperature swing or higher temperature swings at given attainable power cycle numbers. This enables the operation of wide-band-gap power semiconductors like SiC and GaN at high temperature Tjunction values around 200°C and beyond. The initiation of new failure modes and the adaption of the latest qualification routines have to be taken into consideration for such equipped power modules.

ABSTRACT. The reliability for components used in cars is of highest importance. For traction inverters used in cars for e-mobility DC-link capacitors are one of the key components. Partners of the whole supply chain covering OEM to TIER2 have developed a significantly improved qualification standard for DC-link capacitors compared with the AEC-Q200. A uniform qualification procedure will help to decrease development costs and facilate the comparability of components of different suppliers. Capacitors qualified on basis of the new standard will help to even further increase the reliability of traction inverters in the future.

ABSTRACT. VALEO is currently developing sub-systems for new generation of electric powertrain (inverters, DC/DC converters...). As parts of these applications, semiconductors are subjected to very high stresses (especially thermal and cyclic) in their lifetime. Reliability database of electronic components such as FIDES, MIL-HDBK 217F, IEC/TR62380 have a lack of feedback for these new components for the automotive world, such as IGBT power modules. This is an issue for the pre-design phase, it is not possible to give a correct field returns on these components. That is why VALEO has developed a methodology and a tool to estimate the reliability of an IGBT power module for an inverter application based on the methodology used in the  reliability prediction for mechanics as strength-constraint methodology.

ABSTRACT. Incidents of electrical vehicle catching fire forced on a root cause analysis. Failure mode and effects analysis (FMEA) and fault tree analysis (FTA) approaches were used for failure  analysis and to design experiments on the battery system level. Analysis focused on the behaviour of an internal short circuit of a cell and its effect on the battery system and the vehicle. An internal short circuit of a stand-alone cell leads to venting and the release of dense smoke, however no fire or explosion occurred which complies with manufacturer declaration and hazard assessments according to battery safety standards. When such cell venting was triggered in the battery system it could be demonstrated that electric sparks on the carbonizing cell battery management print ignite the smoke and eventually lead to a fire of the complete vehicle. It has been shown that the use of comparatively safe Lithium-Iron-Phosphate cells does not entail a safe battery. The identification of the fire root cause enabled to develop and successfully test a mitigation method preventing fire caused by this failure mode.

ABSTRACT. The in-plane stress distribution in copper through silicon vias (TSV) ensembles of different design has been studied by the scanning infrared stress explorer (SIREX). SIREX is a reflection-based plane polarimeter particularly developed for the high-resolution stress state visualization in silicon-based electronic and mechanic devices. The SIREX method is based on the principle of stress-induced birefringence. We demonstrate that the silicon crystal matrix around the TSV is optically anisotropic with a stress distribution being similar to fields which are known from point-like stress sources. The maps of optical anisotropy have been converted into maps of difference of principal stress components Ds with a resolution of a few kPa. We show that magnitude and direction of Ds depend on the geometrical design of the TSV, in particular on length and diameter. The average radial profile of magnitude is discussed. In consequence, we offer a promising tool and method for the non-destructive evaluation of TSV structures in view of their stress characteristics and integrity.

ABSTRACT. This paper discusses the possibility of using Scanning Acoustic Microscopy in GHz frequencies for detection and analysis of stresses around TSVs. An innovative idea was employed to measure the slight variations in Rayleigh wave velocities as a function of Si crystal orientation using a spherical imaging lens. The fringe pattern around an empty TSV and a copper TSV were analyzed in different directions and Rayleigh wave velocities were calculated. The initial comparison between the measured velocities around the TSVs and the calculated values from a pure Si Crystal suggest the capability of using this technique in detecting Rayleigh wave velocity differences and thus, measuring stresses around Cu TSVs.

ABSTRACT. The formation of voids in metal layers upon stress-induced migration is a well-known defect mechanism in integrated circuits. This phenomenon largely accelerates with increasing ambient temperature. Consequently, the occurrence and the growth of voids result in an increased electrical resistivity which once more leads to an acceleration of the growth rate highly impacting the reliability and the life span of the device. Technological improvements aim at the minimization of stress induced voiding. However, for understanding and optimization of process related factors non- destructive methods for screening and systematic monitoring of the void formation e.g. during stepwise reliability testing are required. In the current paper, the formation of voids induced by repetitive thermal loads has been assessed and evaluated semi-destructively by employing Scanning Acoustic GHz-Microscopy. Prior to the acoustic inspection, sophisticated semi-destructive preparation was required to provide access to the region of interest. Voids with sizes below the acoustic resolution limit have been detected. The relative number and the size of appearance have been analysed using a custom made analysis software tool.

ABSTRACT. In the current paper the application of a custom developed 2-dimenional scanning magnetic field microscope based on tunnel-magnetoresistive sensors and subsequent qualitative and quantitative analysis is described. To improve sensitivity and to enable the detection and evaluation of phase deviations, an off-line lock-in approach was employed by driving the samples under test with an injected current at a fixed signal frequency. Amplitude and phase evaluation was based on simultaneous acquisition of the reference and the measurement signal obtained from the magnetic field sensor. This off-line lock-in approach enables not just the detection but also the estimation of changes in signal phase caused by capacitive, inductive or ohmic coupling of the induced currents. Furthermore assessed magnetic fields were converted into the current density by solving the inverse magnetic problem and post processing of the acquired signals. For verification of the developed set up the current density distribution was computed from experimentally acquired magnetic fields for a two-wire test structure. In addition quantitative values of the current density were derived for a calibration pattern containing defined structures. Finally, to evaluate the practical relevance a power MOSFET with unknown defect was analysed and an area of unexpectedly increased magnetic field intensity was observed.

ABSTRACT. A non-destructive method using X-ray imaging to find cracks in multilayer ceramic capacitors (MLCCs) mounted in different orientations with respect to the bending direction is presented. In total 300 MLCCs were investigated by 2D and 3D X-ray imaging after bending to varying levels of strain, and cross-section analysis was done to verify the findings. With X-ray imaging it was possible to not only detect the continuously cracked MLCCs, but also the cracked ones which were mounted 45° to the bending direction. These non-continuous cracks are difficult to identify even with cross-section analysis because the crack can be absent at the selected interface. None of the cracks could be identified by external optical inspection of the components using optical microscopy. The MLCCs mounted perpendicular to the bending direction were not cracked during the experiments, whereas the MLCCs mounted 45° or parallel to the bending direction were cracking at 3100 and 4300mStr, respectively. Finding cracks with a non-invasive technique such as X-ray imaging is very advantageous because of its possible implementation as a screening test in a production environment.