ABSTRACT. After any process reliability qualification some tool is needed which verifies the stability of the process throughout mass production. A continuous “fast Wafer Level Reliability” (fWLR) Monitoring is essential especially for stringent product reliability specifications of automotive, medical or space applications. “Zero Defect” programs are well known and manifest the implementation of fWLR Monitoring on product wafers. However, often used quarterly reliability re-qualification cannot achieve this quality goal and is inappropriate. Therefore, fWLR Monitoring must be employed, covering reliability topics such as dielectric quality, plasma induced damage, device degradation and metallisation reliability. Additionally, fWLR can support a fast assessment of reliability during process development, split investigations, process tool changes and process qualifications.

In this tutorial an overview will be given on dedicated fWLR test structures, highly accelerated stress measurements, data analysis and sampling. Further, the challenges and limitations of the fWLR methodology will be pointed out as well as benefits will be highlighted. The topics of an out of control action plan, the scrapping of wafers with fWLR and defect density monitoring will be addressed.

This tutorial is suited for engineers and scientists who start in the area of reliability monitoring. But also experts who already work on this topic will benefit since also advanced methods are described. Valuable details and literature citations can be picked up.

ABSTRACT. It is a truism that reliability is related to applications requirements. Robustness Validation (RV) is a methodology to provide data demonstrating that a product is “fit for use”. The ZVEI working group Robustness Validation was initiated 10 years ago. The concept has received increasing attention over this period, also beyond the automotive qualification procedures it initially originated from. The tutorial gives an overview of the basic concept of RV and experiences made in applying it to development and qualification. Two examples are discussed in detail: qualification of power modules and of  thin-film DC-link capacitors. It also discusses difficulties in applying  the concept.

ABSTRACT. After providing a brief introduction to Laser Voltage Probing (LVP), along with useful information and further reading suggestions, this paper provides a deep dive into current benefits and challenges of LVP applied to 16/14 nm FinFET technology and discusses the issues that arise from scaling of technology nodes according to the International Technology Roadmap for Semiconductors.

ABSTRACT. Electro Optical Techniques (EOP: Electro Optical Probing and EOFM: Electro Optical Frequency Mapping) are effective backside contactless methods for defect localization and design debug for VLSI. The image mode (EOFM) gives only one frequency at each scan. In this case, the frequency mapping is a long and hard task. Furthermore, temporal information is not included in EOFM mode. Building a map by point by point EOP is usually too long so it cannot be used as it is to extract all the frequencies of interest in a region of interest. To overcome this limitation, we have developed an automatic process using EOP mode with a wavelets approach and autocorrelation. Temporal and frequency information are simultaneously computed with only one acquisition. We will underline the challenge and define application boundaries of this technique.

ABSTRACT. Thermal Laser Stimulation (TLS) for static logic state analysis is applied to failure analysis. Three case studies of analyses of the digital logic in an automotive Application Specific Integrated Circuit (ASIC) are discussed. By analyzing the logic states of the circuit we were able to identify the mechanism and localize the site of irregular behavior non-destructively, both for a stuck-at fault and two weak interconnects. The approach measures the power supply current while applying TLS to the device back side. This allows an extremely high analysis coverage, because every transistor is connected to the power supply, making this method a universal tool for every digital circuit failure analysis (FA) workflow, because the gained understanding of the fault allows to replace multiple steps of alternative FA techniques by only a single technique, reducing time and cost for successful FA. 

ABSTRACT. Mobility is in a transition phase from individual human controlled to assisted and autonomous driving. Also, new roles add to car manufacturers being now forced to adapt to digital service providers as cars become the ultimate mobile office. Today, functional automotive requirements start to exceed on what’s on the market accompanied with huge reliability assurance process gaps along the supply chain. Standards are out dated, research data unavailable and activities to change this strongly bound to market dynamics and mass volume requirements. This is why reliability engineering and management becomes a leading role in product design and business model formation. Transparency about technological gaps and how they are being handled determine market positions. To create industry awareness, we demonstrate two examples out of an OEM driven study on mechanical induced parametric deviations which relate to corresponding product verification/validation issues that can end up in real, but which are mostly classified as no fault found (NFF) issues.

ABSTRACT. Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.

ABSTRACT. Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process
variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.

ABSTRACT. The introduction of thick copper metallization and topside interconnects as well as a superior die attach technology is improving the performance and reliability of IGBT power transistor technologies significantly. The much higher specific heat capacity and higher thermal conductivity increases the short circuit capability of IGBTs, which is especially important for inverters for drives applications. This opens the potential to further optimize the electrical performance of IGBTs for higher energy efficiency. The change in metallization requires the introduction of a reliable barrier against copper diffusion and copper silicide formation. This requires the development of an efficient test method and reliability assessment according to a robustness validation approach. In addition, the new metallization enables interconnects with copper bond wires, which yield, together with an improved die attach technology, a major improvement in the power cycling capability.

ABSTRACT. Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600 V, 30 A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.

ABSTRACT. The eutectic Au80Sn20 solder alloy has been applied in semiconductor assemblies and other industries for years. Due to some superior physical properties, Au/Sn alloy gradually becomes one of the best materials for soldering in electronic devices and components packaging but the voids growth in AuSn solder joints is one of the many critical factors governing the solder joint reliability. Voids may degrade the mechanical robustness of the die attach and consequently affect the reliability and thermal conducting performance of the assembly. Severe thermal cycles [−55 °C / +175 °C] have highlighted degradations in AuSn die attach solder. The inspection of as-prepared die-attachments by X-ray and SEM (observation of cross-section) shows that the initial voids sizes were increased and a propagation of transverse cracks inside the joint between voids has appeared after ageing, it was featured also the existence of the IMC typical scallop-shape morphology with the phase structure of (Ni, Au)3Sn2 on as-reflowed joints. In this paper, we evaluate the origin of these degradations and ways to address them.

ABSTRACT. Reliability of advanced VLSI circuits becomes more and more important as both product designers and manufactures relentlessly pursue technology advantages and stretch device physical limits to capitalize the consumer electronic market. In this paper, we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. We have characterized the delay degradation of LUT dependent on the duty cycle and the frequency of stress signal. We have identified that the HCI degradation mechanism affects the fall delay more than the rise delay, it is related directly to the frequency stress and independent from the duty cycle. In addition, we built a model of the delay degradation due to HCI depending on switching frequency of stress signal and the aging time. Furthermore, we identified the relation between the effect of each aging transistor and the LUT delay for the HCI aging mechanism. This work is ideal for modelling the LUT aging mechanisms in FPGA.

ABSTRACT. In memory technology, size reduction induces consequences in terms of reliability, including an increase in the line resistances and a voltage drop along the line during memory operation. This problem can occur in Flash products during sector erase mode, and in resistive RAM (ReRAM) during forming, reset or word-reading modes. In this paper we apply a simple resistive model to determine the wordline (or bitline) length of a Flash memory (and thus to optimize the Flash memory array's size) or the word length of a ReRAM, according to specific reliability criteria: the threshold voltage drop of cells along a line in a Flash memory sector, or the resistance variation of the cells in a ReRAM word.
For the technologies considered in this paper, on the one hand we demonstrate a maximal threshold voltage drop of 2V for a 4 Gbit Flash array and we provide design recommendations, and on the other hand we demonstrate that a maximal word length of 32 bits for ReRAM can be achievable in a ReRAM matrix. The presented methodology can easily be extended to any memory technology.

ABSTRACT. SiC MOSFETs reliability issues remain a challenge that requires further investigation. In this article, a short-circuit aging test was developed to characterize the electrical parameter evolution. The threshold voltage and gate drain capacitance seem to be relevant degradation indicators. These two parameters indicate a gate oxide degradation. Electron trapping in the oxide layer could be the mechanism behind this deterioration.

ABSTRACT. This paper proposes a novel mission-profile-based reliability analysis approach for stress on bond wires in Silicon Carbide (SiC) MOSFET power modules using statistics and thermo-mechanical FEM analysis. In the proposed approach, both the operational and environmental thermal stresses are taken into account. The approach uses a twodimension statistical analysis of the operating conditions in a real one-year mission profile sampled at time frames 5 minutes long. For every statistical bin corresponding to a given operating condition, the junction temperature evolution is estimated by a thermal network and the mechanical stress on bond wires is consequently extracted by finite-element simulations. In the final step, the considered mission profile is translated in a stress sequence to be used for Rainflow counting calculation and lifetime estimation.

ABSTRACT. Reliability physics of silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (MOSFET) is not sufficiently clear; therefore an accurate estimation method of lifetime has been strongly required. The
relationship between the failure time of 4H-SiC double implanted MOSFETs under high temperature reverse bias test and the doping concentration in a drift layer was studied to clarify the failure physics. The failure time of the device showed dependence on the doping concentration in the 150 mm wafer. The breakdown occurred at the gate oxide over the threading dislocation in the JFET region. The electric field simulation indicated that the oxide electric field linearly depends on the doping concentration, which means the failure time depends on the oxide electric field. According to these results, the electric field acceleration tests were conducted with the samples in the uniform area of the doping concentration so as to exclude the distribution of the oxide electric field in each sample. The lifetime showed dependence on the oxide electric field varied by the drain bias intentionally. These results revealed the importance of the doping concentration uniformity of the epitaxial layer and we established the method to estimate the lifetime accurately.

ABSTRACT. This work describes a novel analysis method for the power cycling test, developed for high voltage and temperature silicon carbide diodes. The silicon carbide devices working at temperatures beyond 170°C, the maximum temperature rating for silicon devices, need specific reliability tests adapted to high temperature operation of this new generation of power devices. The specificity of the further presented method consist in the use of 10ms sinusoidal power current pulses that are able to evidence the temperature developed inside the diode during the power pulse, the temperature characteristic delay versus the applied current and the temperature calibration method. Moreover, this overall method is able to evidence the transformations occurred in the bonding contact and the dye attach.

ABSTRACT. SiC is a wide bandgap semiconductor with better electrothermal properties than silicon, including higher temperature of operation, higher breakdown voltage, lower losses and the ability to switch at higher frequencies. However, the power cycling performance of SiC devices in traditional silicon packaging systems is in need of further investigation since initial studies have shown reduced reliability. These traditional packaging systems have been developed for silicon, a semiconductor with different electrothermal and thermomechanical properties from SiC, hence the stresses on the different components of the package will change. Pressure packages, a packaging alternative where the weak elements of the traditional systems like wirebonds are removed, have demonstrated enhanced reliability for silicon devices however, there has not been much investigation on the performance of SiC devices in press-pack assemblies. This will be important for high power applications where reliability is critical. In this paper, SiC Schottky diodes in pressure packages have been evaluated, including the electrothermal characterisation for different clamping forces and contact materials, the thermal impedance evaluation and initial thermal cycling studies, focusing on the use of aluminium graphite as contact material.

ABSTRACT. Probing electrical properties of state-of-the-art electronic devices is one of the key features of Scanning Microwave Microscopy. While providing valuable information on charge carrier properties, the combination of an atomic force microscope cantilever with a microwave signal raises the question on the actual spatial resolution of the system. On the example of the highly confined two-dimensional electron gas of an AlGaN/GaN structure, the effective tip radius is demonstrated to be in the range of the theoretical tip radius for sharp tips, while both values differ for unevenly shaped cantilever tips. The presented method demonstrates the role of the microwave excitation region for the spatial resolution of the system as well as the potential of this method to characterise the effective tip radius.

ABSTRACT. Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28 nm samples inside an SEM. The employed techniques include nanoprobing as well as EBAC. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults. In this case, Current Imaging provides insight into the sample's behaviour yielding qualitatively comparable results to the more cumbersome cAFM technique. While the results of the TEM investigations including EDX mappings were inconclusive, the Current Imaging technique clearly shows that the root cause is located below the SiGe layer. By combining these techniques inside a FIB/SEM microscope, it is possible to locate and characterize a failure as well as prepare a TEM lamella for further investigation without the necessity to switch to a different tool.

ABSTRACT. Implantation is the key process in the modern semiconductor process which forms the basic device cell by different doping ditribution, depth, angle and element type. They are the key factors to affect the transistor performance, but the implantation-related defect is invisible by the normal failure analysis method. Then electrical analysis and verification is necessary to visualize this kind of defect. Electrical theory is important in this kind of failure analysis to indirectly proven the problematic process. The transistor body effect is a well know effect which is utilized in some kind of IC design to change the transistor Vth for certain purpose. But nobody uses this effect for the implantation-related failure analysis since the implant itself is complex and is not ideally uniform as the theory model. In this paper, implantation-related defect was successfully identified by the application of transistor body effect combined with nanoprobing on the localized structure.

ABSTRACT. With continuous scaling on CMOS device dimensions, it is becoming increasingly challenging for conventional failure analysis (FA) methods to identify the failure mechanism at the circuit level in an integrated chip. Scanning Electron Microscopy (SEM) based nanoprobing is becoming an increasingly critical tool for identifying non-visual failures via electrical characterization in current electrical FA metrology for fault isolation since 2006 [1-3]. Currently, most of the nanoprobing fault isolation is nanoprobe in top-down planar direction, such as nanoprobe on via, contact and metal line. This paper focused on fault isolation of sub-micron devices by nanoprobing on a crosssectional plane. This is a new application area; it is very useful for sample that cannot perform fault isolation with conventional top-down planar nanoprobing, especially on non-volatile memory that with single transistor memory array that arrange in a vertical direction, such as Magnetic Random Access Memory (MRAM), Phase-Change Random Access Memory (PC-RAM), flash memory and etc.

ABSTRACT. For measurement of electrical characteristics it is essential to supply an electrical current or apply a voltage to the circuit. This study have been carried in order to realize the creation of a stable electrical current flow in the microscopic region only by using the charged particle beams, without requiring contact of the mechanical probes. And it was revealed that stable and constant current flow can be achieved in a self-aligned current-controlling manner by utilizing the secondary electrons. We also have clarified that the mechanism of stabilizing current in a self-aligned manner is dependent on space charge limited current of secondary electrons.

ABSTRACT. In this paper, a numerical description of the ruggedness of punch-through (PT) IGBTs under the unclamped inductive switching (UIS) has been proposed using two-dimensional (2D) simulations with the calibration to experimental results. The UIS capability is an important design factor of device structures for the purpose of screening defects produced during the wafer process. The local hot spot due to the current filament threedimensionally (3D) distributed over the chip area requires 3D simulations to reproduce the current density of the filament and its behavior leading to the device destruction; however, it is difficult to simulate such a large area with an appropriate mesh size and a boundary condition. To provide a possible solution of this technical issue, 2D simulations using large scale multi-cell structures with the increased current density has been proposed to reproduce experimental results without resorting to 3D simulations. With this approach, not only destructive phenomena including the UIS ruggedness and the latch-up failure mode have been reproduced, but also the device internal state leading to the destruction has been revealed. The spatial distribution of the electric potential and the lateral electric field during the UIS condition is shown to be a key role determining the current filament width and the UIS ruggedness. Besides, the high frequency oscillation of the collector voltage during the UIS observed by experiments has been analyzed and has found to be related with the hopping motion of the current filament from a cell to its neighboring cell of the device.

ABSTRACT. A complete Accelerated Life Test on high luminosity blue LEDs is presented. The test was conducted at different temperatures, humidity and current conditions, involving a total of seven individual tests. Life models were obtained for the catastrophic failures of the tests and then a complete temperature, humidity and current model was developed, which enabled the calculation of the life of the LEDs for any of these conditions. Catastrophic failures and model parameters were consistent with earlier results using different high luminosity LEDs. Non-catastrophic failures were modelled with their corresponding luminous power loss on each test, with expected results.

ABSTRACT. With the global interests and efforts in popularizing low carbon vehicles, automotive power module has been becoming one of the fastest growing sectors in power semiconductor industry. As working in a harsh environment, the performance and reliability requirements of automotive module are stringent than industrial products. In this work, an integrated direct liquid cooled power module with enhanced reliability for hybrid and electric vehicles (HEV/EV) is developed. The design and assembly of the module were optimized in terms of performance, weight, cost and reliability. The module is integrated Al direct liquid cooling structure, leading to about 40% reduction of weight and cost and almost 50% reduction of junction to heat sink thermal resistance. Therefore, the junction temperature stays below the upper limit at the worst operation case which enhances the thermal reliability and lifetime. By incorporating advanced die lead bonding, the parasitics can be reduced by 50%, which is beneficial to efficiency and reliability. Furthermore, the die and terminal attach technologies are investigated to improve reliability. The lifetime prediction under a typical driving cycle shows that the proposed module is capable of working in the whole vehicle service period.

ABSTRACT. We have developed a printed circuit board Rogowski coil for monitoring of current and protection of highvoltage power modules and packages. It is small, thin, and inexpensive current sensor and is almost the ideal Rogowski coil because of its fishbone pattern. For noise reduction under high-voltage/-current conditions in a module, shield layers and coaxial connector are employed. In addition, a new, fast simulation tool was developed to optimize the main coil pattern for realization of arbitrary printed circuit board geometry in specific, limited spaces.

ABSTRACT. This study investigates the degradation of light-emitting diode (LED) lamp modules by various stress–load test approaches, namely, step-up stress accelerated degradation testing, step-down stress accelerated degradation testing (SDSADT), and constant stress accelerated degradation testing. Two types of commercial LED lamps with different capabilities of heat dissipation (CHDs) are utilized in the experiment. LM-80 testing on two types of LED packages is further implemented to reproduce the degradation reaction of Lamp B. Result shows that SDSADT can effectively alleviate the initial increase in optical parameters. Lamp B with a strong CHD exhibits a similar lumen decay rate at each stress of step stress testing; this similarity implies that the decay rate of Lamp B is only related to the current loaded stress. The lumen decay rate of the initial decay paths for Lamp B as the thermal stress increases exhibits a parabolic law. This parabolic pattern is also detected in the LM-80 testing for the LED packages and is explained by the strong CHD of Lamp B. The thermally induced mechanisms, which influence the optical emission of LEDs, should be responsible for the parabolic decay law. Moreover, the color shift of the LED modules with increasing loaded stresses is more sensitive than lumen degradation.

ABSTRACT. The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.

ABSTRACT. The thermal properties and reliability of novel heatsinks that use high thermal conductivity graphite were investigated. Graphite plates with different high-thermal-conductivity directions were laminated together
using an Ag-based brazing material, with thin Cu plates on their outer surfaces. The heatsinks were bonded to Si heater chips using Sn-3Ag-0.5Cu solder. Samples with conventional Cu or Cu-65Mo heatsinks were also fabricated as references. The samples were attached to an active cooling plate subjected to a constant water flow, and thermal and reliability measurements were conducted. The experimental results were also compared with the results of a finite element analysis. The novel laminated heatsinks exhibited a lower thermal resistance than the Cu or Cu-65Mo heatsinks, and the experimental results were in reasonable agreement with those of the finite element analysis. The graphite-based heatsinks had better power cycle reliability than Cu-based heatsinks. Therefore, these novel graphite heatsinks have potential for application to power semiconductor modules, it seems to be useful for applications with high heat flux of power semiconductor devices.

ABSTRACT. Under operation the topside metallization of power electronic chips is commonly observed to degrade and thereby affects the device electrical characteristics. However, the mechanisms of the degradation process and role of environmental factors are not yet fully understood. In this work, we investigate the metallization degradation by passive thermal cycling of unpackaged high-power diode chips in different controlled atmospheres. The electrical degradation of the metallization is characterized by sheet resistance measurements, while the microstructural damage is investigated by scanning electron microscopy (SEM) and X-ray diffraction (XRD). To study the evolution of chemical composition of the metallization, energy dispersive X-ray spectroscopy (EDX) is also applied. Since the degradation depends on initial microstructure of the metallization, the film texture and grain size distribution is determined using electron backscatter diffraction (EBSD). The obtained data show that the type of atmosphere plays a minor role in the degradation process, with a slight tendency that cycling in dry nitrogen atmosphere accelerates the degradation compared to the experiments in ambient atmosphere with controlled relative humidity of 50 and 95%.

ABSTRACT. With technology scaling of semiconductor devices and further growth of the integrated circuit (IC)1 design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology. When come to PFA2 on the flip-chip devices with solder bump, wet etch for solder bump removal is an essential method. Upon using wet etch methodology; it is very dependent on etching timing and the chemical aggressiveness to get a good removal result for the solder bump. If there is an excessive period in etching or chemical reacts too aggressively, chemical over-etched on bond pad will occur. It is very unfavorable for FA3 engineer to perform subsequent reverse engineering on the bond pad over-etched device. In this paper, the application of laser deprocessing technique is proposed to solve the bond pad over-etched issue. This proposed technique is a quick and reversal way in deprocessing technique for defect identification in PFA.

ABSTRACT. Reliability is one of the key issues for the application of Silicon carbide (SiC) diode in high power conversion systems. For instance, in high voltage direct current (HVDC) converters, the devices can be submitted to high voltage transients which yield to avalanche. This paper presents the experimental evaluation of SiC diodes submitted to avalanche, and shows that the energy dissipation in the device can increase quickly and will not be uniformly distributed across the surface of the device. It has been observed that failure occurs at a fairly low energy level (<0.3 J/cm²), on the edge of the die, where the electrical field intensity is the greatest. The failure results in the collapse of the voltage across the diode (short-circuit failure mode). If a large current is maintained through the diode after its failure, then the damage site is enlarged, masking the initial failure spot, and eventually resulting in a destruction of the device and an open circuit.

ABSTRACT. Cross-sectional analysis is one of the important areas for physical failure analysis. Focus Ion Beam (FIB) and mechanical polish sample preparation are commonly used and necessary techniques in the semiconductor industry and Failure Analysis (FA) Company [1]. However, each technique has its own limitation. Mechanical polishing technique easily induces artifact by mechanical force, especially on advance technology node. FIB can eliminate mechanically damaged artifact, but have the limitation on cross-sectional view area. Another potential technique will be plasma FIB, it used very high milling current and fast milling speed [2]. However, it comes with a very high cost and having the contamination issue. The contamination issue greatly affects the low kV Scanning Electron Microscopy (SEM) imaging quality. In recent semiconductor industry FA, low kV SEM imaging is preferable, because high kV imaging will introduce delamination artifacts especially on organic material from packaged sample. In this paper, Fast Laser Deprocessing Techniques (FLDT) application is further enhanced on large area cross-sectional FA with fast cycle time and low-cost equipment [3-4]. This is to prevent from mechanical damage. In short, the proposed FLDT is a costeffective and quick way to deprocess a sample for defect identification in cross-sectional FA.

ABSTRACT. The NBTI (Negative Bias Temperature Instability) performance of 28nm HfO2-based HKMG (High-κ Metal Gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (In-Situ Steam Generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (Post Deposition Anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (Decoupled Plasma Nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (Electrical Oxide Thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.

ABSTRACT. The mechanism that phosphorus (P) impurities, one of the most commonly used impurities in silicon (Si), affect the tensile mechanical responses of [1 1 0]-Si nano-wires (NWs) is investigated using molecular dynamics (MD) with a Modified Embedded Atom Method (MEAM) potential. Tensile tests at 300K are carried out for unnotched and notched Si NWs. For unnotched cases, P impurities randomly replace Si atoms at specific concentrations. Two patterns are considered for notched models, one undoped and one with doped notch tip. Results show that evenly distributed P impurities introduce an overall decrement in fracture strength of unnotched Si NWs as the concentration increases. The failure manner is that the local defects come into being around P, then rapidly nucleate and propagate, finally lead to fracture. However, for notched models, P can evidently enhance the fracture strength by impeding the cracking and growth of pre-existing cracks. With regard to Si NWs with surface defects exposed to strain, fracture usually starts from surface owing to stress concentration, indicating that P functions more critically on surface, especially near crack tips. Hopefully, this finding can be applied in the reliability design of Si-based NW devices. Moreover, when doped with P or notched on surface, the transition of failure mode for 2nm and 3nm NWs can happen, namely from ductile to brittle.

ABSTRACT. This paper discusses the universal calculation method for space proton induced failure rate on high power device. High energetic particles can be the reason of power device failure in both terrestrial and space. T-CAD simulation result gives a threshold charge value for the device destruction which is triggered by energetic proton from space. The amount of threshold charge depends on applied voltage for high power device. The probability of charge generation in silicon due to proton penetration is considered as well. This probability function variation depends on the thickness of device and incident energy of proton which studied before at there. Last consideration on this paper is 3.3 kV PiN diode’s single event upset cross section and failure rate which was calculated by proposed method in Low earth orbit environment condition.

ABSTRACT. The work presented here is related to the utilization of EDA tools in combination with real time images from analytical equipment in order to improve the efficiency of Failure Analysis. The new developed applications help to better understand the design, as well as to provide capabilities to overlay signal traces in analog and logic domains of the chip, with real time images obtained from fault localization techniques. Thanks to this enhanced design visibility, the FA process can be performed with more efficiency. In this work we put special focus on interrupted scan chains. Results of diagnosis tools (simulation) and backside imaging tools (analytical measurements) are combined in order to provide very accurate results. The subsequently performed, destructive, physical analysis greatly benefits from precise and confirmed fault localization. In addition, we present the advantages of real-time simulation for imaging and probing analysis in term of immediate assessment of the diagnosis results quality.

Our flow includes tools to start ATPG and BIST. We use diagnosis software including the latest options to improve the accuracy of localization [1], [14] and [15]. CAD Navigation and schematic view tools are brought up along with graphical drag and drop capability between them. This guides the FA engineers to visualize in significantly less time the result of diagnosis and fault localization simultaneously. Dedicated patterns can be generated to improve the accuracy of diagnosis. We demonstrate applications specialized to analyse in particular failing scan chains in complex SOC and analog IP.

ABSTRACT. The continuing decrease in structure and defect size in devices has driven many applications away from SEM towards thin sample preparation and TEM investigation. The latest FIB/SEM technology has the capability to image structures down to less than 5nm on a bulk or thin specimen but cannot provide supporting chemical information from EDS. Here we investigate a new more sensitive EDS detector, which for the first time provides chemical information at these high spatial resolutions on the SEM. We outline operating conditions that are suitable to chemically resolve semiconductor structures below 20nm. Based on these results we propose workflows to speed up failure analysis by obtaining the analysis result directly in the FIB/SEM without the need for TEM analysis. 

ABSTRACT. In 3D integrated microelectronics, the failure analysis of through silicon vias (TSVs) represents a highly demanding task. In this study, defects in tungsten coated TSVs were analysed using scanning acoustic microscopy (SAM). Here, the focus lay on the realization of an automatized failure detection method towards rapid learning. We showed that by using a transducer of 100 MHz center frequency, established with an acoustical objective (AO), it is possible to detect defects within the TSVs. In order to interpret our analysis, we performed acoustic wave propagation simulations based on the elastodynamic finite integration technique (EFIT). In addition, high resolution X-ray computed tomography (XCT) was performed which corroborated the SAM analysis. In order to go towards automatized defect detection, firstly the commercially available software “WinSAM8” was enhanced to perform scans at defined working distances automatically. Secondly, a pattern recognition algorithm was successfully applied using “Python” to the SAM scans in order to distinguish damaged TSVs from defectfree TSVs. Besides the potential for automatized failure detection in TSVs, the SAM approach exhibits the advantages of fast and non-destructive failure detection, without the need for special preparation of the sample.

ABSTRACT. The AECQ-006 (Automotive Electronics Council Qualification Requirements for components using Cu wire) requires stitch pull tests on decapsulated Cu wire devices after TMCL and HAST/THB testing. The challenge is to perform decapsulation that exposes the complete interconnect without damaging the wires, leads or bondpads. A new method was developed in NXP to achieve this goal. An existing Cu wire decapsulation recipe was improved to protect the leads by adding Benzotriazole or AgNO3 to the nitric/sulphuric acid mixture.

ABSTRACT. An alternative integration scheme for a half-bridge switch using 70 mm thin Si IGBTs and diodes is presented. This flat switch, which is designed for high-frequency application with high power density, exhibits high strength, high toughness, low parasitic inductance and high thermal conductivity. Such a novel assembly approach is suitable to optimize performance, reliability and availability of the power system in which it is used. The paper focuses on the thermal performance of this assembly at normal and extreme operating conditions, studied by means of FEM thermofluidynamic simulations of the module integrated with connectors and liquid cooler, and thermal measurement performed on an early prototype. Improved solutions are also investigated by the FE model.

ABSTRACT. In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially. Power electronics is a prerequisite to enable the exponential growth of power density. Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5 K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42 K/W by the construction of a double side chip cooling. A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe. This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000 V DC. The outlook onto an integrated 120 A 700 V SiC MOSFET demonstrator is given.

ABSTRACT. The present work proposes a methodology to predict radiation-induced Single Event Transient (SET) phenomena within the silicon structure of Flash-based FPGA devices. The method is based on a MonteCarlo
analysis, which allows to calculate the effective duration and amplitude of the SET once generated by the radiation strike. The method allows to effectively characterize the sensitivity of a circuit against the transient effect phenomenon. Experimental results provide a comparison between different radiation tests data, performed with different Linear Energy Transfer (LET) and the respective sensitiveness of SETs.

ABSTRACT. Power converter systems in most of the applications are operated continuously with dynamically varying and highly inductive loads. The operating environmental conditions of the IGBT modules in such power converter systems is highly dependent on the thermal management. Hence, the operating conditions can be adverse when the system thermal management is not optimal. All this eventually triggers wear out failures in the power modules. The on-state voltage and threshold voltage have been usually considered in the literature to investigate the device degradation in power modules. In this paper, a novel online computation method for the on-state resistance (rCE) of IGBT modules to develop the health monitoring model for power modules in off-shelf power converter system is proposed. The on-state resistance of power module is investigated so that it could be used as a potential precursor to identify aging of devices with solder die degradation as a failure mechanism.

ABSTRACT. Precise location of leakage in a P-WELL/N-WELL junction has been identified by an AFM (atomic force microscope)-based nanoprober. In order to provide the accurate position of the failure for further analysis, a new method was proposed by combining nanoprobing I-V results on each P-well/N-well contact together with semi-empirical calculation to identify the possible leakage path. Further plan view TEM analysis confirms our result.

ABSTRACT. A flexible amorphous/microcrystalline Si:H (a-Si:H/μc-Si:H) tandem-junction photovoltaic (PV) module was produced in which a thin film of ZnO:B grown by metalorganic chemical vapor deposition (MOCVD) served as the transparent conducting oxide (TCO). The Hall mobility of ZnO:B is degraded by damp heat, simulated here using the conditions of 85°C at 85% relative humidity; this affects the series resistance and efficiency of the PV module. In this study, ZnO:B was treated by H/Ar plasma to reduce the degradation experienced under damp heat. The degradation time of the Hall mobility of ZnO:B, defined as the time necessary for the cell to reach the efficiency loss of -20%, was improved by ~54% by H/Ar treatment (ZnO:B•H/Ar). The mechanism behind this improvement was investigated by assessing the reactions of the ZnO:B and ZnO:B•H/Ar thin films to moisture. Related changes in the physical and chemical properties of ZnO:B and ZnO:B•H/Ar were analyzed by X-ray photoelectron spectroscopy, secondary-ion mass spectroscopy, and ultraviolet photoelectron spectroscopy. The analyses showed that the concentration of OH- was high while those of Zn2+ and B3+ were low in the grain boundaries of the ZnO:B surface after exposure to humidity. After H/Ar treatment, the increase in OH-concentration in ZnO:B was reduced, and the decrease in the Zn2+ and B3+ concentrations was much smaller. The H/Ar plasma treatment of ZnO:B affected the surface reaction forming Zn(OH)2, between the OH- and Zn2+ ions at the grain boundaries under damp heat.

ABSTRACT. In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200-600K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (Ids) and other for cut-off frequency (fT) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of Ion/Ioff, Subthreshold Swing (SS), device efficiency, fT, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.

ABSTRACT. The demands on reliable and fault tolerant power electronic devices are increasing. One opportunity to increase the IGBT short circuit ruggedness is to modify the thermal capacitance and the thermal resistance close to the chip and hence extend the possible short circuit duration. Therefore simulations with different metallization, bond wire and chip interconnect materials are compared to identify the most promising solution for enhancing short circuit capability of IGBTs.

ABSTRACT. This investigation focuses on determining the temperature-dependent leakage current limits which compromise the blocking safe operating area for silicon IGBT technologies. A discussion of a proper characterization method for selecting the maximum rated junction temperature for devices operating at high temperatures is given by comparing the different testing methods: Static performance (including and excluding self-heating effects), Short Circuit Safe Operating area and High-Temperature Reverse Bias. Additionally, a thermal model is used to predict the junction temperature at which thermal runaway takes place. In this paper guidelines are proposed based on the correlation among short circuit withstand capability and off-state leakage current for guarantying reliable operation and ensuring that they are thermally stable under parameter variations. This study is helpful to facilitate application engineers for defining the correct stability criteria and/or margins in respect of thermal runaway.

ABSTRACT. A special feature of vertical power MOSFETs, in general, is the inbuilt body diode which could eliminate the need of having to use additional anti-parallel diodes for current freewheeling in industrial inverter applications: this, clearly, subject to their demonstration of an acceptable level of reliability. Recent improvements in Silicon Carbide (SiC) power MOSFET device manufacturing technology has resulted in their wider commercial availability with different voltage and current ratings and from various manufacturers. Hence, it is essential to perform characterisation of its intrinsic body diode. This paper presents the reliability assessment of body diodes of latest generation discrete SiC power MOSFETs within a 3-phase 2-level DC-to-AC inverter representing realistic operating conditions for power electronic applications.

ABSTRACT. Photovoltaic (PV) modules are exposed to high-voltage stress between grounded module frames and solar cells, a configuration called potential-induced degradation (PID). Since PID mainly depends on the solar cells used for module packaging, several steps for PID tests can be omitted. We carried out PID tests on the cell level with Na fault injection in accordance with IEC 62804 and examined the extent of PID with saturation current density (J02) extracted from I-V measurements in the dark. Na-fault injection is a reasonable means for performing PID tests on the cell level without module packaging.

ABSTRACT. Run-time TID test in SRAM based FPGAs can improve reliability in space applications, but none feasible approach has been presented. This paper proposes a lightweight built-in test approach, in which the propagation delay of combinational logic in FPGA is measured with ring oscillator in runtime. The differences between propagation delays in different time slots are provided as the metric of TID degradation. The irradiation experiments on Xilinx Zynq chip prove the validity of the proposed method.
 

ABSTRACT. Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits. Besides, Spin Transfer Torque Magnetic Tunnel Junction (STT-MJT) has been identified as the most promising candidate for low power and high speed applications. In this paper, we present two majority voter circuits based on nanometer STT-MTJ. By using STMicroelectronics FDSOI 28nm process and a precise STT-MTJ compact model, electrical simulations have been carried out to compare their performances and analyze their reliability. Both radiation sensitivity and variability have been investigated in the reliability-aware analysis.

ABSTRACT. The choice of the right statistical model to describe the distribution of switching parameters (forming, SET and RESET voltages) is a critical requirement for RRAM, as it is used to analyze the worst case scenarios of operation that have to be accounted for while designing the cross-bar array structures, so as to ensure a robust design of the circuit and reliable data storage unit. Several models have been proposed in the recent past to characterize the voltage variations in VFORM, VSET and VRESET using the percolation framework. However, most of these models assume defect generation to be a Poisson process and apply the standard Weibull distribution for parameter extraction and lifetime extrapolation. Recent dielectric breakdown studies both at the front-end as well as back-end have shown that the Weibull statistics does not describe the stochastic trends well enough, more so in downscaled structures at the low and high percentile regions given the possibility of defect clustering which is either physics-driven or process quality-driven. This phenomenon of defect clustering is even more applicable in the context of resistive random access memory (RRAM) devices, as switching occurs repeatedly at ruptured filament locations where defect clusters pre-exist. This study examines the validity of the clustering model for RRAM switching parameter statistics (time / voltage to FORM, SET and RESET) and presents a physical picture to explain the origin of clustering in RRAM. A large set of data from various published studies has been used here to test the suitability and need for aclustering model based reliability assessment. Dependence of the clustering factor on temperature, voltage, device area, dielectric microstructure and resistance state has been examined.

ABSTRACT. Common problems with Oxide-based Resistive Random Access Memory (so-called OxRRAM) are related to high variability in operating conditions and low yield. Although research has taken steps to resolve these issues, variability remains an important characteristic for OxRRAMs. In this paper, a test structure consisting of an OxRRAM matrix where each memory cell can be configured as a ring oscillator is introduced. The oscillation frequency of each memory cell is function of the cell resistance. Thus, the test structure provides within-die accurate information regarding OxRRAM cells variability. The test structure can be used as a powerful tool for process variability monitoring during a new process technology introduction but also for marginal cells detection during process maturity.

ABSTRACT. In nanotechnology domain, reliability is a fundamental concern in the design and manufacturing process of VLSI circuits. Thus, this paper presents a tool developed to evaluate the reliability of logic cells in order to provide a set of information to improve design robustness. The tool is able to evaluate logic cells under Single Event Transient (SET) faults and, also, permanent faults such as Stuck-On (SOnF) and Stuck-Open (SOF). The information produced by this tool help designers to choose the most reliable cells to be adopted in their designs.

ABSTRACT. In this paper the Electrostatic Discharge (ESD) capability of 200 V Fast Recovery Epitaxial Diodes (FREDs) is analysed by means of suitable experiments, TCAD simulations and theoretical analyses. Different doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The newly fabricated devices show a remarkably high ESD capability without any significative loss in forward voltage drop and a reduction of the breakdown voltage that does not affect device rating.

ABSTRACT. This study characterized aluminum polymer capacitors, especially when they are charging and discharging. Tests were conducted under various conditions. The following environments were considered: three hightemperature conditions, two high temperature/high humidity conditions, and room temperature. Various operating conditions were also considered, such as charging–discharging, operating, and storage. The test results showed that the capacitance of the wound polymer aluminum capacitor degraded with charging–discharging at low temperature. At lower temperatures, this characteristic accelerated but was mitigated with a dry electrolyte. The degraded capacitances partially recovered when the capacitors were stored at a high temperature. These characteristics were not observed for a conventional liquid aluminum capacitor. This unreported special characteristic of polymer aluminum capacitors should be considered when designing systems such as power electronics. Polymer capacitors are known for their high reliability, especially at high temperatures. At low temperatures, however, the charging–discharging characteristic should be carefully considered. This paper reports on this characteristic of polymer capacitors for consideration by industries.

ABSTRACT. Focused ion beam (FIB) milling is a widely used and important technique to prepare Transmission Electron Microscopy (TEM) lamella samples. However, it unavoidably introduces contamination on the samples, typically by Ga ions implantation. This study presents an Atom Probe Tomography (APT) analysis together with a computer simulation based on a dynamic Binary Collision Approximation (BCA) model to predict such contamination on silicon samples. Conventional BCA models like SRIM is useful to predict ion implantation on the substrate. But it is not able to describe situation like FIB milling, where significant material transport happens. In this study, a dynamic BCA model is used to describe FIB milling and the simulated Ga contamination results are discussed jointly with APT experiment results. The strong agreement between the two shows the dynamic BCA model is applicable to predict FIB induced Ga ion contamination on silicon samples.

ABSTRACT. In order to evaluate the mechanical robustness of 28nm BEOL on the µm-scale, two non-standard mechanical test methods were used and will be presented in the talk. First an in situ micro pillar bending test and second a cross sectional nanindentation method. These applications will demonstrate their value for finding appropriate integration schemes for improved robustness.

ABSTRACT. 3D integration in microelectronics has been generating the need for new, massive ablation techniques of sample preparation. This challenge is addressed with microPREP^TM, Gatan’s all-new, laser-based preparation tool. Using an ultrashort pulsed laser, synchronized hardware, and a dedicated laser micromachining scheme, large-area, smooth, vertical flanks are prepared. Two workflows will be discussed, complementing the laser cutting either by broad ion-beam or FIB polishing. While the former facilitates the preparation of hundreds of TSV’s within less than two hours, the latter workflow is more surgical in character.

ABSTRACT. Copper has found immense applications within the semiconductor industry. In order to make site-specific alterations using focused ion beam (FIB) at nanoscale levels, it is imperative we manage to operate on polycrystalline copper directly with no need for an extensive grain size and orientation study prior to performing FIB milling operations. Homogenous copper FIB milling arises from the need to perform various circuit edit operations below the dielectric layer following the copper layer.  If the layer beneath the dielectric is affected by inhomogeneous milling, it can lead to short-circuit and eventual device breakdown [1-2]. Failure analysis on an integrated circuit was performed using rocking stage with 6-axes piezo movement capabilities together with the novel approach of the combined Xe-plasma ion source FIB and SEM system (XEIA) [3-5]. Site-specific milling of copper with different milling strategies were tested to optimize time and homogeneity of the milling across the target surface and to overcome the channelling effect posed by polycrystalline copper. Only during the last few nanometres of copper layer the water vapour is used to protect the dielectric layer. The complete removal of copper was followed with XeF₂ assisted milling of the dielectric layer to observe the unharmed circuitry [6]. Channelling effect was reduced by regulating the sputtering rates across different grains keeping the underlying dielectric layer safe. High-resolution scanning electron microscopy (HR-SEM) imaging was used for constant monitoring of the removed material to help modulate the process for highest throughput in the least possible amount of time.

ABSTRACT. TEM sample preparation and liftout is standard task for a large number of FIB/SEM tools in laboratories around the world. Especially for high-throughput environments, but equally for occasional FIB/SEM users, the procedure for picking up the lamella and depositing it on the target substrate should be as easy and intuitive as possible. In this work, we introduce the combination of the LiftOut Shuttle and iLO, a mouse-based control software for drag&drop sample manipulation. Using this toolset, a milled TEM sample can be retrieved and mounted to an appropriate receptacle with ease - within a few minutes!

ABSTRACT. In Charged Coupled Devices (CCDs), radiation-induced events generate electron hole pairs in silicon that cause artifacts and contribute to degrade image quality. In this work, the impact of natural radiation at ground level has been characterized at sea level, in altitude and underground for a commercial full-frame CCD device. Results have been carefully analyzed in terms of event shape, size and hourly rates. The respective contributions of atmospheric radiation and telluric contamination from ultra-traces of alpha-particle emitters have been successfully separated and quantified. Experimental results have been compared with simulation results obtained from a dedicated radiation transport and interaction code.

ABSTRACT. It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1][2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.

ABSTRACT. In standard power cycling devices are always in on-state and heated solely by conduction losses. Contrary the devices in application are heated also by switching losses, which rise with temperature increase. Degradation of interconnects causing higher temperature swings might be thereby accelerated stronger than in standard tests. This paper discusses test bench topologies implemented to overcome this gap. 

ABSTRACT. This work is motivated by the growing importance of lifetime modelling in power electronics. Strongly accelerated High Temperature Reverse Bias (HTRB) testing of power diodes at different stress conditions is
performed until alterations and fatigue mechanisms become evident. Two categories of effects can be separated: Drifting breakdown voltage and hard failures with complete loss of blocking capability. Nevertheless the overall stress duration needed to provoke destructive failures is very high with test durations >2500h even at almost 230°C and 100% rated voltage. For both mechanisms the temperature and voltage acceleration is evaluated. Especially temperature acceleration is significant in the regime of testing between 200°C and 230°C and an activation energy Ea in the regime >1eV can be deduced which is higher compared to values commonly reported in the literature. Failure analysis shows that both package and also chip related effects could contribute to the observed hard failures in HTRB stress under extreme conditions.

ABSTRACT. High measurement accuracy is the basis for a precise determination of the junction temperature Tj. Temperature measurement can be performed by means of temperature sensitive parameters (TSP) as shown in [1] using the VCE(T)-method, however, internal semiconductor processes like the removal of stored charge in bipolar devices have to be respected. The aim of this work is to determine the earliest time point of accurate measurement tMD after switching off, as well as dependencies on device voltage classes and applied battery voltage. Measurement results are confirmed by performing the simulation with Sentaurus TCAD. Dependencies of delay tMD on temperature, applied measurement current and battery voltage are demonstrated for IGBT and silicon diode.

ABSTRACT. Semiconductor devices and packages have firmly moved in to an era where scaling is driven by 3D architectures. However, most of the metrology and inspection technologies in use today were developed for 2D devices and are inadequate to deal with 3D structures. An additional complication is the need for specific structural and defect information that may be buried deep within a 3D structure. We present concepts and technologies that allow for 3D imaging as well as tomography, enabling engineers to view structural information with unprecedented clarity, detail and speed. The discussed methods include FIB and X-Ray Microscopy and show the abilities of these technologies for the analysis of electronic devices.

ABSTRACT. Advanced TEM sample preparation is required for the failure analysis and process control of bleeding edge technology nodes. Ultra-thin lamella with minimal amorphous damage can be made using the Phoenix ion column of the Helios G4 dualbeam microscope, permitting projection free imaging of even the smallest features.  Front-end defects are increasingly difficult to locate for root cause analysis in the TEM, especially for 3D transistor structures. A sample preparation method is described in which a planar view sample of the region of interest is initially made and observed in STEM to more accurately locate the failing region. Subsequently a cross sectional lamella is prepared from the plan-view. In the Helios G4, all of these steps can be performed without taking the sample out of the chamber or physical handling, thus leading to a faster and more robust workflow.