Increasingly design teams are asking for an automated code generation from Electronics System-Level (ESL) design environments to hardware description in Register-Transfer-Level (RTL). Automated RTL generation can be implemented as a direct ESL-to-RTL synthesis or by using High-Level Synthesis (HLS) tools. Most HLS tools use C++ or SystemC as a modeling language, which is closer to the higher-level languages used in ESL environments than VHDL or Verilog. Model translation process is still needed, but the effort of manual translation is reasonable, and the translation process can be automated to some extent. Using C++ or SystemC as an intermediate language in the process provides unexpected benefits to the overall design flow. This paper introduces a generic MATLAB to RTL design flow that can be used with most common HLS tools, and it is target technology agnostic.