Data layouts can significantly impact application performance. However, choosing the best-performing layout for a given application, especially one using complex data structures, remains a challenge: how the data-layout performance depends on factors such as the data access pattern and machine parameters is not sufficiently understood.

In this paper, we present a2D design space exploration (DSE)approach to systematically study the performance impact of data layouts. Starting from a given array of (complex) data structures and a set of representative C++ kernels that read the array, our approach (1) generates all possible data layouts for the input array via structure splitting and data member reordering, (2) generates and executes the kernels with each layout, and (3) collects performance data. Through exhaustive testing, we empirically quantify the impact of different layouts and observe patterns that can help develop data layout selection guidelines.

To demonstrate our approach, we apply it to a set of kernels representing common high-energy physics computations and a particle structure with 7 data members. We generate and measure over 37500 versions of each kernel for 4 different architectures (2 Intel and 2 AMD CPUS), and collect over 6 million data points. Our results indicate that data layouts do have a significant impact on runtime performance when the input is sufficiently large. We identify several causes for the large performance gaps (up to 67%) between layouts and, based on these observations, suggest empirical guidelines for (semi-)automated data layout refactoring.