Field Programmable Gate Arrays, FPGAs, are in- creasing used in space as data processors for sensors. For low power spacecraft, payloads and small satellites, the reconfigura- tion capability of FPGAs increases the versatility of hardware processor without greatly increasing the power consumption. Using partial reconfiguration, the implemented logic design is changed on the hardware level by altering the connections between resources. A dynamically reconfigurable coprocessor allows this versatility to be implemented in small satellites were power constraints limit the onboard processing capability. The coprocessor functions as a hardware accelerator for data intensive processing or functionality unsupported by the main processor. This approach was developed and tested by swapping be- tween one-dimensional and two-dimensional first difference edge detection coprocessors. A single coprocessor was implemented in parallel to a 32-bit integer aerospace processor, RadPC RISC-V 32I. Dynamic partial reconfiguration is used to swap the coprocessor between the different edge detection algorithm versions in real-time. . The coprocessor was evaluated for use in small satellites based on three main criteria, real-time operation, FPGA resource utilization, and power consumption. The dynamic partial recon- figuration time and operation runtime were measured to confirm that real-time operation for the overall system was possible. FPGA resources were measured via the AMD Vivado design tool after implementation. Power consumption was estimated by the AMD Vivado Power Analysis Tool and confirmed via lab power supply measurements. The results of this study provide evidence that the use of dynamically reconfigurable coprocessors has the ability to increase the computational capability of small satellite computers while fitting within the constrained resources of such missions.