Converged computing architectures like AMD's MI300A Accelerated Processing Unit (APU) and Nvidia's Grace Hopper Superchip (GH200) are now featured in world's most powerful supercomputers. On these architectures, both CPU and GPU are on the same chip. However, fundamental design choices separate MI300A and GH200: the first comes with a single physically unified memory for the CPU and GPU cores, while the other has two separate memories, but with the ability for compute units to fetch information from both, through NVLink-C2C.

Heterogeneous compute applications (i.e. with latency and/or throughput sensitive tasks) are expected to get the most out of these new chips, without the CPU-GPU communication bottleneck of PCIe-based architectures. In this paper, we study how the different design choices in GH200 and MI300A can impact the performance of a balanced latency-and-throughput-sensitive simulation software. We also evaluate how converged architectures can reduce memory transfer costs. Finally, we suggest options to get the most out of these architectures based on our performance measurements.

Our findings show that, depending on the balance of latency-bound and throughput-bound tasks in simulation software, some converged architectures will be more suited than others for executing these codes, with differences in speed of up to 2.78x in our case.