Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) due to their high speed and low leakage. However, unique defects in FeFETs, such as Threshold Voltage Shifting (TVS), challenge conventional testing methods. To address this, the Device-aware Test (DAT) approach models defective devices by integrating defect impacts into electrical parameters, calibrated with measurement data. Fault analysis using defect injection and circuit-level simulation identifies realistic fault models. Tailored March tests and Design-for-Test (DfT) solutions are then proposed to detect these defects effectively, advancing FeFET testing methodologies.