Talk Keyword Index

TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

Shortcuts: 1 2 5 8 A B C D E F G H I J L M N O P R S T U V W Σ

1
16nm	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications
2
2.5D IC	Heterogeneous Interconnection of ICs Using Stitch-Chips
2×VDD	A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response
5
5G	CMOS Power Amplifiers for 5G Technology
8
8-bit-serial	Pushing the Limits Further: Sub-Atomic AES
A
Accelerometers	Σ-Δ Based Force-Feedback Capacitive Micro-machined Sensors: Extending the Input Signal Range
acoustic side channel	Process-Aware Side Channel Monitoring for Embedded Control System Security
AES	Pushing the Limits Further: Sub-Atomic AES
Analog front end	A sub-µW Bio-potential Front End in 65nm CMOS
Analog front-ends	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
Antenna	Characterization of RF energy harvesting at 2.4 GHz
Approximate computing	Synthesis of Multi-variate Stochastic Computing Circuits
area minimization	Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
Artificial Neural Networks	Intelligent Embedded and Real-Time ANN-based Motor Control for Multi-Rotor Unmanned Aircraft Systems
ASIC	Pushing the Limits Further: Sub-Atomic AES
Assertion Based Verification	Multiple Reset Domains Verification Using Assertion Based Verification
ATPG	On the In-field Testing of Spare Modules in Automotive Microprocessors
Authentication Protocol	Restoration protocol: Lightweight and secure devices authentication based on PUF
Automotive testing	On the In-field Testing of Spare Modules in Automotive Microprocessors
B
behavioral model	Non-Regression Approach for the Behavioral Model Generator in Mixed-Signal System Verification
better than worst case sigma corner	Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines
Bias Inverter Quantizer (BIQ)	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
bio-potential amplifier	A sub-µW Bio-potential Front End in 65nm CMOS
block cypher	Pushing the Limits Further: Sub-Atomic AES
body bias control	Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI
C
Caches	Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets
calibration	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
CDR	Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector
CDR Less communication	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
chopper stabilized amplifier	A sub-µW Bio-potential Front End in 65nm CMOS
Classification algorithm	A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics
CML : Current Mode Logic	Enabling Efficient System Design Using Vertical Nanowire Transistor Current Mode Logic
CMOS	A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices
Communication techniques	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
computation-in-memory	Embedded Tutorial
Congestion Management	Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique
control systems	Process-Aware Side Channel Monitoring for Embedded Control System Security
covert channel	DFS Covert Channels on Multi-Core Platforms
current auto-zeroing	A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
current density	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
Cut opitmization	Redundant Via Insertion in SADP Process with Cut Merging and Opitmization
D
Data flow graph	Template based synthesis for high performance computing
DC-DC convertors	Single charge-pump generating high positive and negative voltages driving common load
defect-aware synthesis	Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
dependability	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
Design for manufacturing	Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review
Design topology	Improving post-silicon error detection with topological selection of trace signals
Doherty	CMOS Power Amplifiers for 5G Technology
DTM	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
DVFS	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
dynamic comparator	A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
dynamic frequency scaling	DFS Covert Channels on Multi-Core Platforms
dynamic offset cancellation	A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
E
EEPROM	Single charge-pump generating high positive and negative voltages driving common load
electromigration	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
Embedded instruments	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
embedded vision	Extending OpenVX for Model-based Design of Embedded Vision Applications
emerging computing paradigms	Embedded Tutorial
emerging technology	Embedded Tutorial
Energy efficient	Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors
Energy Harvesting	Characterization of RF energy harvesting at 2.4 GHz
Engineering Change Order (ECO)	A New Approach For Constructing Logic Functions After ECO
Error detection	Improving post-silicon error detection with topological selection of trace signals
Error Resilient Applications	Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS
error tolerance	Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines
F
fast transient response	A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response
FD-SOI	Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI
Fellow Sets	Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets
FEM	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
FinFET	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications Analyzing the Behavior of FinFET SRAMs with Resistive Defects
finite element analysis	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
flash ADC	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
Flash Memory	Single charge-pump generating high positive and negative voltages driving common load
Flit Flow Analysis	Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique
Flooding	Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique
force feedback	Σ-Δ Based Force-Feedback Capacitive Micro-machined Sensors: Extending the Input Signal Range
FPGA	Template based synthesis for high performance computing A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics
frequency scaling	Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects
Functional test	On the In-field Testing of Spare Modules in Automotive Microprocessors
G
Gait Dynamics	A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics
GPU	Extending OpenVX for Model-based Design of Embedded Vision Applications
H
Half-Rate	Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector
Hardware security	Restoration protocol: Lightweight and secure devices authentication based on PUF
Heterogeneous embedded systems	Extending OpenVX for Model-based Design of Embedded Vision Applications
Heterogeneous integration	Heterogeneous Interconnection of ICs Using Stitch-Chips
Heterogeneous Multicore Processors	Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors
High performance computing	Template based synthesis for high performance computing
high speed communication	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
High-level synthesis	Template based synthesis for high performance computing
HIST	Heterogeneous Interconnection of ICs Using Stitch-Chips
Hotspot Traffic	Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique
HPC	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
I
IC piracy
ICL	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
IJTAG IEEE 1687	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
ILP	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
In-field testing	On the In-field Testing of Spare Modules in Automotive Microprocessors
information leakage	DFS Covert Channels on Multi-Core Platforms
input offset storage	A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
Intelligent Systems	Intelligent Embedded and Real-Time ANN-based Motor Control for Multi-Rotor Unmanned Aircraft Systems
Inter-Set Wear Leveling	Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets
interconnect	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
Internet of Things (IOT)	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications
IoT
J
Jitter	Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector
L
layout	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
Layout decomposition	Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review
LDO	A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response
level-shifter-less	Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI
library pruning	Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines
Lifetime enhancement	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
lightweight	Pushing the Limits Further: Sub-Atomic AES
Linear	Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector
Logic locking
Logic Restructuring	A New Approach For Constructing Logic Functions After ECO
logic synthesis	Power-aware and Cost-efficient State Encoding in Non-volatile memory based FPGAs
low power	Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI
low power communication	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
low power consumption	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
Low Voltage	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications
low-overhead	Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects
Low-power	Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS
low-power design	Power-aware and Cost-efficient State Encoding in Non-volatile memory based FPGAs
low-voltage	A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response
lower area	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
M
many-core	Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects
Mask optimization	Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review
memristive devices	Embedded Tutorial
MEMS capacitive	Σ-Δ Based Force-Feedback Capacitive Micro-machined Sensors: Extending the Input Signal Range
mixed-signal circuit	Non-Regression Approach for the Behavioral Model Generator in Mixed-Signal System Verification
mm-wave	CMOS Power Amplifiers for 5G Technology
model generator	Non-Regression Approach for the Behavioral Model Generator in Mixed-Signal System Verification
MPI	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
Multi-Level Logic Synthesis	A New Approach For Constructing Logic Functions After ECO
Multi-rotor unmanned aircraft systems	Intelligent Embedded and Real-Time ANN-based Motor Control for Multi-Rotor Unmanned Aircraft Systems
multi-VDD design	Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI
Multicore Systems	Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique
Multiple patterning lithography	Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review
N
Near real-time	Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors
negative charge pump	Single charge-pump generating high positive and negative voltages driving common load
network-on-chip	Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects
Neuro-Degenerative	A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics
Non-Volatile Memory	Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets
NVM-based FPGA	Power-aware and Cost-efficient State Encoding in Non-volatile memory based FPGAs
O
offset voltage & delay monitors	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
optimisation	Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects
optimization	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
P
Packaging	Heterogeneous Interconnection of ICs Using Stitch-Chips
parallel processing	A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation
PD	Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector
PDL	Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems
physical design	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
positive charge pump	Single charge-pump generating high positive and negative voltages driving common load
Post-silicon validation	Improving post-silicon error detection with topological selection of trace signals
Power Amplifiers	CMOS Power Amplifiers for 5G Technology
Power delivery	Heterogeneous Interconnection of ICs Using Stitch-Chips
Power on Reset (POR)	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications
Process Compatibility	Enabling Efficient System Design Using Vertical Nanowire Transistor Current Mode Logic
process variation	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
programmable resolution	A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC
Prototype	A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics
PSRR	A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices
PUF	Restoration protocol: Lightweight and secure devices authentication based on PUF
Pulsed-Data	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
Pulsed-Index	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
R
Razor	Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS
reconfigurable single-electron transistor array	Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
Redundant via insertion	Redundant Via Insertion in SADP Process with Cut Merging and Opitmization
reliability	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
Reset Domain Crossings	Multiple Reset Domains Verification Using Assertion Based Verification
Reset Verification	Multiple Reset Domains Verification Using Assertion Based Verification
Resistive Defects	Analyzing the Behavior of FinFET SRAMs with Resistive Defects
Restoration ratio	Improving post-silicon error detection with topological selection of trace signals
RF	Characterization of RF energy harvesting at 2.4 GHz
runtime	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
S
SADP	Redundant Via Insertion in SADP Process with Cut Merging and Opitmization
SAT	A New Approach For Constructing Logic Functions After ECO
SBST	On the In-field Testing of Spare Modules in Automotive Microprocessors
Self Timed	Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications
Side channel emissions	Process-Aware Side Channel Monitoring for Embedded Control System Security
single channel communication	A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications
single-electron transistor	Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
slack balancing	Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines
SPICE	Analyzing the Behavior of FinFET SRAMs with Resistive Defects
SRAM	Analyzing the Behavior of FinFET SRAMs with Resistive Defects
state encoding	Power-aware and Cost-efficient State Encoding in Non-volatile memory based FPGAs
Stochastic computing	Synthesis of Multi-variate Stochastic Computing Circuits
STT-RAM	Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets
synthesis	Synthesis of Multi-variate Stochastic Computing Circuits Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays
system security	DFS Covert Channels on Multi-Core Platforms
T
Task scheduling	Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors
Template	Template based synthesis for high performance computing
thermal capping	Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes
thermal side channel	Process-Aware Side Channel Monitoring for Embedded Control System Security
Trace signal selection	Improving post-silicon error detection with topological selection of trace signals
U
ultra-low power	A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices
V
verification	Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design
VnanoCML Design	Enabling Efficient System Design Using Vertical Nanowire Transistor Current Mode Logic
VNFET : Vertical-Nanowire-FET	Enabling Efficient System Design Using Vertical Nanowire Transistor Current Mode Logic
voltage multipliers	Single charge-pump generating high positive and negative voltages driving common load
Voltage Over-scaling	Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS
voltage reference	A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices
W
WiFi	Characterization of RF energy harvesting at 2.4 GHz
Σ
Σ-Δ based capacitive sensors	Σ-Δ Based Force-Feedback Capacitive Micro-machined Sensors: Extending the Input Signal Range