VLSI-SOC 2017: 25TH IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION
TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

1
16nm
2
2.5D IC
2×VDD
5
5G
8
8-bit-serial
A
Accelerometers
acoustic side channel
AES
Analog front end
Analog front-ends
Antenna
Approximate computing
area minimization
Artificial Neural Networks
ASIC
Assertion Based Verification
ATPG
Authentication Protocol
Automotive testing
B
behavioral model
better than worst case sigma corner
Bias Inverter Quantizer (BIQ)
bio-potential amplifier
block cypher
body bias control
C
Caches
calibration
CDR
CDR Less communication
chopper stabilized amplifier
Classification algorithm
CML : Current Mode Logic
CMOS
Communication techniques
computation-in-memory
Congestion Management
control systems
covert channel
current auto-zeroing
current density
Cut opitmization
D
Data flow graph
DC-DC convertors
defect-aware synthesis
dependability
Design for manufacturing
Design topology
Doherty
DTM
DVFS
dynamic comparator
dynamic frequency scaling
dynamic offset cancellation
E
EEPROM
electromigration
Embedded instruments
embedded vision
emerging computing paradigms
emerging technology
Energy efficient
Energy Harvesting
Engineering Change Order (ECO)
Error detection
Error Resilient Applications
error tolerance
F
fast transient response
FD-SOI
Fellow Sets
FEM
FinFET
finite element analysis
flash ADC
Flash Memory
Flit Flow Analysis
Flooding
force feedback
FPGA
frequency scaling
Functional test
G
Gait Dynamics
GPU
H
Half-Rate
Hardware security
Heterogeneous embedded systems
Heterogeneous integration
Heterogeneous Multicore Processors
High performance computing
high speed communication
High-level synthesis
HIST
Hotspot Traffic
HPC
I
IC piracy
ICL
IJTAG IEEE 1687
ILP
In-field testing
information leakage
input offset storage
Intelligent Systems
Inter-Set Wear Leveling
interconnect
Internet of Things (IOT)
IoT
J
Jitter
L
layout
Layout decomposition
LDO
level-shifter-less
library pruning
Lifetime enhancement
lightweight
Linear
Logic locking
Logic Restructuring
logic synthesis
low power
low power communication
low power consumption
Low Voltage
low-overhead
Low-power
low-power design
low-voltage
lower area
M
many-core
Mask optimization
memristive devices
MEMS capacitive
mixed-signal circuit
mm-wave
model generator
MPI
Multi-Level Logic Synthesis
Multi-rotor unmanned aircraft systems
multi-VDD design
Multicore Systems
Multiple patterning lithography
N
Near real-time
negative charge pump
network-on-chip
Neuro-Degenerative
Non-Volatile Memory
NVM-based FPGA
O
offset voltage & delay monitors
optimisation
optimization
P
Packaging
parallel processing
PD
PDL
physical design
positive charge pump
Post-silicon validation
Power Amplifiers
Power delivery
Power on Reset (POR)
Process Compatibility
process variation
programmable resolution
Prototype
PSRR
PUF
Pulsed-Data
Pulsed-Index
R
Razor
reconfigurable single-electron transistor array
Redundant via insertion
reliability
Reset Domain Crossings
Reset Verification
Resistive Defects
Restoration ratio
RF
runtime
S
SADP
SAT
SBST
Self Timed
Side channel emissions
single channel communication
single-electron transistor
slack balancing
SPICE
SRAM
state encoding
Stochastic computing
STT-RAM
synthesis
system security
T
Task scheduling
Template
thermal capping
thermal side channel
Trace signal selection
U
ultra-low power
V
verification
VnanoCML Design
VNFET : Vertical-Nanowire-FET
voltage multipliers
Voltage Over-scaling
voltage reference
W
WiFi
Σ
Σ-Δ based capacitive sensors