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08:00-09:00 Session : Registration
Location: Registration Desk
09:00-10:00 Session 8: Morning Keynote
Location: Al Manaar Ballroom
Leon Stok (IBM, USA)
From IoT to SoC
SPEAKER: Leon Stok

ABSTRACT. Analysts project that by 2025, data from connected devices will yield actionable information that will drive potential economic value of as much as 11 trillion US$ [1]. Sixty percent of existing enterprises are slated to adopt machine-to-machine IoT solutions over the next two years [2]. IoT software platforms to enable, connect, secure, manage, and analyze such IoT solutions will be essential. This keynote will spell out what all of this means to the SoCs that will be the fabric of our IoT eco-systems.

References: [1] Unlocking the potential of the Internet of Things. McKinsey & Company, June 2015 [2] [The Forrester WaveTM: IoT Software Platforms, Q4 2016.

10:00-15:00 Session 9A: PhD Forum
Leila Fayez Ismail (United Arab Emirates University, UAE)
Location: Al Manaar Lobby
Xuchen Zhang (Georgia Institute of Technology, USA)
Yang Zhang (Georgia Institute of Technology, USA)
Paul Jo (Georgia Institute of Technology, USA)
Md Obaidul Hossen (Georgia Institute of Technology, USA)
Gary May (Georgia Institute of Technology, USA)
Muhannad Bakir (Georgia Institute of Technology, USA)
Heterogeneous Interconnection of ICs Using Stitch-Chips

ABSTRACT. In this paper, a heterogeneous interconnect stitching technology (HIST) is presented. Stitch chips with high-density fine pitch wires are used to connect active dice of various functions in a manner that mimics system-on-chip (SoC) like performance. Microbumps and compressible microinterconnects (CMIs) are used to provide die-to-die and die-to-package interconnection. A testbed containing two dummy dice and one stitch chip is fabricated and tested. The average measured post-assembly resistance of the microbumps and the CMIs is 116.5 µΩ and 195.9 mΩ, respectively. Using an electrical model for HIST signal channels, a 50%-50% delay as small as 140 ps with an energy efficiency of 0.24 pJ/bit may be achieved for a 1mm channel. In addition, some power delivery challenges and opportunities of HIST are highlighted through simulations. The results show that compared to interposer based 2.5-D integration, HIST may reduce the IR-drop by approximately 18.4%.

Nourhan Elsayed (Khalifa University, UAE)
Hani Saleh (Khalifa University, UAE)
Baker Mohammad (Khalifa University, UAE)
CMOS Power Amplifiers for 5G Technology

ABSTRACT. Currently, there is a large move towards 5G wireless technology beyond the existing, widely used 4G technology due to an increased use of smart devices, and multimedia content. 5G technology is expected to operate at high frequencies between 15 GHz and 100 Ghz opening up a new horizon for spectrum constrained future wireless communications. Designing high efficiency power amplifiers for such high frequencies presents a new challenge. This paper presents different designs of integrated PAs operating at 15-100 GHz for 5G applications.

Hadeel Aboueidah (Khalifa University of Science, Technology and Research, UAE)
Nasma Abbas (Khalifa University of Science, Technology and Research, UAE)
Nadeen El Nachar (Khalifa University of Science, Technology and Research, UAE)
Aya Alyousef (Khalifa University of Science, Technology and Research, UAE)
Mohammad Al-Hawari (Khalifa University of Science, Technology and Research, UAE)
Baker Mohammad (Khalifa University of Science, Technology and Research, UAE)
Hani Saleh (Khalifa University of Science, Technology and Research, UAE)
Characterization of RF energy harvesting at 2.4 GHz

ABSTRACT. Abstract— This paper presents a comprehensive study on RF energy harvesting at a frequency of 2.4 GHz using P21XXCSR-EVB evaluation board. The study is carried out by considering several types of antennas, varying distances from the transmitting source at different input and output power. The maximum distance at which the harvesting kit can regulate the output voltage of 3.4V is 65 cm using a 10 dBi Omni directional antenna. Further, the harvesting kit can produce an output power of 4 mW using a 5-dBi-dipole antenna at 10 cm away from the source with a maximum efficiency of 55%. The demonstration of energy harvesting is presented by powering an LED dimming circuit. This study could be helpful for researchers to design circuits and systems in RF energy harvesting area.

Shimna Shafeek (University of Bolton - RAK Campus, UAE)
Jikui Luo (University of Bolton, UK)
Theoretical Numerical Investigation Simulation and Optimization of Triboelectric Generators

ABSTRACT.  The recent development of internet of things (IoT) and sensor networks dramatically increases the demands for robust energy harvesting techniques for sensors to work as self- powered. Scavenging mechanical energy from ambient environment through friction and vibration has attracted great attention. Among electromagnetic, electrostatic, piezoelectric and triboelectric mechanical energy harvesting technologies, triboelectric nanogenerators (TENGs) based on coupling of contact electrification and electrostatic induction, shows a promising technology owing to their numerous advantages: high output power, high energy conversion efficiency and low cost materials and fabrication. This PhD work focuses on the numerical and computational study on various modes of TENG using MATLAB and Comsol Multiphysics.The output characteristics of the TENG are evaluated with respect to various geometrical parameters of the model, and measurement conditions. The effect of material selection, geometry as well as the angle between the dielectrics will also be investigated in the selected TENG model.

Felipe Rocha Da Rosa (Universidade Federal do Rio Grande do Sul, Brazil)
Luciano Ost (University of Leicester, UK)
Ricardo Reis (Universidade Federal do Rio Grande do Sul, Brazil)
Early Evaluation of Multicore Systems Soft Error Reliability Using Virtual Platforms

ABSTRACT. The combination of continually shrinking technology and ever-increasing on-chip power density and temperature operation calls for novel reliability-oriented techniques which can provide reliable system operation while meeting performance and energy constraints. This work reports techniques and tools, which have been developed during the first three Ph.D. years.

Somayeh Sadeghi-Kohan (University of Tehran, Iran)
Zainalabedin Navabi (University of Tehran, Iran)
Cross Layer Handling of Timing Variations Effects in a Digital System

ABSTRACT.  There are physical phenomena such as variability, defects, aging and crosstalk that affect the timing behavior and functionality of a digital system. To mitigate the effects of these phenomena and increase the life time of a system, we should consider them at different parts of the system. In this dissertation, we add some utilities to the system in order to detect, monitor and predict the effects of dynamic variations. These utilities provide provisions and information that some mechanisms are employed them for reducing and handling problems of delay degradations due to dynamic variations.

Sukarn Agarwal (Indian Institute of Technology Guwahati, Assam, India)
Controlling Writes for Energy Efficient Non-Volatile Cache Management in Chip Multiprocessors

ABSTRACT.  With the advent of Chip Multiprocessors (CMPs), the demands of large sized Last Level Cache (LLC) is continuously increasing. Conventional caches fabricated from SRAM fall short in fulfilling these demands. Recently, the emergence of non-volatile memory technologies has shifted the attention of researchers to fabricate the cache using other technologies. These Non-Volatile Memory (NVM) technologies such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (ReRAM) and Spin Transfer Torque Random Access Memory (STT-RAM) offer many benefits over the traditional SRAM memory technology. The benefits include high density, good scalability low static power consumption and the high immunity to soft errors. Previous researches have shown that by employing these NVMs in a different level of cache hierarchy (such as L2 or L3), one can significantly reduce the static/leakage power consumption in the cache. However, the cache made from these memory technologies suffers from costly write operations and low write endurance.

George W. Archbold Taylor (Pontificia Universidad Javeriana, Colombia)
Soil pH and Macronutrient Agricultural Soil Sensing System Based on ISFET Sensor and Compensation Techniques

ABSTRACT. Many agricultural researchers have devoted themselves to the study of ISFET electrochemical sensors as a useful tool in the field of precision agriculture. These works have been dedicated to the detection of multiple ions (pH, N and K) using On-The-Go platforms that allow the construction of nutrient concentration maps of soils. However, there is a need to improve the stability of the electronic sensor-interface system so that large volumes of reliable information can be obtained for the agricultural sector with this platforms. 

On the other hand, in the last decades, electronic researchers have proposed techniques to mitigate the problems that are presented in ISFET sensors, however, most of the time their approaches are based on pH measurement. In addition to this, there is still little research in which the main focus is the design of electronic compensation circuits for measuring macronutrients, contrary to the biomedicine field where already developed sensor arrays ISFET with the main focus on the integration of millions of these sensors for the autonomous and massive ions detection.

Mahesh Kumar Adimulam (EE Department, Birla Institute of Technology and Science – Pilani, Hyderabad Campus, India)
An Ultra Low Power, Low Noise Programmable Analog Front End (PAFE) for Biopotential Signal Processing Applications

ABSTRACT.  In this presentation, an ultra low power, programmable Analog Front End (PAFE) for biopotential signal processing applications (such as electrocardiography (ECG), electromyography (EMG) and electroencephalography (EEG)) is presented. The PAFE mainly consists of programmable gain capacitive coupled instrumentation amplifier (PG-CCIA), programmable low pass filter (PLPF) and a low power 12-bit 3- stage successive approximation register (SAR) analog-to-digital converter (ADC). The PG-CCIA circuit is implemented with chopping technique for reducing offset voltage and a new operational transconductance amplifier (OTA) is introduced with improved transconductance. The proposed OTA design improves the performance parameters such as common mode rejection ratio (CMRR), power supply rejection ratio (PSRR), input referred noise and offset voltage. The 12-bit programmable 3-stage SAR ADC is implemented in this design, the main advantages of this architecture at higher resolutions are higher static/dynamic performance due to improved feedback DAC performance, area and power reduction by using three 4-bit capacitive DACs instead of single 12-bit capacitive DAC in the feedback path. The power consumption of proposed ADC is reduced due to multiple stages, by OTA/Comparator sharing technique between the stages and operating digital blocks on 0.3 V supply voltage. The performance parameters of the proposed PAFE design are found to be input referred noise voltage of 0.82 μVrms over 0.5 Hz-1 KHz range, gain of 25-70 dB, signal-to-noise-and-distortion ratio (SNDR) of 69.24 dB and power consumption of 0.68μW @ 0.5 V supply voltage.

10:00-15:00 Session 9B: University Booths/IoT Demos
Mohammad Al-Hawari (Khalifa University of Science, Technology and Research, UAE)
Location: Al Manaar Lobby
10:05-10:20 Session : PhD Forum Presentations
Leila Fayez Ismail (United Arab Emirates University, UAE)
Location: Al Manaar Ballroom A
10:30-12:00 Session 10A: Low-power and thermal-aware IC design
Nicola Bombieri (University of Verona, Italy)
Location: Al Manaar Ballroom A
Daniele Cesarini (University of Bologna, Italy)
Andrea Bartolini (ETH Zurich, Switzerland)
Luca Benini (ETH Zurich, Switzerland)
Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes

ABSTRACT. We are entering the era of thermally-bound computing: Advanced and costly cooling solutions are needed to sustain the high computing densities of high-performance computing equipment. To reduce cooling costs and cooling overprovisioning, dynamic thermal management (DTM) strategies aim at controling the device temperature by modulating online the performance of processing elements. While operating systems allow the migration of threads between cores, in HPC systems the threads of parallel applications are pinned to the allocated cores at start-time to avoid job-migration overheads. In this scenario state-of-the-art DTM solutions which use thermal models to map jobs to cores are based on long-term predictions to map the most critical job to the coldest core. Instead, turbo-mode and DVFS controllers are based on short-term predictions to squeeze the thermal capacitance allowing for short period performance boosts which are thermally unsustainable. In this work we propose an integer-linear programming formulation and a fast solver for controlling at the same time the job mapping and cores frequency selections in HPC nodes, tested with real supercomputer workload. Our approach can be integrated with the run-time MPI and OpenMP libraries and is capable of assigning high-performance cores to performance-critical threads. We show that by combining long and short term predictions with information of the programming model we can significantly improve the performance of final application w.r.t. state-of-the-art DTM solutions.

Andrea Calimera (Politecnico di Torino, Italy)
Roberto Giorgio Rizzo (Politecnico di Torino, Italy)
Valentino Peluso (Politecnico di Torino, Italy)
Jun Zhou (Institute of Microelectronics (IME), A*STAR, Singapore)
Xin Liu (Institute of Microelectronics (IME), A*STAR, Singapore)
Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS

ABSTRACT. Razor is a milestone in the field of Error Detection&Correction strategies for low-power operation. Despite the impressive level of maturity, its application on circuits other than pipelined processors still remains an open issue. Firstly, the error detection mechanism relies on special flip-flops (FFs), the Razor-FFs, whose use imposes heavy hold-time fixing and large circuit area/power overheads; secondly, the error correction is performed through instruction replay, a practice that is not available (or very expensive to implement) in generic circuits. This work introduces Early Bird Sampling (EBS), a Razor variant that applies to low-power sequential circuits. The EBS allows to (i) solve the problem of short-path races bypassing tedious hold-time fixing design stages, (ii) reduce design overhead exploiting a local logic-masking mechanism for error correction. As a key feature, EBS enables Data-Driven Voltage Over-Scaling (DDVOS), an aggressive dynamic voltage scaling strategy particularly suited for ultra-low power error-resilient applications. Simulation runs on a representative set of circuits provide a fair comparison with a standard Razor strategy. The collected results show EBS reduces area overheads (3.6% against 71.6% for Razor) and improves the voltage scaling profile achieving lower energy-per-operation (savings w.r.t. Razor range from 19.1% to 53.1%).

Kimiyoshi Usami (Shibaura Institute of Technology, Japan)
Shunsuke Kogure (Shibaura Institute of Technology, Japan)
Yusuke Yoshida (Shibaura Institute of Technology, Japan)
Ryo Magasaki (Shibaura Institute of Technology, Japan)
Hideharu Amano (Keio University, Japan)
Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI

ABSTRACT. Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

10:30-12:00 Session 10B: Analog, mixed-signal and sensor architectures I
Baker Mohammad (Khalifa University of Science, Technology and Research, UAE)
Location: Al Manaar Ballroom B
Vivek Nautiyal (ARM Inc, USA)
Lalit Gupta (ARM Inc, USA)
Sagar Dwivedi (ARM Inc, USA)
Gaurav Singla (ARM Inc, USA)
Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications

ABSTRACT. A Power on Reset (POR) circuit operates when the supply is ramping up, then resets latches, and flip-flops in an SOC to a known state. The power up supply is not stable, and the ramp-up time can vary depending on the applications. A robust approach to generate a POR signal is to compare the supply with a reference voltage. Battery frugal applications like Internet of Things operate at very low supply voltage. At such low voltages, generating a reference voltage is difficult. This paper presents a circuit that operates without using any reference voltage, making it robust against different sources of variation. The proposed circuit is self-timed, which means that the reset signal pulse-width varies according to the time needed to reset the latch. The circuit does not consume any dynamic power during normal operation of the SOC and has minimal area overhead of 21.3-µm2. The designed circuit has been fabricated in 16nm FINFET technology. Based on silicon validation, the proposed POR circuit works at a minimum supply voltage of 400mv

Shuangxing Zhao (Southern University of Science and Technolgy, China)
Chenchang Zhan (Southern University of Science and Technolgy, China)
Guigang Cai (Southern University of Science and Technolgy, China)
A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response

ABSTRACT. This paper presents a 2×VDD-enabled fully-integrated CMOS low-dropout (LDO) regulator with fast transient response for cost-effective SoC power management applications with elevated-VDD supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high-voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate 1×VDD voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-um CMOS process which achieves 3.3~3.6V nominal input, 3.1V nominal output and 100mA loading capability with all the transistors being 1.8V MOSFETs.

Vikas Rana (STMicroelectronics Pvt Ltd, India)
Marco Pasotti (STMicroelectronics Pvt Ltd, Italy)
Fabio Desantis (STMicroelectronics Pvt Ltd, Italy)
Single charge-pump generating high positive and negative voltages driving common load
SPEAKER: Vikas Rana

ABSTRACT. A new architecture of charge-pump circuit is discussed which can be used to generate high positive and negative voltages to drive a common load (Load can be capacitive, resistive or both). Basic voltage multiplier cell used for charge-pump composed of two phase clock signals, charge transfer NMOS transistors and bootstrapped configuration to boost the gate drive of NMOS transistors. Due to use of NMOS transistors, output resistance of circuit is lower than conventional circuits thus able to drive high load current. Electrical conditions of all devices used in the circuit are managed in such a way that there is no electrical stress across any device. This circuit can be very useful for high voltage applications (like E2PROM, Flash Memory etc.) to reduce on-chip area. Circuit is designed and implemented in BCD-110nm technology.

13:00-14:30 Session 11A: Special Session I: Physical Design and Mask Synthesis for Advanced Lithography Technology
Youngsoo Song (Samsung, South Korea)
Location: Al Manaar Ballroom A
Shao-Yung Fang (National Taiwan University, Taiwan)
Design Optimization for Directed Self-Assembly

ABSTRACT. The directed self-assembly (DSA) technology has shown its great potential in via/contact layer fabrication for sub 10-nm technology nodes. To guarantee sufficient overlay accuracy of generated vias, only a few guiding templates with simple shapes are feasible, and thus manufacturable via patterns are limited. In addition, redundant via insertion has become a necessary step in the circuit design flow to improve reliability and yield. In this presentation, post-layout optimization techniques and some design methodologies to simultaneously maximize redundant via insertion rates and via manufacturability in DSA will be introduced.

Yuzhe Ma (The Chinese University of Hong Kong, Hong Kong)
Xuan Zeng (Fudan University, China)
Bei Yu (The Chinese University of Hong Kong, Hong Kong)
Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review

ABSTRACT. As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

Youngsoo Song (Korea Advanced Institute of Science and Technology, South Korea)
Jinwook Jung (Korea Advanced Institute of Science and Technology, South Korea)
Youngsoo Shin (Korea Advanced Institute of Science and Technology, South Korea)
Redundant Via Insertion in SADP Process with Cut Merging and Opitmization
SPEAKER: Youngsoo Song

ABSTRACT. Line-end cuts in self-aligned double patterning (SADP) process are employed for printing 1D-gridded patterns. Redundant via (RV) requires another cut, named RV cut, to be introduced, which may cause coloring conflicts or design rule violations with adjacent line-end cuts. RV insertion should be coordinated together with cut optimization so that maximum number of RVs are inserted while incurring no coloring conflicts among cuts. A technique named cut merging is addressed to remove cut conflicts and thereby increase the number of RV candidates. Cut redistribution and color assignment (for both line-end and RV cuts) are also taken into account to further increase RV candidates.

13:00-14:30 Session 11B: Embedded Tutorial: Memristive devices for computing: Beyond CMOS and Beyond von Neumann
Muhannad Bakir (Georgia Institute of Technology, USA)
Location: Al Manaar Ballroom B
Said Hamdioui (Delft University of Technology, Netherlands)
Dietmar Fey (Friedrich-Alexander-University (FAU), Germany)
Embedded Tutorial
SPEAKER: Said Hamdioui

ABSTRACT. Today’s computing systems are still based on von Neumann (VN) architectures and still rely on many parallel (mini) cores with a shared SRAM cache. It is well recognised that such solutions suffer from major limitations such as a decreased performance acceleration per core, increased power consumption, and limited system scalability. These limitations are mainly caused by the processor-memory bottleneck. As the current data-intensive and big data applications require huge data transfers back and forth between processors and memories through load/store instructions, the maximal performance cannot be extracted as the processors will have many idle moments while waiting for data. Moreover, today’s computers are manufactured using the traditional CMOS technology, which is reaching the inherent physical limits due to transistor down-scaling and are suffering from multiple challenges, such as high static power consumption, reduced performance gain, reduced reliability, complex manufacturing process leading to low yield and complex testing process, and extremely costly masks. Many novel nano-devices and materials are under investigation to be combined with- or to replace- the CMOS in next IC generations. Among the emerging devices, such as graphene transistors, nanotube, tunnel field-effect transistor (TFET), etc., memristor is a promising candidate. Its advantages are CMOS process compatibility, lower cost, zero standby power, nanosecond switching speed, great scalability and high density, and non-volatile nature. It offers a high OFF/ON resistance ratio and it is promising to have a good endurance and retention time. More importantly, the memristor has a wide potential application including non-volatile memory applications, digital computing, neuromorphic computing, etc.

This Session will discuss the use of memristor devices as enabler to set up major step toward a new generation of (radically) new architectures that address the major shortcomings of today’s conventional architectures and technologies; namely, latency, energy, area efficiency, scalability, parallelism, etc.