Vladimir Voevodin

• Deputy Director, Research Computing Center, Lomonosov Moscow State University
• Head of the Department on Supercomputers and Quantum Informatics, Computational Mathematics and Cybernetics Faculty, MSU

The computing world is changing rapidly. All devices – from mobile phones and personal computers to high-performance supercomputers – are becoming parallel. The huge capacity of modern supercomputers allows complex problems, previously thought impossible, to be solved. Performance of the best supercomputers in the world is measured in Petaflops providing unprecedentedly powerful instruments for research. At the same time, the efficient usage of all opportunities offered by modern computing systems represents a global challenge and requires new knowledge, skills and abilities, where one of the main roles belongs to understanding of key properties of parallel algorithms. The talk will address the urgent need for theoretical and practical technologies of an accurate and concerted design of high performance computing systems, highly parallel algorithms, and extreme scaled applications to be able to solve large problems using the current and prospective generations of high performance computing systems. The most essential concept behind these technologies is co-design which is a very close partnership or interrelationship between all the layers involved in the process of solving these problems on high performance computing systems: mathematical methods, algorithms, applications, programming technologies, runtime systems, layers of system software and hardware. The notion of co-design is so important for HPC that the following thesis is definitely true: “No efficient co-design technologies, no reasonable exascale in the future”.

Vladimir Voevodin is Deputy Director of the Research Computing Center at Lomonosov Moscow State University. He is Head of the Department “Supercomputers and Quantum Informatics” at the Computational Mathematics and Cybernetics Faculty of MSU, professor, corresponding member of Russian academy of sciences.

Vl. Voevodin specializes in parallel computing, supercomputing, extreme computing, program tuning and optimization, fine structure of algorithms and programs, parallel programming technologies, scalability and efficiency of supercomputers and applications, supercomputing co-design technologies, software tools for parallel computers, and supercomputing education. His research, experience and knowledge became a basis for the supercomputing center of Moscow State University, which was founded in 1999 and is currently the largest supercomputing center in Russia. He has contributed to the design and implementation of the following tools, software packages, systems and online resources: V- Ray, X-Com, AGORA, Parallel.ru, hpc-education.ru, hpc-russia.ru, LINEAL, Sigma, Top50, OctoShell, Octotron, AlgoWiki. He has published 90 scientific papers with 4 books among them. Vl.Voevodin is one of the founders of Supercomputing Consortium of Russian Universities established in 2008, which currently comprises more than 60 members. He is a leader of the major national activities on Supercomputing Education in Russia and General Chair of the two largest Russian supercomputing conferences.

Pedro José Marrón

• Full Professor for Pervasive Computing at the University of Duisburg-Essen and Co-Founder of Locoslab GmbH

The world is changing at an extremely rapid pace and it seems impossible even for computer scientists to keep up with the evolution of technologies. Fifteen years ago, smart phones were just a dream and people were reluctant to go online for many things. Nowadays, everything seems to be moving to the virtual realm and as of today, 3 billion people have regular access to the Internet and to communication technologies. This number is equal to the world population in 1967. In this talk, we will look back at some of the predictions of future computing done by “experts” in the last years and will analyze the state of Ubiquitous Computing technologies using examples from current research projects not with virtual entities, but with real people in real cities.

Prof. Dr. Pedro José MARRÓN received his bachelor and master’s degree in computer engineering from the University of Michigan in Ann Arbor in 1996 and 1998. At the end of 1999, he moved to the University of Freiburg in Germany to work on his Ph.D., which he received with honors in 2001. From 2003 until 2007, he worked at the University of Stuttgart as a senior researcher, leading the mobile data management and sensor network group. In 2007, he left Stuttgart to become a Professor of Computer Science at the University of Bonn, where he led the sensor networks and pervasive computing group. In 2009 he left Bonn to become a full Professor at the University of Duisburg-Essen. He is currently head of the “Networked Embedded Systems Group” (NES) which counts with almost 20 researchers working on fields related to ubiquitous computing. He is also co-founder of Locoslab GmbH, a spin-off of the University of Duisburg-Essen specialized in providing complete solutions for location-based services. Additionally, Pedro Marrón is also the initiator and president of UBICITEC, the European Center for Ubiquitous Technologies and Smart Cities, which counts with over 20 institutional partners from industry and academia forming a virtual European Center with clear research and dissemination objectives. The goal of UBICITEC is to coordinate the research efforts on enabling technologies for Smart Cities, e.g. Internet of Things and to encourage the transfer of technology to industry.

Rafael Asenjo

• Associate Professor at the Dept. of Computer Architecture, Univ. Malaga

Heterogeneous computing is seen as a path forward to deliver the energy and performance improvements needed over the next decade. That way, heterogeneous systems feature GPUs (Graphics Processing Units) or FPGAs (Field Programmable Gate Arrays) that excel at accelerating complex tasks while consuming less energy. There are also heterogeneous architectures on-chip, like the processors developed for mobile devices (laptops, tablets and smartphones) comprised of multiple cores and a GPU. More recently, some architectures have also paired multicores along with an FPGA in the same die. Examples of the latest are Xilinx Zync (2 cores Cortex-A9 + FPGA), Xilinx UltraScale+ MPSoC (4 cores Cortex-A53 + GPU Mali 400 + FPGA) or Intel HARP (12 cores Xeon + FPGA).

This talk covers hardware and software aspects of this kind of heterogeneous architectures. Regarding the HW, we briefly discuss the underlying architecture of some heterogeneous chips composed of multicores+GPU and multicores+FPGA, delving into the differences between both kind of accelerators and how to measure the energy they consume. We also address the different solutions to get a coherent view of the memory shared between the cores and the GPU or between the cores and the FPGA. With respect to the SW, different heterogeneous programming models will be introduced, paying more attention to those that are aimed at exploiting several devices at the same time (CPU + GPU or CPU + FPGA). Again, the different optimization techniques and the levels of parallelism that are suitable for the GPU and for the FPGA will be identified. Finally, we present our own proposal that tackles heterogenous execution of applications based on the pipeline and parallel_for patterns. We discuss our extensions to the Threading Building Blocks, TBB, pipeline and parallel_for templates to automatically distribute the workload between the multicore and the accelerator, taking care of the load balancing and considering energy consumption in the scheduling policies. We evaluate the performance and energy efficiency of the different approaches for several heterogenous processors: Intel Ivy Bridge, Intel Haswell, Samsung Exynos 5 Octa, Xilinx Zync and Intel Broadwell + Altera Stratix V FPGA.

Rafael Asenjo received his B.S. and M.S. degrees in Telecommunications Engineering in 1993 and his Ph.D. degree in 1997, both from the University of Malaga, Spain. He has been an Associate Professor at the Dept. of Computer Architecture, Univ. Malaga, Spain, since 2001, where he leads a research group working on “productivity” in the context of high performance computing.  He collaborated on the IBM XL-UPC compiler in 2008 and has contributed to the Cray’s Chapel runtime development since 2011. This year he served as General Chair of ACM PPoPP’16 and has also served as Program Committee member for IPDPS’13, IPDPS’14 and SC’15. His research interests include  programming models, parallelization of irregular codes, parallel IO, parallelizing compilers and heterogeneous architectures.

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