FMCAD 2019: FORMAL METHODS IN COMPUTER-AIDED DESIGN 2019

A
Akshay, S.	Knowledge Compilation for Boolean Functional Synthesis
Aldous, Peter	Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order
Arora, Jatin	Knowledge Compilation for Boolean Functional Synthesis
B
Bachrach, Jonathan	GuidedSampler: Coverage-guided Sampling of SMT Solutions
Barbosa, Haniel	Extending enumerative function synthesis via SMT-driven classification
Barthe, Gilles	Verifying Relational Properties using Trace Logic
Baumgartner, Jason	Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties Input Elimination Transformations for Scalable Verification and Trace Reconstruction
Berryhill, Ryan	Chasing Minimal Inductive Validity Cores in Hardware Model Checking
Biere, Armin	Verifying Large Multipliers by Combining SAT and Computer Algebra
Bloem, Roderick	Synthesizing Reactive Systems Using a Robustness Specification
C
Carloni, Luca	KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
Cassimiro Teixeira Dos Santos, Aellison	TSNsched: Automated Schedule Generation for Time Sensitive Networking
Chakraborty, Supratik	Knowledge Compilation for Boolean Functional Synthesis
Chockler, Hana	Synthesizing Reactive Systems Using a Robustness Specification
D
Deshmukh, Jyotirmoy	Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems
Di Guglielmo, Giuseppe	KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
Dureja, Rohit	Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties
Dutra, Rafael	GuidedSampler: Coverage-guided Sampling of SMT Solutions
E
Ebnenasir, Ali	Verification and Synthesis of Symmetric Uni-Rings for Leads-To Properties
Ebrahimi, Masoud	Synthesizing Reactive Systems Using a Robustness Specification
Eilers, Renate	Verifying Relational Properties using Trace Logic
F
Fedyukovich, Grigory	Property Directed Inference of Relational Invariants
Finkbeiner, Bernd	Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications
Frohn, Florian	Proving Non-Termination via Loop Acceleration
G
Gajavelly, Raj Kumar	Input Elimination Transformations for Scalable Verification and Trace Reconstruction
Ganichev, Igor	BDD-Based Algorithms for Packet Classification
Ge-Ernst, Aile	Localizing Quantifiers for DQBF
Geier, Gideon	Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications
Georgiou, Pamina	Verifying Relational Properties using Trace Logic
Ghosh, Shiladitya	Input Elimination Transformations for Scalable Verification and Trace Reconstruction
Giesl, Jürgen	Proving Non-Termination via Loop Acceleration
Gleiss, Bernhard	Verifying Relational Properties using Trace Logic
Goswami, Pronnoy	Scalable Translation Validation of Unverified Legacy OS Code
Gupta, Indranil	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
Gurfinkel, Arie	Unification-based Pointer Analysis without Oversharing
H
Heim, Philippe	Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications
I
Ivrii, Alexander	Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties Input Elimination Transformations for Scalable Verification and Trace Reconstruction
J
Joshi, Sarang	Scalable Translation Validation of Unverified Legacy OS Code
K
Kalim, Faria	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
Kanzelman, Robert	Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties Input Elimination Transformations for Scalable Verification and Trace Reconstruction
Kauers, Manuel	Verifying Large Multipliers by Combining SAT and Computer Algebra
Kaufmann, Daniela	Verifying Large Multipliers by Combining SAT and Computer Algebra
Klein, Felix	Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications
Kovacs, Laura	Verifying Relational Properties using Trace Logic
Kuderski, Jakub	Unification-based Pointer Analysis without Oversharing
Kullmann, Oliver	Autarkies for DQCNF
L
Larraz, Daniel	Extending enumerative function synthesis via SMT-driven classification
M
Madhusudan, P.	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
Maffei, Matteo	Verifying Relational Properties using Trace Logic
Markgraf, Oliver	Learning-Based Synthesis of Safety Controllers
Mehar, Jayasi	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
Mercer, Eric	Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order
Mordvinov, Dmitry	Property Directed Inference of Relational Invariants
Muduli, Sujit Kumar	Verification of Authenticated Firmware Loaders
Murali, Adithya	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
N
Nadel, Alexander	Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization
Narodytska, Nina	BDD-Based Algorithms for Packet Classification
Navas, Jorge A.	Unification-based Pointer Analysis without Oversharing
Neider, Daniel	Learning-Based Synthesis of Safety Controllers
Nigam, Vivek	TSNsched: Automated Schedule Generation for Time Sensitive Networking
O
Ogles, Benjamin	Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order
P
Palmskog, Karl	Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity
Piccolboni, Luca	KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
R
Raghunathan, Divya	Knowledge Compilation for Boolean Functional Synthesis
Ravindran, Binoy	Scalable Translation Validation of Unverified Legacy OS Code
Ray, Sayak	Verification of Authenticated Firmware Loaders
Reynolds, Andrew	Extending enumerative function synthesis via SMT-driven classification
Rozier, Kristin Yvonne	Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties
Ryzhyk, Leonid	BDD-Based Algorithms for Packet Classification
S
S, Krishna	Knowledge Compilation for Boolean Functional Synthesis
Schneider, Ben	TSNsched: Automated Schedule Generation for Time Sensitive Networking
Scholl, Christoph	Localizing Quantifiers for DQBF
Sen, Koushik	GuidedSampler: Coverage-guided Sampling of SMT Solutions
Sevinc, Soner	BDD-Based Algorithms for Packet Classification
Shah, Shetal	Knowledge Compilation for Boolean Functional Synthesis
Shukla, Ankit	Autarkies for DQCNF
Strichman, Ofer	Synthesizing Reactive Systems Using a Robustness Specification
Subramanyan, Pramod	Verification of Authenticated Firmware Loaders
T
Tahat, Amer	Scalable Translation Validation of Unverified Legacy OS Code
Tinelli, Cesare	Extending enumerative function synthesis via SMT-driven classification
V
van de Pol, Jaco	Concurrent Chaining Hash Map for Software Model Checking
van der Berg, Freark I.	Concurrent Chaining Hash Map for Software Model Checking
Veneris, Andreas	Chasing Minimal Inductive Validity Cores in Hardware Model Checking
W
Wang, Chao	Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems
Wang, Jingbo	Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems
Wimmer, Ralf	Localizing Quantifiers for DQBF
Wu, Meng	Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems

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