FLOC 2018: FEDERATED LOGIC CONFERENCE 2018
PROGRAM
AUTHORS
KEYWORDS
SLIDES
FLoC
|
FoPSS
|
ITP
|
CSF
|
FSCD
|
SAT
|
CAV
|
IJCAR
|
ICLP
|
FM
|
LICS
|
ADHS
|
ADSL
|
ARQNL
|
ASPOCP
|
AVOCS
|
CL&C
|
COALG
|
Coq
|
DCM
|
Domains13
|
DS-FM
|
EICNCL
|
F-IDE
|
FCS
|
FRIDA
|
GraMSec
|
GS
|
HCVS
|
HDRA
|
HOR
|
HoTT/UF
|
ICLP-DC
|
IFIP WG 1.6
|
Isabelle
|
ITRS
|
IWC
|
LaSh
|
LCC
|
LearnAut
|
LFMTP
|
Linearity/TLLA
|
LMW
|
LOLA
|
LPOP
|
LSB
|
MLP
|
MoRe
|
MSFP
|
NLCS
|
NSV
|
Overture
|
PAAR
|
PARIS
|
PC
|
PLR
|
POS
|
PRUV
|
QBF
|
RCRA
|
REFINE
|
ReMOTE
|
rv4rise
|
SCSC
|
SMT
|
SoMLMFM
|
SR
|
SYNT
|
TERMGRAPH
|
Tetrapod
|
ThEdu
|
TLA
|
TYDI
|
UITP
|
UNIF
|
Vampire
|
VaVAS
|
VDMW
|
VEMDP
|
VSTTE
|
WiL
|
WPTE
|
WST
Revantha Ramanayake
Organization:
Vienna University of Technology
Web page:
https://www.logic.at/staffpages/revantha
Pages in this Program
EICNCL on Thursday, July 19th
EICNCL Program
Program
Program for Saturday, July 7th
Program for Thursday, July 19th
Slides
Slides
TYDI on Saturday, July 7th
TYDI Program
Disclaimer
|
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