EURO-PAR 2026 WORKSHOPS: 32ND INTERNATIONAL EUROPEAN CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING WORKSHOPS
PROGRAM FOR TUESDAY, AUGUST 25TH
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09:00-10:30 Session 5A: Workshop HeteroPar 1
Location: Room B
09:00
Welcome Message from the HeteroPar 2026 Chair
09:05
Accelerated computing for the masses: programming a (NVIDIA) GPU today is nothing like 10 years ago!

ABSTRACT. There was a time when GPUs were considered exotic and programming them was considered difficult. Fast forward a decade, advance in programming models helped democratize Accelerated Computing. The concept of “accelerator” itself has evolved, it is not longer just a PCIe card attached to a server. It is now often tightly coupled with a host CPU and the architecture spawns from one node to full rack-scale solutions.

In this talk, I present programming model approaches to improve the developer productivity by helping them exploiting the performance potential of modern tightly-coupled NVIDIA CPU+GPU systems. I will also highlight trends in modern and novel programming models approaches (e.g cuTILE) and languages within the NVIDIA CUDA ecosystem to support more efficient and agile use of latest hardware capabilities. To conclude, a glimpse of the role of AI and agentic tools in support of code development and optimization.

09:00-10:30 Session 5B: Workshop HiPES 1
Location: Room C
09:00
Welcome Message from the HiPES 2026 Chair
09:15
A Malleable Ad-hoc In-memory File System for HPC Ephemeral Data

ABSTRACT. As data-heavy applications continue to become more popular, High-Performance Computing (HPC) storage systems are under immense strain in terms of both capacity and speed. Although modern innovations like NVMe and persistent memory provide substantial performance enhancements, equipping entire systems exclusively with high-speed storage is impractical in terms of cost, making multi-tier storage architectures essential. Compounding this challenge, modern workloads across HPC, data analytics, and artificial intelligence exhibit increasingly heterogeneous and dynamic I/O access patterns. While traditional storage was designed for predictable, batch-oriented tasks, today’s applications generate bursty, mixed traffic that strains the rigidity of existing storage hierarchies. Consequently, there is a need to shift toward adaptive, malleable designs that bridge the gap between evolving application behaviors and underlying infrastructures. To address these demands, ad-hoc file systems have emerged as a practical solution by pooling local compute-node resources, such as RAM and local persistent storage, to create highly adaptable, temporary file systems that are customized to the specific behavior of HPC workloads.

This talk explores the malleability capabilities of HERCULES, a distributed ad-hoc in-memory storage system, detailing its malleability model design. The system incorporates runtime malleability and fault-tolerance mechanisms, enabling dynamic data migration through flexible allocation policies to maximize resource utilization. Comprehensive evaluation results show that HERCULES outperforms Lustre and BeeGFS, two widely used parallel file systems in high-performance computing environments

10:00
Völ: A domain-specific language and runtime for AI-native workflows

ABSTRACT. Workflows using Generative-AI tasks are error-prone and hard to audit when model calls, validation, retries, and outputs are scattered; they must connect visibly so the pipeline can be audited and reviewed.

This paper presents Völ, a domain-specific language for expressing AI-native tasks, including scientific workflows. Völ separates deterministic control flow from probabilistic model calls and places validation, retry logic, and failure handling next to the task that uses them, so the policy for each model step is visible where it runs. It expresses model calls, structured-output contracts, automatic repair, retry policy, and workflow control in one program rather than across prompts, helper scripts, libraries, and glue code, so end-to-end behavior can be read and reviewed in one place.

We use the recognition of chemical entity in scientific articles from NLM-Chem to evaluate Völ and compare it with a Python, LangGraph, Snakemake, and Nextflow implementations. The Völ program is more compact and achieves the lowest mean end-to-end runtime, including about 1.8× and 2.1× speedups over Python and LangGraph. On a six-node SLURM cluster, Nextflow with embedded Völ runs about 1.5× faster than Nextflow with embedded Python and keeps per-job AI logic more compact than embedding Python in Nextflow or Snakemake.

09:00-10:30 Session 5C: Workshop EuroQHPC 1
Location: Room A1
09:00
Welcome Message from the EuroQHPC 2026 Chairs
09:30
QDMI in Practice: Connecting Quantum Backends, Cloud Services, and HPC Workflows

ABSTRACT. Integrating quantum computers into HPC environments is increasingly less about gaining access to a QPU and more about making that access usable across hardware providers, cloud services, schedulers, and user-facing software.

This talk shares practical perspectives on how the Quantum Device Management Interface (QDMI) can help standardize this hardware–software boundary. Using two recent case studies, I will discuss QDMI integrations with IQM superconducting systems in Slurm- and Qiskit-oriented HPC workflows, as well as its use for unified access to heterogeneous cloud backends through Amazon Braket.

The examples show how a shared interface can simplify integration work that is otherwise repeated for each provider and deployment setting. I will reflect on what has worked in practice, where the remaining challenges lie, and how QDMI can help HPC centers and quantum-software developers build more reusable paths from experimental systems to operational workflows.

09:00-10:30 Session 5D: Workshop FRAME 1
Location: Room C1
09:00
Welcome Message from the FRAME 2026 Chairs
10:00
Smart Adaptive Computing Across the Continuum: LLMs in IoT-Edge-Cloud Resource Management

ABSTRACT. Managing resources across IoT, edge, and cloud layers calls for continuous, context-aware decisions under constraints that rarely stay fixed. Deep reinforcement learning (DRL) handles this class of problems well, and large language models (LLMs) are increasingly used to aug- ment DRL pipelines, yet the architectural relationship between the two is seldom made explicit. We build on the taxonomy of Wang et al. [16] of Continuum Orchestration Systems employing DRL techniques and ex- tend it with a third dimension, the AI Augmentation Paradigm, which measures how LLMs are exploited, from absent in a pure DRL baseline, to fully orchestrating a layer of autonomous agents. A further metric we identify is whether execution feedback returns to the LLM and through which system path, in order to close the MAPE control loop at the LLM Orchestration layer. We apply this taxonomy to six recent system architectures and find a common gap, as none combines full LLM or- chestration with full agent-layer feedback in a Cloud Continuum setting. We relate this gap to a missing cross-tier feedback abstraction, bridging the incommensurable per-tier signals and the LLM Orchestrator. As we set out to explore how to engineer LLM Orchestration, we identify as key axes in the resulting design space the LLM cardinality and the agent specialisation, and we devise a roadmap toward LLM Orchestration in the Continuum via federated, domain-specialized agents.

09:00-10:30 Session 5E: Minisymposium PEPSC 1
Location: Room B1
09:00
Welcome Message from the PEPSC 2026 Chairs
09:10
Semi-implicit PIC codes on current and next-generation supercomputers: lessons learned and future directions

ABSTRACT. Semi-implicit particle-in-cell (PIC) codes are essential tools for investigating the kinetic
dynamics of multiscale plasmas, particularly for understanding how microscopic
processes influence the macroscopic evolution of plasmas permeating the heliosphere.
The massively parallel, multidimensional codes ECsim (Gonzalez et al. 2018) and
iPIC3D (Markidis et al. 2010) are prominent examples of this class of applications.
Developed in the early 2000s, when the high-performance computing landscape was
comparatively homogeneous, these legacy scientific codes now face the challenge of
adapting to increasingly heterogeneous architectures. Current and next-generation
supercomputers combine diverse CPU architectures and accelerators to meet the
demands of exascale computing, requiring new approaches to performance portability,
scalability, and resilience.
In this talk, we will discuss our experience in addressing these challenges. First, we will
present the strategy adopted in ECsim to exploit modern GPUs while avoiding intrusive
changes to the existing codebase. Our approach preserves code readability and
maintainability while delivering substantial performance improvements and excellent
scalability (Boella et al. 2026). We will then discuss our experience benchmarking
iPIC3D on RISC-V CPUs, analysing the observed performance in relation to key
architectural characteristics and comparing the results with those obtained on more
established x86_64 and ARM-based architectures (Almerol et al. 2026). Finally, we will
describe our efforts to improve the resilience of iPIC3D to MPI failures through the
integration of the Legio framework, which represents a shift from traditional checkpoint-
and-restart fault tolerance toward a graceful degradation resilience model (Rocco et al.
2025).
Together, these experiences provide practical lessons on how established scientific
applications can evolve to exploit emerging hardware while preserving portability,
maintainability, and scientific productivity.
Almerol, J.L., et al. (2026), Is RISC-V Ready for Massively Parallel Astrophysical Codes?,
arXiv pre-print, arXiv:2606.15490.
Boella, E., et al. (2026), Accelerating the Particle-In-Cell Code ECsim with
OpenACC, 2026 34th Euromicro International Conference on Parallel, Distributed, and
Network-Based Processing (PDP), Cluj-Napoca, Romania, 224.
Gonzalez-Herrero D., et al. (2018), Performance analysis and implementation details of
the Energy Conserving Semi-Implicit Method code (ECsim), Computer Physics
Communications 229, 162.
Markidis, S., et al. (2010), Multi-scale simulations of plasma with ipic3d, Mathematics
and Computers in Simulation 80, 1509.
Rocco R., et al. (2025), To repair or not to repair: Assessing fault resilience in MPI stencil
applications, Journal of Parallel and Distributed Computing 205, 105156

09:50
Recent Developments & Updates of The BIT1 PIC MC Code

ABSTRACT. We introduce the BIT1 PIC MC code for plasma edge simulations and describe recent updates enabling simulation speed-up by order(s) of magnitude. In particular, we describe BIT1 GPU porting examples, new Poisson solver, uniform task load, as well as attempts to accelerate simulation through particle merging. Finally, we give an example of a plasma study performed with BIT1 code – a recent discovery of so-called collisional sheath, a thin plasma layer, which will influence plasma exhaust in next generation fusion devices.

10:30-11:00Coffee Break
11:00-13:00 Session 6A: Workshop HeteroPar 2
Location: Room B
11:00
Execution-Guided LLM Translation of Parallel Programs: A CUDA-to-SYCL Study
PRESENTER: Ruben Laso

ABSTRACT. Parallel-application translation requires more than syntactic code conversion: translated programs must compile, execute on the intended accelerator, preserve results, and retain useful runtime behavior. This paper presents ParTrans, an execution-guided, iterative LLM translation pipeline for parallel programs. ParTrans combines static repository analysis, source and target execution in a real HPC environment, and feedback-driven re-translation after build errors, run errors, or output mismatches. We study the current state of practice for such LLMbased translation by applying the approach to CUDA-to-SYCL migration. CUDA is mature and highly optimized for NVIDIA GPUs, while SYCL offers a portable C++-based programming model for CPUs, GPUs, and other accelerators. We evaluate correctness, runtime behavior, and monetary cost on 30 CUDA programs from HeCBench. The results show that the strongest models can translate the complete benchmark set within few feedback iterations, while smaller and cheaper models solve fewer samples or require more correction steps. For functionally correct translations, median runtimes are often close to the original CUDA baseline, but slow outliers remain and must be measured separately. Compilation success alone is therefore insufficient for judging translation quality.

11:30
PortLBM: A Portable Lattice Boltzmann Tool Leveraging SYCL on AMD, NVIDIA, and Intel GPUs
PRESENTER: Alexander Strack

ABSTRACT. The lattice Boltzmann method (LBM) is a well-established approach for simulating fluid flows at the mesoscopic scale. With the stagnation of Moore's law, high-performance computing has shifted toward GPU accelerators, necessitating programming models that ensure both portability and efficiency across diverse hardware platforms.

We present PortLBM, an extensible portable LBM framework built on SYCL that integrates cross-platform GPU support with interactive real-time visualization. PortLBM supports diverse simulation scenarios ranging from Kármán vortex streets and wing flows to porous media, and is designed for easy extension with new algorithms and backends. As part of a performance portability study, we evaluate PortLBM on contemporary GPU architectures from NVIDIA, AMD, and Intel, examining the impact of three memory layouts (stream, bundle, and collision) and four algorithmic variants on simulation throughput.

Our results show that no single configuration achieves optimal performance across all GPU vendors, confirming the need for system-specific tuning. The stream layout maximizes bandwidth and performs best on contemporary NVIDIA and Intel GPUs, while the bundle layout improves cache efficiency and excels on AMD GPUs. Two-lattice schemes achieve higher throughput while one-lattice schemes are preferable under memory constraints. Our work underscores the necessity for adaptable, portable LBM software in increasingly heterogeneous computing environments.

12:00
C++ Parallel STL on GPUs: A Performance Evaluation of CUDA and SYCL Backends

ABSTRACT. With the introduction of parallel algorithms in the Standard Template Library (STL) in C++17, there is now a standardized way to write parallel and performance-portable programs in C++. In this work, we study the performance of parallel STL algorithms on GPUs using the micro-benchmark suite pSTL-Bench. We analyze the performance of memory management strategies, compilers, and backends, CUDA and SYCL. In our experiments, we find that the performance of ISO C++ parallel algorithms on GPUs is mainly affected by the choice of the memory management strategy. On NVIDIA GPUs, Unified Memory (UM) achieves the best performance, sycl::buffer is the second best option, and SYCL’s shared Unified Shared Memory (USM) is the slowest. Across compilers, NVHPC and DPC++ generally offer higher performance and better stability than AdaptiveCpp.

12:30
Microbenchmarking modern AMD GPUs
PRESENTER: Juan Ferrand

ABSTRACT. The share of AMD GPUs in HPC infrastructure and their use in research increased enormously in recent years. These GPU provide comparable performance to those of NVIDIA at attractive prices, and the late development of AMD ecosystem of tools (ROCm) enables an easy transition from CUDA applications. However, the public documentation of AMD's GPU architectures is still considerably less complete than NVIDIA's. In this work, we develop microbenchmarks in HIP to evaluate aspects of thread scheduling and memory access, revealing some architectural characteristics and comparing recent AMD HPC and consumer GPUs.

11:00-13:00 Session 6B: Workshop HiPES 2
Location: Room C
11:00
BiJuTy: An Interactive HPC-Aware Big Data Cluster Lifecycle Manager and Performance Assessment Utility for JupyterHub

ABSTRACT. The increasing demand for data processing has created a pressing need for access to high-performance computing (HPC) systems. Nevertheless, leveraging these systems to execute complex big data processing workflows remains a significant challenge, especially for beginners, despite the growing requirement for such capabilities. This work presents BiJuTy, a solution designed to bridge the accessibility gap for big data workflows on HPC systems within the Jupyter ecosystem. By providing an interactive and user-friendly interface, BiJuTy simplifies cluster lifecycle management and performance assessment, making it more accessible on HPC systems to beginners and experienced users alike. The solution is presented as an interactive interface that guides the user through the entire process, from setting up the cluster configuration to carrying out initial performance assessments. Additionally, the framework enables seamless management of multiple clusters directly within the Jupyter Notebook interface, eliminating the need to switch outside of working environment. The collection of performance metrics from various sources further simplifies the optimization workflow. Furthermore, a illustrative example is provided to demonstrate how BiJuTy can be deployed to optimize the performance of a big data processing application. This example showcases how the entire big data processing lifecycle can be iteratively executed and optimized in just a few clicks, helping to reach the goal optimization easily and interactively. By facilitating such interactive and accessible workflows, this work contributes in bringing the field of big data computing and high-performance computing one step closer to the goal of seamless interaction and usability.

11:30
Resilient Metadata Orchestration: Enhancing Availability in Cross-Institutional Scientific Collaborations

ABSTRACT. Modern scientific collaborations (such as those in large-scale eScience projects) depend on continuous metadata resolution to access distributed datasets across autonomous institutions. Existing federation-based platforms remain vulnerable to outages of organizational metadata authorities, which can block data access even when storage is reachable. To address this limitation, we investigate decentralized mechanisms for distributing metadata authority in cross-institutional environments. We present two architectures: a peer-set-based design that replicates metadata across cooperating organizations to provide low-latency, stable scalability, and a permissioned-blockchain-based design that offers strong consistency and auditability through a globally replicated ledger. Using prototype implementations, deployed on HPC-center Kubernetes infrastructure we experimentally evaluate their latency, throughput, and scaling behavior under workloads representative of large-scale eScience deployments. The results show that the peer-set approach scales effectively to large, geographically distributed collaborations, while the blockchain-based approach remains practical primarily for smaller deployments prioritizing global consistency over performance. These findings clarify the design trade-offs in resilient metadata orchestration and provide guidance for building fault-tolerant data sharing infrastructures.

12:00
Unifying von-Neumann HPC and Neuromorphic Acceleration via the EBRAINS Research Infrastructure: A Framework for High-Performance Workflows

ABSTRACT. Modern scientific workflows increasingly span diverse computing architectures, yet executing a single computational model across disparate systems often forces researchers to maintain fragmented, site-specific pipelines. In this paper, we address this challenge within the domain of computational neuroscience by presenting a unified, cloud-based workflow orchestrated via EBRAINS JupyterLab. This workflow enables users to transparently execute spiking neural networks on both von-Neumann supercomputers and neuromorphic hardware. Using a single federated identity, the system dispatches jobs to HPC sites (JUSUF, Galileo100) via PyUNICORE and to the SpiNNaker-1 neuromorphic system via the Neuromorphic Computing Platform Interface. To guarantee cross-site reproducibility and mitigate software version drift, we utilize a zero-installation execution mode that dynamically pulls PMIx-aware Apptainer containers to HPC compute nodes. Furthermore, we demonstrate genuine model-level portability using the NESTML domain-specific language, allowing custom neuron models to be written once and automatically compiled for either the NEST (C++) or sPyNNaker backends. Validated with a balanced random network case study, this work illustrates a practical, end-to-end path for hardware-agnostic workflows while highlighting the critical role of containerization and domain-specific languages in achieving true cross-platform reproducibility.

12:30
A Reproducible Deep Learning Pipeline for Embryo Localization in Time-Lapse IVF Microscopy

ABSTRACT. Automated embryo localization in time-lapse in vitro fertilization (IVF) microscopy is a prerequisite for any downstream morphokinetic analysis, yet the evaluation protocol itself can strongly bias reported performance. Because consecutive frames from the same embryo are highly correlated, random frame-level splitting leaks visual information across train and test partitions and substantially inflates detection metrics. This paper presents a complete detection pipeline built on RT-DETRv2, a real-time transformer-based detector, fine-tuned on the ELIDA dataset (16 embryos, 10,383 annotated frames) using a two-phase backbone-freeze strategy. We formalise the data leakage problem, implement an embryo-level splitting protocol, and quantify its effect empirically: frame-level splitting inflates AP@[0.50:0.95] by 0.143 points (18% relative). The proposed pipeline achieves AP@0.50 = 1.000 and AP@[0.50:0.95] = 0.779 on the held-out embryo-level test set. A systematic augmentation ablation and a training-strategy ablation confirm that geometric transforms yield the largest benefit (+0.026 AP) and that the two-phase strategy produces the best bounding-box precision (AP@0.75 = 0.970). All code, configuration files, and split definitions are designed for full reproducibility.

11:00-13:00 Session 6C: Workshop EuroQHPC 2
Location: Room A1
11:00
Mesoscopic Aware Hierarchical Layouts for Lattice Surgery Quantum Compilation

ABSTRACT. The transition to fault-tolerant quantum computation demands specialized compilation strategies to manage fault-tolerant gate execution. Lattice surgery has emerged as the de facto standard for implementing two-qubit gates; however, the relationships between circuit structures and lattice surgery optimizations remain largely unexplored. In this work, we highlight the connection between the mesoscopic community structure of quantum circuits and its impact on compilation performance. Drawing inspiration from classical chip design flows and graph-theoretic concepts, we develop a compiler that optimizes the lattice surgery schedule using a community-based hierarchical qubit layout. Experimental results demonstrate that our method achieves a substantial reduction of up to 84% in code-cycle depth compared to random-layout baselines on a set of standard quantum circuit benchmarks, while performing competitively with recent state-of-the-art lattice-surgery compilers. To further quantify the impact of circuit modularity on compilation efficiency, we generate synthetic circuits using the Stochastic Block Model, showing that our approach achieves, on average, a 32% reduction in code-cycle depth in the high-modularity regime.

11:30
From ECR to Generalized Gate Support: Extending the Qulacs Quantum Simulator

ABSTRACT. Qulacs is a high-performance quantum circuit simulator for quantum computing research. It supports state-vector and density-matrix representations and employs various optimization and parallelization techniques targeting diverse hardware architectures. Since the computational cost of quantum circuit simulation grows exponentially with the number of qubits, such optimizations are essential for large-scale computations.

This work presents the implementation of the Echoed Cross-Resonance (ECR) gate within the Qulacs framework and provides a general metho-\linebreak[4]dology that can be extended to the efficient implementation of arbitrary quantum gates. The ECR gate is an entangling two-qubit opera-\linebreak[4]tion commonly used in superconducting quantum processors, arising from the cross-resonance interaction between coupled qubits. Full integration into Qulacs requires ECR implementations for both supported representations: density-matrix and state vector. Achieving comprehensive hardware coverage, the state-vector implementation spans single-CPU (SIMD/SVE), GPU (CUDA), and distributed multi-CPU (MPI) environments, mirroring the structure followed by native gates within the framework.

12:00
Parallel QEC Decoding Applied to Distributed Quantum Computing

ABSTRACT. A novel parallel approach is proposed for QEC decoding based on Belief Propagation with Ordered Statistics Decoding. The main idea is to pre-process the error vectors obtained from Belief Propagation by applying Singular Value Decomposition locally to sub-regions of the lattice. The proposed approach is applied to distributed quantum computers and evaluated in terms of complexity, accuracy, and scalability.

12:30
Benchmarking Distributed Quantum Computing Emulators: Scalability, Fidelity, and Architectural Trade-offs

ABSTRACT. Scalable quantum computing requires architectural solutions beyond monolithic processors, and distributed quantum computing (DQC) addresses this challenge by interconnecting smaller quantum nodes through quantum communication protocols. In this work, we introduce a benchmarking framework for evaluating DQC emulators using a distributed implementation of the inverse Quantum Fourier Transform as a representative test case for efficient phase recovery from pre-encoded Fourier states. The QFT is partitioned across nodes via teleportation-based protocols, and emulator performance is assessed in terms of execution time, memory usage, and fidelity relative to a monolithic baseline. We also review a broad range of DQC emulators, identifying their capabilities and limitations for programming distributed quantum algorithms, and benchmark four representative platforms: Qiskit Aer, SquidASM, Interlin-q, and SQUANCH. These tools differ substantially in their support for discrete-event simulation, quantum networking, noise modeling, and parallel execution. Our results highlight the trade-offs between architectural fidelity and simulation scalability, providing a foundation for future emulator development, protocol validation, and extensions to additional distributed quantum algorithms.

11:00-13:00 Session 6D: Workshop FRAME 2
Location: Room C1
11:00
Structured Pruning for Efficient Transformer Inference: Edge to HPC Performance and Energy Analysis

ABSTRACT. Transformer-based language models, particularly BERT, have established foundational architectures for modern natural language processing (NLP) despite the emergence of larger models. BERT remains computationally expensive for edge and IoT deployment, making it an ideal testbed for evaluating compression techniques applicable to the broader Transformer class. This work presents a comprehensive evaluation of three structured pruning strategies (2:4 sparsity, Attention Head Pruning (HAP), and Feed-forward network (FFN) Width Pruning) applied to BERT variants (base, large, DistilBERT) at multiple sparsity levels (25%, 50%, 75%). Experiments on WikiText-2 compare Jetson AGX Orin (edge) and NVIDIA V100 (HPC) across diverse batch sizes, measuring pseudo-perplexity, latency, and energy efficiency. Key findings: FFN Width Pruning achieves highest latency reduction on edge and 1.69-1.80x energy efficiency; HAP preserves precision with minimal degradation; 2:4 pruning requires native sparse tensor core support, delivering benefits only on modern hardware (Jetson). Pruning effectiveness depends on structural redundancy: attention heads tolerate aggressive pruning (75%), while FFN neurons limit viable sparsity to 25-50%. Results demonstrate that pruning effectiveness varies significantly across platforms and sparsity levels, with important implications for selecting deployment strategies in heterogeneous edge-cloud environments. This work bridges model compression research and practical IoT deployment.

11:30
Improving the Performance of Inference Pipelines under Interference

ABSTRACT. Co-location of deep neural network inference with other workloads is common practice in both datacenter and edge deployments, but contention for shared resources can substantially degrade inference throughput. Pipeline parallelism offers an underused adaptation point: when interference makes a previously balanced pipeline imbalanced, re-partitioning the layer-to-stage assignment can restore throughput without modifying the model or the serving stack. We present ReactivePipe, a runtime system for throughput-oriented, interference-aware pipeline-parallel DNN inference. ReactivePipe monitors per-stage execution times, decouples the optimization policy from the reconfiguration mechanism, and rebuilds the assignment of model layers to processes at runtime with low overhead. We additionally contribute a pluggable optimizer that builds on the Shisha heuristic, adding tolerance bands for noise-resilient comparison and an exploration-restart mechanism that triggers only after sustained interference rather than transient noise. We implement ReactivePipe over PyTorch and evaluate it on four ImageNet-1k image classification models under controlled CPU and memory-bandwidth interference on a 32-core server. ReactivePipe retains 70.4–86.8\% of its pre-interference throughput, substantially outperforming a static GPipe partitioner and a one-shot Shisha tuner, both of which typically lose around 50\% of their throughput when interference begins.

12:00
ContinuumBench: Benchmarking Joint Autoscaling and Placement Across Evaluation Regimes in the Cloud-Edge Continuum
PRESENTER: Lanpei Li

ABSTRACT. Latency-sensitive continuum applications are often DAG-structured workflows deployed across heterogeneous IoT, edge, and cloud tiers; some also depend on intermittent contacts. Static placement alone is insufficient: controllers must also choose active worker counts and, in contact-critical settings, manage work across contact windows. We present ContinuumBench, a benchmark for joint autoscaling and placement in the cloud-edge continuum with contact-aware transport and buffering. It uses Eclypse for substrate modeling, placement feasibility, path lookup, and route costs, and adds an execution loop for arrivals, elastic workers, failures, and completion-aware summaries. The benchmark covers four DAG scenario families and supports deterministic synthetic, contact-aware, and calibrated execution regimes. Across the 10-seed F0/F2 comparison, the selected scale-capable controllers reduce SLO violations relative to matched placement-only references in all eight scenario-regime pairs and improve completion in seven of the eight. The largest gaps arise when elastic worker pools determine whether work reaches the sink or remains pending, exposing behavior that placement-only evaluation hides. These results show why continuum controller comparisons need completion-aware accounting across controlled evaluation assumptions.

11:00-13:00 Session 6E: Minisymposium PEPSC 2
Location: Room B1
11:00
On the Vectorization of BIT1 for RISC-V and x86 Architectures

ABSTRACT. Vector processors can improve performance and parallel execution for many types of applications. In this presentation we show the studies performed on BIT1, a representative PIC code, to assess the benefit from Vector/SIMD architectures using automatic and manual vectorization. We provide an extensive evaluation study on x86 and RISC-V platforms and improve BIT1 code to enable better vectorization and improve its performance. Our results show that a portable solution (with minor code updates) enhances the performance using the out-of-the-box compiler’s auto-vectorization capabilities on x86 by 78% when using 8 MPI ranks, and on RISC-V by 2× using auto or manual vectorization with 2 MPI ranks.

11:40
Simulating Matter under Extreme Conditions in the Exascale Era

ABSTRACT. We present recent advances on PIConGPU to run on Exascale machines such as JUPITER and present progress on our grand challenge, accelerating electrons to GeV energies with high power lasers using the Travelling-Wave Electron Acceleration (TWEAC) scheme.

12:20
mallocMC: Performant and Portable Many-Core Memory Allocation

ABSTRACT. This talk introduces the new FlatterScatter algorithm as part of mallocMC, a heterogeneous, configurable C++ framework for performant and portable dynamic memory allocation on highly multithreaded hardware such as GPUs. Configurability is achieved by a policy-based design enabling choice and configuration of the core algorithm and other behavior with a single line of code. Performance is achieved by shipping with state-of-the-art allocation algorithms including our new FlatterScatter algorithm improving its inspiration ScatterAlloc algorithm in terms of applicability, stability and maintainability while retaining performance.

We assess performance using a synthetic benchmark written in the CUDA language used to evaluate other allocators. It is also evaluated in the exascale particle-in-cell simulation code PIConGPU wherein mallocMC excels over its competitors. Platform independence is achieved by building on alpaka (abstraction library for parallel kernel acceleration). This enables running on NVIDIA, AMD and Intel accelerators as well as on CPU without changing a single line of code. We also evaluate performance on AMD hardware, a capability unique to the open-source library mallocMC.

13:00-14:00Lunch Break
14:00-15:30 Session 7A: Workshop HeteroPar 3
Location: Room B
14:00
Energy-Performance Analysis of CPU-GPU Workloads Under Power Capping
PRESENTER: Paweł Czarnul

ABSTRACT. The increasing computational demands of artificial intelligence (AI) and high-performance computing (HPC) workloads have led to substantial growth in energy consumption in modern heterogeneous systems. Power capping is a promising technique for improving energy efficiency, however, independent control of CPUs and GPUs often results in suboptimal system-level performance due to their tightly coupled execution. This work investigates coordinated CPU-GPU power capping for mixed HPC and AI workloads based on NPB and MLPerf benchmarks. A comprehensive exploration of power cap configurations is conducted on two heterogeneous platforms equipped with A100 and H100 GPUs. System behavior is evaluated using energy consumption, Energy-Delay Product (EDP), and Energy-Delay Gain (EDG) metrics. The results show a convex relationship between power limits and system efficiency, with optimal configurations consistently occurring at moderate GPU power caps and reduced CPU power caps. GPU power appears to be the dominant factor influencing both energy and execution time. Compared to maximum-power operation, energy savings of up to 19.76% and EDP improvements of up to 13.79% are achieved, while EDG confirms consistent system-level gains across all workloads. These findings demonstrate that coordinated power management significantly improves energy efficiency without substantial performance degradation.

14:30
RCC-Preserving Online Resource Allocation for Heterogeneous GPU Sharing with Finite Availability Windows
PRESENTER: Gennai Yuki

ABSTRACT. Cross-organizational GPU sharing has emerged as a practical approach to alleviating GPU scarcity, yet it introduces a form of heterogeneity beyond compute and memory: temporal availability governed by each provider's autonomous policy. Providers pre-declare availability windows and reclaim their resources at expiration as a normal operating condition. Existing schedulers are ill-suited to this setting: they either assume persistent availability or treat departure solely as a feasibility constraint, leaving residual availability unexploited as a scheduling signal. Finite availability thus constrains not only current feasibility but also future executable capacity, requiring scheduling that prevents mid-execution interruptions while preserving capacity for later demand. We introduce \textit{Residual Computational Capacity (RCC)}, a unified abstraction that integrates compute throughput, memory capacity, and temporal availability into node value. Building on this abstraction, we propose \textit{RCC-Preserving}, a Mixed-Integer Linear Programming (MILP)-based online resource allocation strategy that minimizes RCC consumption subject to feasibility constraints on task deadlines and resource availability. Evaluation against two MILP-based baselines demonstrates that embedding residual availability in the objective yields measurable gains in success rate and robustness to resource volatility.

15:00
Accelerating HLS-based FPGA Development in Distributed Heterogeneous Systems

ABSTRACT. FPGAs have been the prime components for applications with tight requirements regarding energy efficiency, latency, and flexibility for future updates for a long time. As systems become increasingly distributed across multiple heterogeneous devices in the edge, their main drawback, the high design complexity, becomes even more challenging. While previous approaches already presented frameworks for local FPGA execution, remote procedure calls (RPC), and cloud environments, these are not sufficient for the collaborative development of systems with lower amounts of several distinct FPGAs. These pose significant challenges regarding design space exploration (DSE), bitstream generation and management in the context of multi-user operation. Therefore, this paper presents a new streamlined method for an incremental development flow for distributed FPGAs. We achieve this with an own RPC-capable OpenCL library that transparently performs high-level synthesis, the adaptation to a specific board, and bitstream generation in the background. At the same time, partial reconfiguration of the FPGA is also deferred to a background task scheduler and based on the actual kernel dispatches such that users cannot indefinitely block concurrent others. With this approach, we successfully generated designs for five different static shells on three types of FPGA boards from the same source code. These designs achieved a speedup in application runtime by a factor of up to 5.4 compared to a local ARM Cortex A53 processor, with only a low remote execution overhead of less than 4 %.

14:00-15:30 Session 7B: Workshop HiPES 3
Location: Room C
14:00
The INTERSECT Scientific Data Layer An Ontological Framework for Data Provenance for Complex Scientific Workflows
PRESENTER: Sheikh Ghafoor

ABSTRACT. Complex scientific workflows have multiple stages, including experiments, sim- ulations, data analyses, and visualization, generating data and metadata stored across heterogeneous storage infrastructures and used in downstream stages or future experimental campaigns. This paper presents the design and implemen- tation of a comprehensive ontological framework for managing scientific data generated within such workflows, addressing the key challenges of data interop- erability, provenance capture, and adherence to Findable, Accessible, Interop- erable, and Reusable (FAIR) data principles. The Autonomous Chemistry Lab- oratory (ACL) at Oak Ridge National Laboratory (ORNL) enables automated liquid phase and solid state synthesis and related chemical analysis. Our frame- work has been deployed within the ACL for a native and machine-interpretable semantic representation of its ecosystem, including instrument capabilities, syn- thesis workflows, analytical observations, and experimental results. The proposed approach enables end-to-end provenance tracking, supports heterogeneous data formats, and establishes a foundation for Artificial Intelligence (AI)-ready scien- tific discovery. We validate the framework through concrete modeling examples.

14:30
A FAIR Cross-Backend Workflow for Latin America Energy Analytics on Commercial Hardware

ABSTRACT. FAIR scientific workflows require more than open scripts: they require a stable dataset contract, explicit hardware provenance, backend agreement checks, and generated artefacts that can trace back to measured runs. We present a workflow for Latin America energy-transition analytics that combines five practical stages: data ingest, CPU reference computation, OpenCL execution, PTX execution, and publication of hashes, CSVs, tables, and figures. The case study uses a 22 country, 13-indicator panel derived from OWID Energy (563 country-year rows, 2000--2025). The case study executes on a measured commercial workstation with an Intel Core i7-14700HX, 64 GB RAM, and an NVIDIA GeForce RTX 4070 Laptop GPU (8 GB). The workflow exposes an important reproducibility fact often hidden in eScience GPU papers: on the native panel, the CPU is faster than both GPU backends because the workload is too small; only after controlled workload scaling, do the GPU paths overtake the CPU, with PTX providing the earlier and broader crossover regime: deltas and weighted-index construction cross at 18,016 rows, normalisation at 72,064 rows, while OpenCL first crosses on deltas at 18,016 rows but only overtakes the CPU on normalisation and weighted-index construction at 288,256 rows. Agreement remains within float32 expectations for both GPU paths, and the generated artefacts explicitly record those crossover thresholds. We then transfer the same workflow contract to a second public profile based on CHIRPS v3 monthly Latin America climate rasters, processed as three 4-month chunks totaling 39.2 million pixel-month rows and four derived hydroclimate features. The result is a compact HiPES-style workflow that makes backend choice, hardware context, workload profile, and reproducibility boundaries auditable rather than implicit.

15:00
Spritz: An On-Demand Workflow for Air-Quality Impact Modeling of Wildfires and Arson

ABSTRACT. Wildfires, whose ignitions in Europe are overwhelmingly human-caused, including negligence and deliberate arson, inject large pulses of gas and aerosol pollutants into the atmosphere, degrading air quality far downwind of the burned area. Reconstructing the resulting ground-level particulate fields for a specific event joins fire perimeters and ignition-cause records, meteorology, atmospheric composition reanalysis, and emission inventories with a heavy dispersion stage, and is prohibitively slow when assembled ad~hoc. We present a workflow that delivers this analysis on demand: a directed acyclic graph (DAG) expressed in the DagOnStar engine, exposed as a Workflow-as-a-Service, with tasks mapped elastically onto edge, local, HPC, container, and cloud resources, and every input and artifact recorded in a provenance graph that yields FAIR outputs. At the dispersion core sits Spritz, a new clean-room Python3 re-implementation of the CALPUFF suite that provides a Lagrangian formulation of atmospheric transport through a puff- and particle-based representation of tracer evolution. The model adds NetCDF-CF interoperability, MPI parallelism, and a pip-installable orchestration entry point. On a representative regional workload, the makespan shrinks by more than an order of magnitude from one to sixty-four concurrent workers, with parallel efficiency above $60\%$ up to sixteen workers.

14:00-15:30 Session 7C: Workshop EuroQHPC 3
Location: Room A1
14:00
Distributed VQE: Embarrasingly Parallel strategies on NISQ

ABSTRACT. Variational Quantum Eigensolver requires many circuit executions, making it ideal for distributed parallelization. However, heterogeneous noise in NISQ devices can skew results and efficiency. Using the CUNQA platform for emulation of virtual QPUs, we evaluate three embarrassingly parallelization strategies - shot-level, circuit-level for gradients and observables, and candidate level for population-based optimizers — across metrics like speedup and accuracy.

14:30
Implementing an Entanglement-Agnostic DEGGA via Virtual Quantum Communication using CUNQA

ABSTRACT. Quantum computing faces critical scalability bottlenecks in the Noisy Intermediate-Scale Quantum (NISQ) era, motivating the development of Distributed Quantum Computing (DQC) architectures. Recent algorithmic advances, such as the Distributed Exact Grover Algorithm (DEGA) and its generalized version (DEGGA), propose mathematically partitioning the search space across multiple Quantum Processing Units (QPUs) without relying on quantum communication. However, these purely algorithmic decompositions struggle when multi-target searches generate highly entangled global states that cannot be cleanly factored into independent local registers. In this paper, we propose an entanglement-agnostic physical architecture for DEGGA utilizing network-assisted quantum communication to overcome these limitations. By leveraging CUNQA, an open-source DQC emulator deployed on High-Performance Computing (HPC) infrastructure, we execute remote multi-controlled phase gates via the virtual entanglement protocol Telegate. Through this approach, we demonstrate the successful dynamic orchestration of concurrent multi-qubit exposures across the network boundary. We show that by explicitly allocating the necessary physical entanglement resources, the virtual quantum channel natively stabilizes both symmetric and asymmetric topologies without requiring manual algorithmic refactoring. To validate this approach, we successfully executed multi-target exact distributed searches scaling up to 15 logical qubits with a 100% deterministic success rate, seamlessly preserving global entanglement.

15:00
Approximate Quantum State Preparation Through Proximal Policy Optimization

ABSTRACT. In this work, a quantum architecture search framework for approximate quantum state preparation (QSP) is proposed. QSP is a challenging task, since the search space grows exponentially with the number of qubits, making the identification of the optimal circuit non-trivial. To address this problem, deep reinforcement learning is employed through an agent based on proximal policy optimization. The objective of the agent is to identify the best possible approximation of the target state while simultaneously minimizing the number of gates used. At each step, the agent appends a new gate to the circuit and recomputes the fidelity between the approximated state and the target states. Various experiments have been performed from 2 to 5 qubits. Both predefined states, such as Bell, GHZ, W, and Dicke states, and completely random states are considered. The proposed framework is able to achieve approximation errors of $10^{-14}$.

14:00-15:30 Session 7D: Workshop FRAME 3
Location: Room C1
14:00
Controlling Fragility: Governance-Driven Spectral Dynamics for Phase Transitions in AI System Risk
PRESENTER: Songhee Kang

ABSTRACT. Artificial intelligence systems are typically optimized for average-case efficiency, yet they often become fragile under rare, high-impact disruptions. We frame this fragility not simply as an anomaly detection problem, but as a core challenge in algorithmic risk governance. To address this gap, we introduce the 3C (Chance, Choice, Change) framework, which models systemic risk as sto- chastic event dynamics shaped by organizational accountability. To operational- ize this perspective, we propose Seq-LAMFNO, a backbone-agnostic predictive architecture with a regime-conditioned Lorentzian spectral residual branch. Ra- ther than relying on static filters, Seq-LAMFNO uses a hypernetwork to adapt spectral dynamics to governance-conditioned risk states. When risk intensity crosses critical thresholds, the model shifts its focus from local operational effi- ciency to global precursors of system-level instability. Empirical evaluation on a cloud-edge benchmark shows that Seq-LAMFNO outperforms static sequential baselines in both event prediction and structural risk estimation. In addition, high- resolution sensitivity analysis reveals that the decision boundary lies near a highly unstable regime, supporting the need for dynamic control under phase- transition-like risk conditions. By tuning governance parameters, decision-mak- ers can explicitly shape non-linear response behavior, turning AI from a passive forecasting component into a controllable governance layer for resilient system operation.

14:30
A BLP Model for User-Centric Serverless Edge Container Placement
PRESENTER: Hanna Kavalionak

ABSTRACT. This paper presents a user-centric Binary Linear Programming formulation for serverless edge container placement. The model jointly optimizes container placement and request assignment under storage, processing, budget, and latency constraints, while accounting for warm- and cold-start execution. Its objective is to maximize the number of users whose average request latency satisfies a predefined threshold. We evaluate the model using Azure Functions workload traces combined with a synthetic edge environment. The results show that optimized placement can improve user satisfaction, but its effectiveness is strongly affected by the initial system configuration and edge-node resource constraints. In particular, uninformed initial placement may consume scarce resources at poorly located nodes, limiting the optimizer’s ability to place useful containers where they are needed. These findings highlight the importance of informed initialization and motivate future work on adaptive and scalable placement strategies.

15:00
Accelerating Dynamic Graph Clustering on GPU Architectures with cuGraph

ABSTRACT. This work addresses community detection in temporal networks through GPU-accelerated extensions of spectral clustering and modularity-based algorithms originally designed for static graphs. Based on the RAPIDS ecosystem, the proposed framework enables the characterization and tracking of communities in snapshot-based temporal graphs by Leiden greedy optimization with support for multi-GPU execution via Dask-based workload distribution, or ratio cut minimization on a supra-graph encoding temporal dependencies. Our approach achieves substantial speedups over CPU-based execution while preserving compatibility with existing graph analytics pipelines. We demonstrate its applicability on real-world temporal network datasets, facilitating exploratory analysis of structural network properties over time. Such capabilities are relevant across several application domains, such as epidemic spreading, financial systems, cybersecurity, and trajectory and mobility analysis. We release our implementation as open-source software, including Python bindings through the NetworkX-Temporal library for ease of use and zero-code integration with existing workflows.

14:00-15:30 Session 7E: Minisymposium PEPSC 3
Location: Room B1
14:00
Accelerating Gyrokinetic Turbulence Code GENE-X on GPUs
PRESENTER: Jordy Trilaksono

ABSTRACT. Digital simulations hold critical roles in paving the road to the commercialization of fusion energy. The gyrokinetic code, GENE-X, simulates the plasma turbulence in any regions of a fusion device or reactor from the core to the edge. GENE-X is aimed to discover mechanisms and the correct conditions for fusion plasma to produce net-positive energy. Such large-scale rector-relevant simulations require massive computing resources, such that accelerating the code is critical to keep the cost realistic. This includes GPU acceleration to all GENE-X kernel and optimization of the performance hotspot of the code.

Field solver is one of the major performance hotspots in GENE-X as it is reduced to three-dimensional configuration space from the five-dimensional phase space. In this study, we accelerate the field solver with the application of NVIDIA AMGX library on GPU with algebraic multigrid preconditioner. We further exploit the data dependency in GENE-X solving procedure to apply concurrent solving of quasi-neutral equation and Ampere’s equation. Finally, we apply a field-extrapolated Runge-Kutta time scheme to skip the intermediate field evaluation in the time integrator. With these optimisations, we speedup the field solver by a factor of four in a typical production benchmark case.

14:50
In-Situ Techniques for GENE-X

ABSTRACT. The increasing scale of plasma simulations makes traditional post hoc analysis increasingly inefficient due to the high cost of data movement, storage, and offline processing. In-situ techniques address these challenges by performing analysis and visualization while the simulation is running, reducing I/O overhead and enabling faster scientific insight.

This work presents a comprehensive study of in-situ techniques for the gyrokinetic plasma simulation code GENE-X. First, we compare two in-situ coupling frameworks, ADIOS2 and preCICE, for integrating GENE-X with ParaView and evaluate their suitability for in-situ visualization. Next, we propose a dynamic resource management strategy for asynchronous in-situ visualization, allowing visualization tasks to execute concurrently with the simulation while adapting computational resources to minimize resource utilization. Finally, we develop an in-situ coupling framework between GENE-X and the local flux tube using code GENE, enabling global GENE-X simulations with lower resolution.

Together, these contributions demonstrate how modern in-situ techniques can improve the efficiency and scalability of plasma simulation workflows by reducing data movement, overlapping computation with analysis, and enabling tightly coupled multi-code simulations on large-scale HPC systems.

15:30-16:00Coffee Break
16:00-18:00 Session 8A: Workshop HeteroPar 4
Location: Room B
16:00
SYCL-HD: Parallel Framework for Hyperdimensional Computing
PRESENTER: Leonel Sousa

ABSTRACT. Hyperdimensional computing (HDC) is an emerging, brain-inspired approach for machine learning classification, offering significant efficiency gains while maintaining competitive accuracy. However, existing HDC frameworks often lack portability and support for heterogeneous systems, limiting their ability to fully leverage the diverse range of accelerators from different vendors. In this paper, we address this gap by introducing SYCL-HD, a multi-platform, highly parallelized framework that enables precise execution of HDC applications from a unified program. We demonstrate that SYCL-HD outperforms existing state-of-the-art HDC libraries, achieving up to 2x improved performance compared to an optimized CUDA implementation and 17x compared to TorchHD.

16:30
Parameter Savings Are Not Memory Savings: Butterfly Attention on a Tile Processor

ABSTRACT. Replacing dense weight matrices with structured factors cuts parameter count, but on accelerators that compile the whole model graph ahead of time, parameter count is a poor predictor of on-chip memory use. We compare butterfly attention against dense attention on an NVIDIA A30 GPU and a Graphcore GC200 IPU, using a stack of attention layers at the long-context, small-vocabulary shape that arises in DNA k-mer modeling. Butterfly has 88% fewer parameters at d_model=128 but runs 8.8x slower on GPU, because its sequential stages cannot keep dense GEMM kernels busy. On IPU the slowdown shrinks to 1.3x. At long sequences, butterfly runs out of IPU memory before dense does, even with far fewer weights: which configurations fit within on-chip SRAM is decided by the size of the compiled computation graph, not by the weight count. Butterfly is therefore beneficial on IPU in a wide-shallow regime (d_model >= 512, L <= 4): 88-98% fewer parameters at 30-40% inference latency overhead. As a task-level validation, training butterfly from scratch on a synthetic binary classification task over k-mer-tokenized DNA sequences reaches 97.8% test accuracy against 97.9% for dense, and an open-source PyTorch implementation of butterfly attention is released as sparse-layers on PyPI.

17:00
Latent Motifs Discovery via Matrix-Accelerated IMF Modeling using GPU Tensor Cores

ABSTRACT. Residual signals in gravity-field estimate pipelines are often seen as random modeling error, despite their structured temporal behavior from orbital dynamics, external disturbances, and the lack of accuracy in physical models. An unsupervised framework for discovering recurring temporal motifs in case study dataset from Gravity Recovery and Climate Experiment (GRACE)/GRACE Follow-On (GRACE-FO) range-rate residuals is proposed using hierarchical similarity-mining. The suggested method uses Empirical Mode Decomposition (EMD), Hilbert domain analysis, and high-order cross-Intrinsic Mode Function (IMF) interaction modeling to provide compact temporal-state representations for nonlinear multiscale residual dynamics. Large-scale motif identification mapped to matrix multiplication units. Experiments show that increasing interaction order transforms latent similarity fields into particular recurring patterns, such as eclipse-related orbital routes. The findings show that high-order state interaction spaces are nonlinear structural amplifiers that reveal latent residual organization that first-order representations cannot. Experimental evaluation achieves efficient execution, demonstrating that the proposed method is suitable for exploration of the mission-scale widow similarity problems.

17:30
Closing Remarks
16:00-18:00 Session 8B: Workshop HiPES 4
Location: Room C
16:00
Before Malleability: ParaStation MPI Runtime Performance Assessment

ABSTRACT. Malleability is essential in HPC environments because it improves resource utilization, energy efficiency, and workload adaptation. Although MPI was not originally designed with such features, version 4.0 introduced an initial mechanism for removing processes without terminating the application. ParaStation (PSMPI) is an extension of MPICH 4.2.3 based on the PSCOM library, supporting the addition and removal of processes at runtime, enabling malleable MPI jobs. However, before implementing malleability in MPI applications, the literature still lacks evaluations of the potential performance overheads associated with replacing the MPICH communication layer with PSCOM. In this paper, we conducted a comparative evaluation between both implementations to better understand such impacts. In our network experiments, MPICH showed better performance for small message sizes. For application benchmark workloads, the impact of using PSMPI ranged from an 18.99% slowdown to an 8.38% improvement on execution time compared to MPICH.

16:30
Panel Discussion

ABSTRACT. Discussing the vision about the high-performance cloud computing in eScience application

17:15
Closing Remarks
16:00-18:00 Session 8C: Workshop EuroQHPC 4
Location: Room A1
16:00
Practical Considerations for Processing Massive Classical Data via Quantum Oracle Sketching

ABSTRACT. Quantum Oracle Sketching (QOS) offers a theoretical route toward processing massive classical data with exponential space/sample quantum advantages. Its original formulation assumes an online, interactive execution model that is not matched by current batched quantum platforms. We study the practical realization of QOS in this setting through an offline construction, exact fusion for commuting oracle classes, and a DNA sequence fingerprinting case study. Using a Qiskit implementation with ideal statevector simulation and transpilation-based resource analysis, we show that larger stream lengths improve approximation quality but also increase circuit size, while fusion yields useful but limited compression. Offline QOS does not retain the original online space-advantage interpretation on current systems, but remains valuable as a reusable, approximate dataset-level oracle and as a benchmark for studying quantum data access and accuracy-cost trade-offs.

16:30
Workshop Discussion and Closing Remarks
16:00-18:00 Session 8D: Workshop FRAME 4
Location: Room C1
16:00
Panel - The Future of Efficient, Adaptive, and Trustworthy Computing

ABSTRACT. Panelists:

Valeria Cardellini — University of Rome Tor Vergata
Tommaso Cucinotta — School of Advanced Studies Sant'Anna
Patrizio Dazzi — University of Pisa
Carlo Vallati — University of Pisa

17:00
Closing Remarks
16:00-18:00 Session 8E: Minisymposium PEPSC 4
Location: Room B1
16:00
Performance Engineering of a Highly Load-Imbalanced Hybrid-Vlasov Simulation at Scale

ABSTRACT. Vlasiator is a space plasma simulation code in hybrid-kinetic approximation. In contrast to the state-of-the-art particle-in-cell simulation approach, it followed the deliberate design decision to operate directly on the Eulerian discretization of 6D phase space. Its scientific applications encompass the entirety of near-Earth space, including ionospheric, magnetospheric, magnetotail, shock and foreshock physics.

In choosing to discretize the 6-dimensional phase space density directly, Vlasiator requires a number of extreme optimizations to tackle the otherwise completely infeasible computational scale of the problem: Sparse grid techniques, dynamic load balancing, adaptive mesh refinement and cutting-edge data compression techniques are being employed to fit the domain onto current-generation supercomputers.

This presentation will present the path from the conceptually simple and elegant (but extremely resource-hungry) Vlasov simulation approach to the stack of optimization tricks that make 6D hybrid-Vlasov simulations of near-Earth space feasible.

16:40
MPI Pancake: Improving Communication Overheads in Large-Scale Hybrid-Vlasov Simulations

ABSTRACT. Vlasiator is a hybrid-kinetic plasma simulation code for near-Earth space research. Its large memory- and computing power requirements necessitated that it, like many other simulation codes, has been extended to support hybrid computational platforms with CUDA and HIP support on GPUs.

As part of the porting process, we encountered great difficulties in getting suitable performance in GPU-to-GPU MPI communication, as the codes’ sparse grid implementation exposes the MPI communication system to vast memory-scattered transfer requests, implemented through a hierarchy of nested MPI data types. The MPI implementations of all major vendors failed to properly accelerate these requests, instead resorting to collating transfer buffers on the host side and re-distributing the data after completion.

To facilitate high-performance GPU-to-GPU MPI communication with memory scattered contents, we devised the "MPI Pancake", an LD_PRELOAD able library that automatically flattens complex MPI data type sends and receives into continuous transfer buffers on-device. This library is, in principle, application agnostic.

In this talk, we present both implementation details and performance results from Vlasiator and encourage experimentation for all other code authors suffering from low-performance GPU-to-GPU transfers.

17:20
Panel - Pushing Lighthouse Plasma Simulation Codes to Tackle Exascale-Enabled Grand Challenges
17:50
Wrap-up & Closing Remarks