ABSTRACT. The paper presents a model for I-V characteristics of RRAMs based on Ni/HfO2/Si-n+ structures that can be easily implemented in SPICE. It describes the successive formation and rupture of one or several conductive filaments which are responsible for their behavior. For each filament an equivalent circuit is built upon a flux-controlled memristor model whose relationship between the charge and the flux has been particularized to fit the experimental results. The model describes almost perfectly the I-V characteristics during the set and reset operations in quasi-static regime, using a set and a reset fluxes as fitting parameters. However, further work is needed to extend the model to dynamic operation. Experimental work is underway to refine the relationship between the set and reset fluxes and the input rise rate.

ABSTRACT. This paper addresses the role played by the voltage ramp rate in the reset transient of resistive switching TiN/Ti/HfO2/W devices. The reset parameters extracted from experimental current-voltage (I-V) characteristics were analyzed in the charge-flux domain typical of memristive structures. The obtained results allowed proposing an analytic expression for the reset voltage as a function of the ramp rate. This relationship was included in the memdiode model for the SPICE simulator. Close agreement between simulations and experimental results was achieved.

ABSTRACT. The resistive switching behavior of Ta2O5:ZrO2-based metal-insulator-metal devices was studied. Asymmetrical and repetitive current-voltage loops were observed. Excellent control of admittance parameters in the intermediate states between the high and low resistance ones was achieved, demonstrating suitability to analog and neuromorphic applications. Admittance memory cycles provide relevant information about the switching mechanism, in which the existence of two different metallic species in the dielectric seems to play an important role.

ABSTRACT. Memristors in neuromorphic circuits typically need to drive currents of many mA because their Low Resistance State (LRS) is in the order of a few kohm and many devices need to be activated simultaneously which results in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a three-stage cascaded calibration scheme to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array read-out systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV – only limited in practice by mismatch and electrical noise. The circuit has been designed in 130nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are shown to validate the presented calibration technique

ABSTRACT. Connecting all electronic systems around the world in order to intercommunicate their data is called the Industrial Internet of Things (IIoT). Presently, more and more industrial factories are generating complex information systems that integrate sensors, processors and communication; as a result, intelligent companies, smart grids and even smart cities have been created and, subsequently, IIoT expanded. For this purpose, the authors have designed a skillful gateway, implemented on an All Programmable System-on-Chip (SoC), that faces Cyber-Physical Production System requirements. Developments like this simplify sourcing applications for remote monitoring and automation, M2M solutions, industrial networking and advanced data acquisition infrastructures, focused on Big Data analysis.

ABSTRACT. The EnviGuard Port is an embedded system developed in the framework of the EnviGuard FP7 Project, which serves as the gateway and network coordinator for a distributed ocean monitoring system. As a gateway, the EnviGuard Port collects data from different chemical contaminants and biohazards sensors, and after including date-time and geo-localization stamps, data are transmitted to a web server, whenever a GPRS or 3G connection is available. As the network coordinator, the port module is a core element for the unattended operation of the monitoring system: it periodically triggers sensor measurements, while reporting to the web server any error detected on them. Apart from this, the proposed module contributes to the ease of deployment and the flexibility of the monitoring system. The software and hardware design of the Port Module, as well as the proposed operation scheme of the whole monitoring network, are described in this paper.

ABSTRACT. Wireless sensor networks have become one of the most productive and cost-effective way of gathering data in a distributed and unattended fashion from the environment, and are considered a key technology of the twenty-first century in the field of pervasive systems, indeed contributing in the implementation of Internet-of-Things based ecosystems. However, the wide range of different hardware and software platforms, communication capabilities and data management techniques, certainly makes the integration of heterogeneous technologies a must, so that the final success of the target deployment and the underlying service provision can be assured. In this way, the combination and interoperation of wearable technologies with wireless sensor networks is demonstrated in this work towards the implementation of urban collaborative sensing, particularly considering a twofold integration process: seamless connectivity among wireless mobile and deployable devices, as well as hardware-software embedded support for dynamic interaction with sensing/service capabilities.

ABSTRACT. This paper presents an ultrasonic communication system based on piezoelectric transducers for monitoring ambient parameters in cargo containers. The proposed system consists in several sensors placed inside the container, whose data are collected and transmitted outside the container. Transmission is carried out by an ultrasonic communication channel, in order to avoid drilling the surface of the container. An experimental characterization of the metallic channel for two transducer-metal coupling methods is performed. Depending of the different channel responses of the employed methods, two different communication systems are proposed. Their main advantages and drawbacks are presented, as well as an experimental comparison of different modulation schemes in terms of BER and power consumption.

ABSTRACT. Quantum computers may revolutionize the field of computation by solving some complex problems that are intractable even for the most powerful current supercomputers. This paper describes the basic concepts of quantum computing and quantum error correction (QEC) and discusses the different engineering challenges when building a quantum computer, that includes: 1) scalable quantum processors, 2) the need for conventional control logic close to the quantum processor, implying CMOS operating at cryogenic temperatures, and 3) overall system architecture.

ABSTRACT. We explore the advantages, in terms of device reliability of the use an asymmetric SET to implement SET-based circuits. To extend their use towards little nanometer level FinFET device is explored as a suitable option to implement the hybrid SET-FET circuits. A low variability level (<10%) of the FinFET-based SET-FET circuit is achieved, with high circuit integration level. The vertical SET structure appears as a suitable device configuration for other SET-based circuits, such as NDR and logic inverters.

ABSTRACT. The development of specific hardware realizing machine learning algorithms such as artificial neural networks (ANNs) is crucial to achieve fast, efficient and reliable implementations of these models. In this work, we propose the use of stochastic computing (SC) to implement echo state networks (ESNs) with limited hardware resources. The resulting design is applied to the classification of temporal patterns under noisy conditions showing a high robustness to soft errors.

ABSTRACT. This paper presents a new process for 3D circuit fabrication based on two main steps: additive manufacturing of the plastic or ceramic substrate, through a stereolitographic 3D printer, and a copper electroless plating metalization process. Some of the available printable materials have been characterized in order to find permittivity and losses of the dielectrics. The metalization part has also been evaluated by measuring the square resistance of different samples. The capabilities of the process have been demonstrated with a full-3D circuit.