ABSTRACT. Graphics Processing Units (GPUs) are platforms very appropriated to accelerate processes with high computational load, like the supervised classification of hyperspectral images. The supervised classifier Random Forest has proved to be a good candidate to classify hyperspectral images and currently constitutes an emerging technology for medical diagnosis. The objective of this paper is focused in the Random Forest training phase acceleration using GPUs, starting from an efficient CPU implementation. For some applications, it is necessary to refine the classification model depending on the new acquired samples. In this paper are presented solutions for two bottlenecks identified in the training stage in order to accelerate the algorithm. The different solutions for the bottlenecks provided in this research study have demonstrated that GPU implementation is a promising technique to generate models in shorter time. With this implementation it is possible to achieve the training process in real-time.

ABSTRACT. In this paper, a study of the parallel adaptation of a spatial-spectral classifier which consist of a Principal Component Analysis (PCA) algorithm, a Support Vector Machine (SVM) classifier and a K-Nearest Neighbors filter, running on a Massively Parallel Processor Array (MPPA) platform –a system that joins 256 cores distributed among 16 clusters–, is presented. This research work is aimed at exploiting the MPPA platform potential to implement in parallel these algorithms, so as to minimize the required time to analyze a hyperspectral image. The spatial-spectral classifier algorithm is intended to discriminate between cancer and normal tissues during neurosurgical procedures. Experimenting with medical brain images captured in one operating theater, the processing time measured when parallelizing the processing chain has been compared to the one obtained when executing them sequentially. As a result, an average speedup of more than 140x has been achieved. Consequently, the hyperspectral images are processed in less than a 4% of the available time, considering this time as that required for the hyperspectral sensor to capture a new image.

ABSTRACT. During the last years, the market of embedded vision-based systems has been growing at an accelerated rate. Virtual and augmented reality has the potential to become one of the most innovative technologies for the next decade. One of the most important aspects of these technologies is related to the spatial location of objects or people in defined environments, for which there are several techniques. One of the most widely used is based on visual marker recognition. The main problems of these approaches are related to the accuracy, the changing environments, the processing time, the operating range/distance and the price. The popularization of these technologies produces a pull effect toward the companies developing the best technology at the lowest price. This paper proposes a marker design and an algorithm to detect the markers under different ambient conditions, with a long range to be executed on embedded systems with low computational requirements. The proposed method reduces the existing problems in the state-of-the-art related to the use of different environments and conditions such as different distances or different illumination. Moreover, the requisites of the method are minimal to reduce the cost of deployment.

ABSTRACT. This paper describes a hardware proposal to speed up the process of image matching in stereo vision systems like those employed by autonomous mobile robots. This proposal combines a classical window-based matching approach with a previous stage, where key points are selected from each image of the stereo pair. In this first step the key point extraction method is based on the SIFT algorithm. Thus, in the second step, the window-based matching is only applied to the set of selected key points, instead of to the whole images. For images with a 1% of key points, this method speeds up the matching four orders of magnitude. This proposal is, one the one hand, a better parallelizable architecture than the original SIFT, and on the other, a faster technique than a full image windows matching approach. The architecture has been implemented on a lower power Virtex 6 FPGA and it achieves a image matching speed above 30 fps.

ABSTRACT. A nonlinear electromechanical model for a CMOS-MEMS microbeam and its tuning procedure through the thermal effect is exposed in this work and compared with experimental results as a way to state the conditions to achieve bistability. Furthermore, the bistable behaviour of a submicrometer scale CMOS-MEMS resonator is experimentally demonstrated for first time as far we know.

ABSTRACT. We analyze experimentally the noise-matching capabilities of fully integrated CMOS-MEMS resonators to determine the system noise-limiting element. Measurements from four MEMS resonator geometries designed for ultrasensitive mass detection operating between 2-MHz and 8-MHz and monolithically integrated with a low-noise CMOS capacitive readout circuit are analyzed. The CMOS-MEMS system provides unprecedented detection resolution of 0.15 yF Hz-1/2 equivalent to a displacement resolution MDD of 0.35 fm Hz-1/2, enabling noise-matching that is experimentally demonstrated by thermomechanical noise detection and compared with theoretical model values.

ABSTRACT. In this paper we present the design of a differential CMOS amplifier for sensing the movement of embedded CMOS-MEMS resonators. This amplifier has been designed towards high gain, low noise and wider output range. Design parameters together with the simulated and experimental results demonstrate the benefits of this amplifier in comparison with previous integrated systems.

ABSTRACT. In this work, we present a digital implementation of a True Random Number Generator (RNG) combining a Boolean chaotic circuit and a Linear Feedback Shift Register (LFSR). The proposed methodology has been fully implemented on a Field Programmable Gate Array (FPGA). The chaotic system guarantees the uncertainty of the bit generation while the uniformity of the distribution is guaranteed by the LFSR. The complexity of the sequences is exponentially increased by performing the negation and permutation operations to the output bit string, and by refreshing the LFSR seed. The system has passed the NIST random tests by using a LFSR with only 8 registers. This scheme is a useful tool when implementing stochastic computing systems in which uniform and uncorrelated sequences are needed. The configuration of the proposed model can be adapted to any particular application, by adding more or less complexity.

ABSTRACT. Software-based Self-test (SBST) is one of the techniques adopted to detect latent faults in safety-critical applications, thus aiming at preventing them from producing failures. When adopted for in-field test, not only the achieved fault coverage, but also the test duration of SBST test programs become critical parameters. Sometimes, these test programs are created following guidelines allowing to guarantee a given Fault Coverage with reduced test duration. In other cases, existing test programs are re-used. Hence, it is important to devise automatic techniques able to modify them in such a way that the fault coverage is kept unchanged (or increased) while the test duration is reduced. This paper presents a possible approach in this direction. Its effectiveness is evaluated on some test programs targeting the openMSP430 processor. Experimental results show that the proposed method is able not only to significantly reduce the test duration (up to 26%), but also to further increase the achieved Fault Coverage, while keeping the required computational time acceptable.

ABSTRACT. Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming mostly popular because it presents major speed and implementation compactness compared to other public-key technologies. Calculations, however, cannot be executed in the same microprocessor since it would take unacceptable long time and commonly a co-processor (ECC-core) is included to accelerate the speed.

Test infrastructure in crypto-cores is often avoided because it poses serious security holes against adversaries. However, ECC-cores include complex modules for which only functional test methodologies are unsuitable, thus they would take unacceptable long time during production test. Therefore, some internal test infrastructure is always included to permit structural test techniques being applied.

Designing a secure test infrastructure is a quite complex task that relies on designer's experience and on trial \& error iterations over different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore prototypes are prepared using FPGAs. In this paper a Crypto-Test-Lab is presented which includes an ECC-core with flexible test infrastructure whose purpose is to facilitate the design and validation of secure strategies for test in these types of cores.

ABSTRACT. Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One of the most powerful techniques to compromise the correct functioning of a device are fault injection attacks. They enable an active adversary to trigger errors on a circuit in order to bypass security features or to gain knowledge of security-sensitive information. There are several methods to induce such errors. In this work we focus on the injection of faults through the electromagnetic (EM) channel. In particular, we document our efforts towards building a suitable platform for EM pulse injection. We design a pulse injection circuit that can provide currents over 20~A to an EM injector in order to generate abrupt variations of the EM field on the vicinity of a circuit. We validate the suitability of our platform by applying a well-know attack on an embedded 8-bit microcontroller implementing the AES block cipher. In particular, we show how to extract the AES secret cryptographic keys stored in the device by careful injection of faults during the encryption operations and simple analysis of the erroneous outputs.

ABSTRACT. We present the experimental results obtained by using a pulsed laser to induce transient events on a circuit consisting of chains of logic gates. The data obtained is used to validate an SET propagation model developed in a previous work.

ABSTRACT. Abstract— SEEs (Single Event Effects) are a major concern in electronic circuits, where high levels of reliability are demanded. These effects are provoked by the strike of a single radiation particle on the device, and an accurate estimation of their impact on the failure rate is mandatory. SEUs (Single Event Upsets), which are sudden bit flips provoked by a single radiation strike, are the most relevant SEE in FPGAs, since a flip in the configuration memory alters the implemented circuit. SEU emulation is considered an appropriate technique for characterizing the SEU tolerance of the configuration memory of FPGAs. SEUs can provoke single or multiple upsets. However, SEUs have traditionally been considered as SBUs (Single Bit Upsets) by emulation platforms, since the probability of MCUs (Multiple Cell Upsets) has been considered as negligible. Nevertheless, the continuous device shrinking has brought smaller memory cells, increasing the likelihood of multiple events. In this work a SEU emulator for MCUs is presented, and its effect is compared to an approach considering MCUs as independent SBUs.

ABSTRACT. In this paper, the design of a Power-On-Reset (POR) IP block for RD53 collaboration (Pixel Readout integrated Circuit for Extreme Rate and Radiation) is presented. The aim of this collaboration is the design of a pixel Read Out Chip for the High Luminosity Large Hadron Collider (HL-LHC) project. The POR has been designed taking into consideration Radiation Hardening By Design (RHBD) techniques in order to survive in the HL-LHC tracker radiation environment, with expected ionizing dose of 500 Mrad during full operation. The presented circuit has been analyzed using an automatic SEE sensitivity tool (AFTU) designed by our group, and also tested in several experiments performed to obtain the final IP qualification.

ABSTRACT. The effect that a soft error can produce on an instruction is determined by the Instruction Set Architecture (ISA). It has been shown that the instruction encodings have some intrinsic capability of error detection depending on the Hamming distance among instructions. For example, a soft error can change an instruction and produce an invalid code or can produce an instruction having a high probability of triggering an exception. This means that different bits of the ISA may be more sensitive to errors than others and thus have a higher percentage of error detection. This idea has been exploited in our previous work by introducing a simple encoding of the instructions that increases error detection by propagating an error to the most sensitive bit of the ISA. This paper presents a generalization of our previous technique that considers more than one error propagation bit to optimize error detection and encoding delay. This technique has been evaluated on the ARM Cortex-M0 Thumb ISA giving an error detection improvement up to 1.11x

ABSTRACT. Configuration memory bits in SRAM-based FPGAs contain information about both logic and routing resources. Consequently, if a single event upset (SEU) is induced in an SRAM cell, the loaded design functionalities can change permanently. The number of logic and routing configuration bits can be modified by changing the position of the design and the input/output resources, therefore, an optimal SEU-minimizing design placement can be achieved. In this paper, some guidelines for fault-tolerant design placement in SRAM-based FPGAs are presented. The guidelines are obtained from several placement tests in which the entire design is positioned in different FPGA regions. These experiments show that, with the proposed guidelines, significant SEU reductions can be accomplished.

ABSTRACT. In this work, an experimental framework for the characterization of various reliability effects in modern CMOS technologies is described. The main element in this framework is a versatile transistor array chip, designed to accurately characterize process variability, Random Telegraph Noise and BTI/HCI related time dependent variability effects. The measurement setup, the other element in the framework, has been designed to take full advantage of the array architecture, which allows parallel testing of its 3136 MOS transistors, thereby reducing considerably the total measurement time. Thanks to a control toolbox and a user-friendly GUI, the setup also facilitates the programming of any of the required characterization tests.

ABSTRACT. With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability (i.e., spatial or process variability) but also the degradation due to time-dependent variability (i.e., aging). While process variability has been extensively treated, solutions to cope with aging-related problems are, nowadays, not yet mature enough, especially in the field of analog circuit simulation. Nevertheless, considerable efforts are currently being made to develop new simulation tools and simulation methodologies to evaluate the impact of reliability effects. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

ABSTRACT. Gate oxide breakdown (GOBD) degrades the performance of SRAMs. In this paper, a modeling methodology for SRAM reliability degradation due to GOBD is implemented with a compact current model. SRAM lifetime is obtained from Monte Carlo simulations while considering the stress probability distribution and process variations. We analyzed the lifetime distribution and failure rate of SRAM cells under different stress, and found that the data cache with a duty cycle distribution closer to 50% has a lower failure rate. Moreover, the effect of Error Correcting Codes (ECC) is also studied.

ABSTRACT. This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown, GTDDB, but also the newly emerged wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown, MTDDB. A lifetime assessment flow for both analog and digital circuit is proposed for target wearout mechanisms; moreover, the optimal accelerated test conditions for those mechanisms are presented. To perform circuit-level accelerated life test, optimal condition varies for analog and digital circuit and needs to be carefully considered before conduct the test. Only the test in the optimal region will be able to reflect target wearout mechanism and the degradation. In this way, circuit designer can use that information to redesign their circuit in a more robust and reliable way.

ABSTRACT. Testing of analogue and M-S circuits using octree encoding in an alternate measurements space has been shown effective to detect parametric failures. In this paper, the analysis of the viability to use octree encoding to detect catastrophic faults has been explored. In addition to the classical short and open defects, the class of controlling open faults causing unpredictable behaviour have been considered. In this category, fall some opens causing floating gate defects where the high impedance node gets a voltage imposed by the capacitive coupling of surrounding lines and possible leakage currents to the floating node. The method has been applied to a Biquad filter where a wide class of catastrophic defects (shorts, path opens and floating opens) have been injected. Parametric and catastrophic failures were detected using the same alternate test procedure achieving significant savings in test application time. The results show that with a simple octree based on two indirect measures detectability was guaranteed for all shorts, and path opens. A significant number of floating gate opens is also detectable. The floating gate defects escaping assured detection would be those in which the floating gate during test excitation produces voltages at the open gate(s) similar to the voltage of the non-defective circuit.

ABSTRACT. This paper presents a wide-input, fully-integrated switched-capacitor voltage regulator with multiple conversion ratios (CRs) for ultra-low-power sensor applications. An unit cell with one flying capacitor and five power switches is designed to realize buck/boost conversion with low system complexity. Detailed power loss breakdown of the unit cell assists to optimize the power devices for high efficiency. With three buck/boost unit cells, 11 buck and 11 boost CRs are achieved. For the input range from 0.2V to 5V, hysteretic controller is used to well regulate the output voltage at 1.2V. The proposed switched-capacitor voltage regulator supports the maximum load current of 10mA and 80.5% peak efficiency.

ABSTRACT. A folded cascode Operational Transconductance Amplifier (OTA) suitable for low-voltage low-power operation is presented. Dynamic performance is not degraded by the low static power consumption thanks to adaptive biasing techniques, which provide power-efficient class AB operation. Measurement results of a test chip prototype fabricated in a 0.5um CMOS process show an increase in slew rate and GBW by a factor of 30 and 9, respectively, versus the conventional folded-cascode OTA using the same supply voltage and bias currents. Overhead in area, noise, and static power consumption, is minimal.

ABSTRACT. This paper presents a low power CMOS RF second-order all-pass filter (AFP) as a time delay cell. The proposed filter benefits from a simple structure; consisting of one transistor, three resistors, and one grounded capacitor and inductor. The filter reaches to a group delay of 60 ps over a 10 GHz bandwidth, while achieving maximum delay-bandwidth-product (DBW) and it consumes only 1.91 mW power. On the other hand, an active inductor is used in the AFP instead of a passive RLC tank in order to control the time delay and improve the size. In this case, the proposed AFP consumes 5.59 mW power while its time delay can be varied. The proposed AFP is designed and in a TSMC 0.18 µm CMOS process.

ABSTRACT. In this work a new design methodology for the low-power design of switched-capacitors delta-sigma modulators using the recently introduced switched-variable-mirror amplifiers (SVMAs) is presented. The effectiveness of the methodology is demonstrated for a third-order single-loop single-bit delta-sigma modulator employing SVMAs designed in a standard 0.18 um CMOS technology. Results show that the proposed methodology allows for the design of state-of-the-art high-resolution ADCs while greatly boosting design cycles by removing the need for time consuming full electrical simulations.

ABSTRACT. Electronic circuits powered at ultra low voltages (300 mV and below) are desirable for their low energy and power consumption. However, the performance at such low power voltage is severely degraded. FDSOI technology, with its large range of body bias voltages can counteract the performance loss by applying forward body bias to the circuit. For this reason, charge pumps circuits to generate positive and negative body bias voltages need to be integrated on the chip. This paper studies the main challenges in the design of such circuits operating at 300 mV to reach body bias voltages of more than +1/-1 V.

ABSTRACT. Waste Electronic and Electric Equipment (WEEE) is one of the challenges of our time due to the huge amounts generated, specially in the fields of wearables, smart sensors and IoT. The use of reconfigurable electronics to reduce WEEE is investigated in this paper. By using this type of systems it is possible to reduce significantly the number of devices converted to WEEE. As a proof of the utility of this philosophy, some projects using PSoC® are presented.

ABSTRACT. Embedded Systems are widely used in nowadays industry. Since this usage is expected to be maintained or even grow in the near future, the Informatics Engineering Degree includes “Embedded Systems” as a required class in the student’s curriculum. Among other efforts to make the subject both attractive and understandable for the pupils, teachers have developed a robot with different sensor and actuator modules. The design has been focused on producing a robust, cheap and versatile robot. This paper presents our experience with this new platform and shows several implementations carried out by the students.

ABSTRACT. In recent years a large number of degrees have appeared in the scientific-technical field, many of them are engineering degrees. These new emerged engineering degrees are characterized by its transversality and its interdisciplinarity. A clear example is the Biomedical Engineering (BE), a profile that presents an increased demand within the educational, scientific and industrial communities. So, the mixing of different disciplines involves complex teaching approaches of the curriculum courses. In this work, the challenges related to the learning and teaching process with a rapidly evolving discipline like BE is discussed. A Problem-based learning (PBL) methodology is presented to address the issue of multi-disciplinary teaching, in this case applied to basic learning of electronic instrumentation.

ABSTRACT. Hardware acceleration is considered a powerful parallel-computing paradigm, able to overcome the limitations imposed by sequential execution of software applications and, at the same time, provide energy-efficient alternatives to other parallel computing platforms such as GPUs. However, the increasing application complexity makes it unaffordable to map algorithms directly into HDL. Hence, High-Level Synthesis tools can be used to leverage the design of hardware accelerators from high-level programming languages such as C/C++ or OpenCL.

In this paper, the use of High-Level Synthesis tools to generate hardware accelerators for applications with significant data-level parallelism is evaluated. Multiple copies of the same accelerator are used to analyze performance scalability in two different scenarios: high-performance embedded computing, and small-scale datacenter. In the former, Vivado HLS is used to generate accelerators from C and OpenCL code, which are then compared to several software-based multicore alternatives. In the latter, accelerators are seamlessly integrated using SDAccel, and the OpenCL-based description is also used to establish comparisons with other parallel computing platforms (GPUs). Experimental tests show promising results in the high-performance embedded computing scenario, where hardware-based processing outperforms its software-based counterparts. However, the results obtained in the small-scale datacenter scenario show that FPGA-based acceleration using OpenCL is currently no match for high-end GPU devices in certain applications.

ABSTRACT. This works presents an efficient way to design hardware modules on FPGAs using the SystemC framework.This framework permits the description and simulation of a hardware architecture with C++ that can be directly synthesized to VHDL thanks to HLS (High-Level Synthesis) tools. The module selected to be the reference design in this paper is a PI controller. A work-flow for both the design and simulation parts is presented and developed to get the final module well-designed and wellimplemented. This solution provides flexibility in the design: the architecture can be quickly adjusted and the PI coefficients can be changed at run-time among other benefits. Moreover, the final implementation done in fixed-point to save resources of the FPGA is made easier with this work-flow and the designer’s work is simplified by using user-friendly tools for simulation. This way, errors in the design can be detected and corrected at each simulation phase and not only during the final tests. The solution presented in this paper is also applicable to nearly every module to be designed for a FPGA.

ABSTRACT. Over the past decade, High-Level Synthesis (HLS) tools and methods have increasingly become mainstream in the strategy of leading companies in the field of FPGAs. On the one hand, HLS allows FPGA manufactures to widen the target market, smoothing the existing barriers that prevented potential users from adopting reconfigurable hardware technologies. On the other hand, HLS easies the work of system developers who benefit from integrated and automated design workflows, considerably reducing the “time to market” constrain. However, there is still some uncertainty about the quality and performance of the designs that results from the HLS processes. As the HLS tools increase the level of abstraction, it is necessary to evaluate if the incurred performance losses compensate the design time reduction. Therefore, a better understanding of HLS tradeoffs is needed to make the most of this technology. In this paper, an optimization of the high-level synthesis methodology using Vivado HLS is presented. Several options are analyzed for each alternative through the testing of the interpolators used in the Scalable Video Codec (SVC), using the Programmable Logic (PL) of the ZynQ device. Thus, an accurate evaluation on the pros and cons of this implementation is provided to allow the designers making decisions to speed-up their circuits when using this methodology.

ABSTRACT. This paper presents a low power analog front-end designed to be part of an intelligent stent for restenosis monitoring in a distal pulmonary artery. The heterogeneous front-end comprises a capacitive MEMS pressure sensors for the acquisition of physiological signals, as well as 0.18 μm CMOS electronics for wireless device powering and data transmission, performed using the ISM 433.92 MHz band. The architecture includes a voltage rectifier, a voltage reference, a voltage regulator, an oscillator and a MEMS pressure sensor. A modified Sawtooth oscillator has been designed to allow the operation of the system under ramped-voltage biasing signals. Post-layout simulations present a good correlation with the analytical model of the system, showing an average power consumption of 11 μW and a frequency-to-capacitance sensitivity of 0.1569 MHz/pF.

ABSTRACT. This paper describes a low-noise, low-power and fully differential amplifier intended for sensing neural signals. In order to reduce 1/f noise, the amplifier is chopper-stabilized. To palliate the up-modulated dc offset due to chopper-stabilization, an integrator with programmable duty-cycled resistors is implemented. A switched-capacitor common-mode feedback and a low pass filter, carried out using subthreshold-source-follower biquad, guarantee lower power consumption and lower distortion on the circuit. Transistor-level simulations were realized in a prototype designed in a 0.18 um AMS CMOS technology with a 1V supply showing a low power consumption (1.67 uW) and a noise floor of 0.8 uVrms over a bandwidth from 1 to 200 Hz.

ABSTRACT. It is presented a new approach to monitor restenosis in arteries where a stent has been placed during an angioplasty. The growth of neointimal tissue is watched by taking BioImpedance (BI) measurements with electrical impedance spectroscopy circuitry. Besides, a mathematical model is derived to analytically describe the neointima’s histological composition from bioimpedance data. The bioimpedance model is validated by finite-element analysis (FEA) with COMSOL Multiphysics®. Satisfactory correlation between the analytical model and the FEA simulation is achieved for most of the characterization, detecting some deviations introduced by the thin "double layer" that separates the neointima and the blood. It is shown how to apply conformal transformations to obtain bioimpedance models for stack-layered tissues over coplanar electrodes. Particularly, this is applied to characterize the neointima in real-time. This technique is either suitable as a main mechanism of restenosis follow-up or it can be combined with proposed intelligent stents for blood pressure measurements to auto-calibrate the sensibility loss caused by the adherence of the tissue on the micro-electro-mechanical sensors (MEMS).