Keyword:Masking

Papers
Simulation Based Evaluation of Bit-Interaction Side-Channel Leakage on RISC-V Processor Tamon Asano and Takeshi Sugawara In:Proceedings of 10th International Workshop on Security Proofs for Embedded Systems
Multilevel Decomposition of the Envelope for Faults Detection in Gears Amina Benzineb, Hanen Gabzili and Zied Lachiri EasyChair Preprint no. 4955
Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes Inès Ben El Ouahma, Quentin Meunier, Karine Heydemann and Emmanuelle Encrenaz In:PROOFS 2017. 6th International Workshop on Security Proofs for Embedded Systems