WRTLT 2021: The 22nd Workshop on RTL and High Level Testing WRTLT’21 is likely to be organized as a virtual workshop due to the COVID-19 pandemic. Matsuyama, Japan, November 25-26, 2021 |
Submission link | https://easychair.org/conferences/?conf=wrtlt2021 |
Scope
The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. WRTLT'21, the 22nd workshop, will be held in conjunction with the 30th Asian Test Symposium (ATS'21).
Areas of interest include but are not limited to:
- RTL fault modeling, ATPG, DFT, BIST
- High-level fault modeling, testing and synthesis for testability
- Functional fault modeling and test bench generation
- System Level Testing
- 3D IC testing
- SoC/NoC testing, test scheduling, core-based testing, interconnect testing
- Reliable SoC, system level reliability, self-repair, fault tolerant SoC
- Microprocessor testing, design verification
- Low power testing and Test compression
- Hardware trojan detection and secure testing
Submissions
Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper (4-6 pages, two columns). The submission should include title, full name, and affiliation of all authors, 50 words abstract, keywords and the name of contact author, in a standard IEEE two-column format. All submissions are now to be made electronically. Digest of Papers will be handed out to the workshop participants.
Key Dates
- Submission deadline: August 20, 2021
- Notification of acceptance: September 24, 2021
- Camera-ready: October 29, 2021